Docstoc

IEEE full pdf on cmos

Document Sample
IEEE full pdf on cmos Powered By Docstoc
					       A Transmission Gate Flip-Flop Based on Dual-
              Threshold CMOS Techniques

                                                   Linfeng Li and Jianping Hu
                                          Faculty of Information Science and Technology
                                                         Ningbo University
                                                        Ningbo City, China


Abstract—In present CMOS circuits, the power dissipation             Though it can effectively reduce leakage current, the feed
caused by leakage current cannot be neglected anymore. An            back balloon cause large additional dynamic power and area
effective way to reduce the leakage power is dual-threshold          to lead to a penalty of performance. The gate-length biasing
techniques. Low-threshold transistors are assigned to critical       flip-flop is based on the principle that an 8nm increase in gate
paths of the circuits to enhance the performance, while high-        length yields 30% decrease in leakage with a 5% increase in
threshold transistors are assigned to non-critical paths to reduce   delay for a minimum size inverter [7]. However, considering
the leakage current. This paper proposes a new transmission          the balance of the leakage power and the delay, the reduction
gate flip-flop based on dual-threshold CMOS technique to             magnitude of the leakage power is limited.
reduce its leakage power. Simulation results show that the
proposed transmission gate dual-threshold flip-flop saves 20-            In this paper, a new flip-flop based on dual-threshold
30% power and 40-50% leakage power compared with the                 technologies is proposed for delay-constrained circuits. For a
single-threshold transmission gate one and gate-length biasing       logic circuit, a high threshold voltage can be assigned to some
one, respectively. The proposed flip-flop is an excellent            transistors on non-critical paths to reduce its leakage current,
candidate for low-power VLSI designs in deep sub-micro ICs.          while the performance is maintained due to the low-threshold
                                                                     transistors. The proposed flip-flop achieves considerable low
                       I.   INTRODUCTION                             leakage power without additional dynamic power and silicon
    With the growing uses of portable and wireless electronic        area caused by sleep transistors.
systems, reduction in power consumption has become more
and more important in today’s VLSI circuits [1-3]. In CMOS                                 II.    PREVIOUS WORKS
digital circuits, power dissipation consists of dynamic and              A single-threshold transmission gate flip-flop (ST-TG FF)
static components. Since dynamic power is proportional to the        is shown in Fig. 1. ST-TG FF is extensively used in sequential
square of supply voltage VDD, lowering supply voltage is the         systems, thus it is taken as a benchmark circuit for comparing
most effective way to reduce power consumptions as long as           the performances of the flip-flops in this paper. Because
dynamic power is dominant. With the lowering of supply               leakage current increases exponentially, several leakage
voltage, transistor threshold voltage should also be scaled in       reduction techniques for flip-flops have proposed in recent
order to satisfy the performance requirements. Unfortunately,        years. A leakage feedback flip-flop (LFB FF) [9] shown in
such scaling can lead to a dramatic increase in leakage current,     Fig. 2 applies the principles of the leakage feedback gate to a
which become an important concern in low voltage and high            traditional master-slaver flip-flop. The inherent design of the
performance circuits.                                                flip-flop allows this implementation to avoid adding any
                                                                     capacitive load to the nodes on the critical path.
    For sequential circuits, there are several technologies to
                                                                               clk                             clkb
reduce their leakage power. MTCMOS, leakage feed back,
gate-length biasing, and DTCMOS have been applied in flip-                                           M
                                                                        D      T1          I1                  T3          I3            Q
flops [4-9]. MTCMOS technology provides low leakage and
high performance operation by utilizing high speed and low
VT transistors for logic cells and low leakage and high VT                                                                 clkb
                                                                        clkb         T2   clk            clk          T4
devices as sleep transistors [4-6]. However, sleep transistors
cause additional dynamic power and logic cells to slow down                                 I2I                                 I4
during the active mode. The leakage feed back technology is
applied to overcome the problem of holding state during
standby mode by maintaining an active path to one rail [9].             Figure 1. Single-threshold transmission gate flip-flop (ST-TG FF).




     978-1-4244-4480-9/09/$25.00 ©2009 IEEE                      539
                                    VDD                                                      VDD                        I0                    I1                               I3   I5
                                                                                                                               clk                       clkb
           clk     sleep            P1                             clkb         sleepb        P2                                                   M
                                                           M                                                       D           T1                            T3                           Q
     D      T1                      I1                             T2                        I2      Q
                                                                                                                                                                       L4
          clkb     sleepb           N1                I3           clk           sleep        N2

                                                                                                                        clkb          T2     clk       clk        T4         clkb

               Figure 2. Dynamic leakage feedback flip-flop (LFB FF).                                                                                    L3

    The critical path through the LFB FF consists solely of
low-threshold devices. The high-threshold inverters that                                                                                L1
feedback to hold state during the active mode also provides
the feedback for the conditional sleep gating in standby mode.                                                                                                          L2
                                                                                                                                             I2                               I4
It has no extra loading from the feedback mechanism beyond
the load inherent to the latches. During sleep mode, the                                                                         Leakage paths reduced
transistors P1 and N1 are off, and the transistors P2 and N2 are                                                                                                  High-threshold transistors
                                                                                                                                 Leakage paths
on. Therefore, the master stage stores the data value and
propagates it through the low-threshold inverter (I2) in the                                                           Figure 4. Dual-threshold transmission gate flip-flop (DT-TG FF).
slave stage to the output. The sleep devices attached to the
sleep signal all turn off. The other sleep devices (minimum                                                        DT-TG FF consists of two paths, namely non-critical and
sized) conditionally turn off to maintain the correct values at                                                critical. The circuits that hold the state use high-threshold
the internal and external storage nodes. Simulations have                                                      transistors to reduce its leakage current. The performance is
shown that the LFB FF is very favorable in terms of speed and                                                  maintained due to the low-threshold transistors in the critical
power compared to the other MTCMOS flip-flops [9].                                                             path.
    A gate-length biasing flip-flop is shown in Fig. 3, which is                                               A. Power dissipations
implemented with inverters and tri-state inverters. If we
employ gate-length biasing only to those transistors that are                                                     The switching power of an inverter PSW can been
turned off when both D-input and Q-output are low as shown                                                     described as
in Fig. 3, the leakage for those two flip-flop states can be
made very different. The increase of rising delay is larger than                                                                Psw = fVDD 2 (CparW + C wire )                            (1)
that of falling delay since the transistors whose gate length is
increased are sensitized for rising signal. The rising and falling                                             Where the drain and gate capacitive parasitic are
setup time is increased by 34% and 24%, respectively [7].
                 VDD                                   VDD                                                                           C par = 3(C D LD + Cox L)                            (2)
                              VDD                                                                  VDD
                                                                                                               Where CD and LD defines the diffusion capacitance per unit
         clk           E                   F   clkb            G                                               area and the length of diffusion area of a MOS device,
 D                                                                                                       Q
         clkb                                  clk                                                             respectively. COX and L define the oxide capacitance per unit
                                                                                                               area and the drawn gate length, respectively, and Cwire is the
                                                                                                               wire capacitance.
                                                                                                   VDD
                           VDD                                 VDD                                                 Compared with the leakage feedback flip-flop (LFB FF),
                                                                                                               the DT-TG FF doesn’t demand additional MOS devices. The
                                                                                                               performance penalty of a sleep transistor depends on its size
                                    clkb                                  clk
                                                                                         H                     and the amount of current that goes through it. In LFB FF and
                                    clk                                   clkb                                 the other flip-flops using sleep transistors, the high-threshold
                                                                                                               transistors have wider transistors to maintain the performance.
                                                                                                               According to (1) and (2), this will affect the total power
                                                                                    L-biasing device           consumption. Though the leakage feedback flip-flop can
                  Figure 3. Gate-length biasing flip-flop (GLB FF).                                            reduce larger leakage power than the ST-TG FF, the DT-TG
                                                                                                               FF avoids the penalty of the additional dynamic power caused
                                                                                                               by the sleep transistors with large size.
                       III.         DUAL THRESHOLDS FLIP-FLOP
     The proposed dual threshold flip-flop is shown in Fig. 4.                                                     The leakages paths can be analyzed in Fig. 4. When the
Its structure is the same as a single-threshold transmission gate                                              master latch works, T1 is on while T2 is off. When the slave
flip-flop (ST-TG FF), but a higher threshold voltage is                                                        master latch works, T3 is on while T4 is off. T2 and I2 are
assigned to the transistors in the blocks of Fig. 1 to reduce its                                              used to hold the state of node M, T4 and I4 are used to hold
leakage current, which is used to hold the state.                                                              the state of node Q. The leakage of the two paths (L1 and L2)


                                                                                                             540
is reduced due to the inverters (I2 and I4) with high-threshold       Where COX and L define the oxide capacitance per unit area
transistors. The other sneak leakage paths are depended on the        and the drawn gate length, respectively. In long channel
working states. When Q = 1, the leakage of the path (L3) is           devices the velocity saturation parameter, a, is equal to 2.
reduced due to the transmission gate (T4) and the NMOS                However, in cutting-edge processes a approaches 1. It is clear
transistor of inverter (I4) assigned with high threshold. When        that the large device size of high-threshold transistors for
Q = 0, the leakage of the path (L4) is reduced is reduced due         satisfying the delay requirement will cause their switching
to the transmission gate (T4) and the PMOS transistor of              power, which may dominate the leakage power.
inverter (I4) assigned with high threshold. The total leakage
power is reduced greatly. Moreover, no any additional                     The leakage feedback flip-flop is implemented by inserting
dynamic power is caused, because no more transistors are              sleep transistors. Small sleep devices further reduce the
added in the flip-flop.                                               leakage current in standby mode but slow down transitions in
                                                                      active mode, because of the voltage drop across the sleep
B. Delay constraint                                                   transistors.
    There are three important timing parameters associated                Gate-Length biasing involves a small increase in the gate
with a flip-flop. The set-up time tsu is the time that the data       lengths of devices. In a 130-nm industrial process, it is
inputs (D) must be valid before the clock transition. The hold        reported that an 8nm increase in gate length yields 30%
time thold is the time the data input must remain valid after the     decrease in leakage with 5% increase in delay for a minimum
clock edge. Assuming that the setup and hold times are met,           size inverter. However, the magnitude of reducing leakage
the data at the input D is copied to the output Q after a worst-      power is limited, because the gate-length biasing transistors
case propagation delay (with reference to the clock edge)             used in critical path directly deteriorate its performances.
denoted by tc-q.
                                                                          In the proposed dual-threshold flip-flop, the critical paths
      Once we know the timing information for the flip-flops          are assigned with low VT, which assures the same level delay
and the combinational logic blocks, we can derive the system-         as the conventional master-slave flip-flop.
level timing constraints. In the synchronous sequential
circuits, switching events take place concurrently in response                                          IV.     SIMULATION RESULTS
to a clock stimulus. The results of operation await the next              In this section, the leakage power consumption of the
clock transitions before progressing to the next stage. In other      proposed dual-threshold transmission gate flip-flop is
words, the next cycle cannot begin unless all current                 compared with the other typical ones (ST-TG FF, GLB FF,
computations have completed and the system has come to rest.          and LFB FF) in the 130nm CMOS process. ST-TG FF is taken
The clock period T, at which the sequential circuit operates,         as a benchmark circuit for comparing their performances in
must thus accommodate the longest delay of any stage in the           this paper. For the four flip-flops, the simulation is carried out
network. Assume that the worst-case propagation delay of the          by HSPICE using the BSIM4 predictive models [11]. Their
logic circuit equals tplogic, while its minimum delay (also called    delay, leakage power, and total power have been compared.
the contamination delay) is tcd. The minimum clock period T           The same input and clock shown in Fig. 5 are given to these
that is required for proper operation of the sequential circuits      circuits to assure the fairness of the comparison.
is given by
                                                                          Their delays are listed in Tab. 1. Compared with ST-TG
               T ≥ tc − q + t plogic + tsu                    (3)     FF (single-threshold transmission gate flip flop), both GLB FF
                                                                      (gate-length biasing flip-flop) and LFB FF (leakage feedback
                                                                      flip-flop) have large delay penalty while the DT-TG FF (the
    The hold time of the flip-flop imposes an extra constraint
                                                                      proposed dual-threshold transmission gate flip-flop) has the
for proper operation,
                                                                      same delay as the benchmark circuit due to the critical path
                                                                      assigned with low VT. Moreover, there aren’t any more
           tcd , flip − flop + tcd , log ic ≥ thold           (4)     transistors (sleep transistors or feed back transistors) inserted
                                                                      in DT-TG FF.
Where tcd, flip-flop is the minimum propagation delay (or
contamination delay) of the flip-flop. This constraint ensures
                                                                                          1.2
that the input data of the sequential elements is held long
enough after the clock edge and is not modified too soon by                                                                                        D
the new wave of data coming in.                                                             0
                                                                           Voltage (V)V




                                                                                          1.2
   According to the Alpha power delay model [10], the                                                                                              clk
propagation delay, tp, of a CMOS inverter can be                                            0
approximated as                                                                           1.2
                                                                                                                                                   Q

                          C LVDD                                                           0
           tp = K                                             (5)                               0              0.1           0.2             0.3
                         W
                     μCox (VDD − VT )α                                                                                  Time (us)
                         L                                                                          Figure 5. The transient curves of flip-flop.




                                                                    541
                                TABLE I.             DELAY COMPARISONS OF FLIP-FLOPS                                TABLE II.       POWER COMPARISONS OF FLIP-FLOPS
                                                                                                                                 Dynamic       Static Power      Total Power
   Flip-flops                             tsu (ns)         thold (ns)       tc-p (ns)         T (ns)           Flip-flops
                                                                                                                                Power (uw)         (uw)             (uw)

   ST-TG FF                               0.029                0             0.029            0.058            ST-TG FF           0.425             0.7              1.125

    GLB FF                                0.059                0             0.052            0.111            GLB FF             0.475             0.5              0.975

    LFB FF                                0.083                0             0.075            0.158             LFB FF             0.55             0.2              0.75

   DT-TG FF                               0.029                0             0.029            0.058            DT-TG FF           0.425             0.3              0.725


    The simulation results for energy consumptions are                                                                             V.     CONCLUSIONS
illustrated in Fig. 6. Since the ST-TG FF doesn’t adopt any                                                  Based on that the characteristic of the high VT transistors
technology of reducing leakage current, the total power is the                                           has low leakage current, the dual-threshold transmission gate
largest one, which is contributed to the increasing leakage                                              flip-flop is proposed. Compared with the previously published
power in sequential circuits. The DT-TG FF has the lowest                                                technologies, the proposed flip-flop reduces the leakage power
power among those flip-flops. The high-threshold transistors                                             considerably, and maintains the performance as the
adopted in the state holding circuits reduce its leakage power.                                          conventional master-slave flip-flop. By HSPICE simulations,
Moreover, its simple structure with the least count of                                                   the propose flip-flop can work well. It achieves considerable
transistors doesn’t cause the additional dynamic power.                                                  energy savings over the other similar implementations. This
Though LFB FF can reduce leakage current of all existing                                                 design idea could provide a significance reference that would
sneak leakage paths very effectively, the sleep transistors can                                          guide the design of the other circuits for reducing leakage
bring up additional dynamic power, because the size of the                                               power in deep sub-micron ICs.
sleep transistors must be enlarged to meet the delay constraints,
and the gate capacitance of the sleep transistors becomes large,
                                                                                                                                  ACKNOWLEDGMENT
which leads to additional dynamic power.
                                                                                                            Project is supported by National Natural Science
    The power dissipations are compared in the Tab. 2.                                                   Foundation of China (No. 60773071).
Compared with ST-TG FF, DT-TG FF can save the 50%
leakage power and the 30% total power at the same size                                                                                  REFERENCES
transistors level, and DT-TG FF keeps the same dynamic                                                   [1]  D. Meindl, “Low power microelectronics: Retrospect and prospect”,
power as the ST-TG FF. Compared with ST-TG FF, LFB FF                                                         Proceedings of the IEEE,Vol.83(4) ,pp.619, 1995.
can save the 70% leakage power and the 23% total power with                                              [2] A. P.Chandrakasan, et al.,“Low-power CMOS digital design", IEEE
the serious penalty of additional dynamic power. GLB FF can                                                   Journal of Solid-State Circuits, Vol.27, No.4, pp.473, 1992.
save 30% leakage power and the 20% total power compared                                                  [3] P. Pant, V. De and A. Chstterjee, “Device-circuit optimization for
with ST-TG FF. with the increasing frequency, the dynamic                                                     minimal energy and power consumption in CMOS random logic
power will increase quickly, and thus LFB FF can be used in                                                   network”, DAC, pp. 25.1.1-25.1.6, 1997.
low operation frequencies. The DT-TG FF is an excellent                                                  [4] S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. S. Yamada, “A 1V
                                                                                                              multi-threshold voltage CMOS DSP with an efficient power
candidate for low-energy VLSI designs in deep sub-micro                                                       management technique for mobile phone application”, pp. 168-169, In
integrated circuits.                                                                                          IEEE ISSCC,1996.
                                                                                                         [5] S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. S. Yamada,, “A 1-
                                                                                                              V High-Speed MTCMOS circuit scheme for power down application
                                                 ST-TG DFF                                                    circuits, IEEE JSSC, Vol. 32(6), June 1997.
                                  2
                                                 GBL DFF                                                 [6] James Kao and Anantha Chandrakasan, “MTCMOS sequential circuits”,
                                                                                                              In Proc. of ESSCIRC 2001, 2001.
                                                 DLF DFF
                                                                                                         [7] Sewan Heo, Youngsoo Shin, “Minimizing leakage of sequential circuits
     Energy dissipations (pJ)




                                1.5               DT-TG DFF                                                   through flip-flop skewing and technology mapping”, Journal of
                                                                                                              Semiconduvtor Technology and Science, Vol. 7(4), pp. 215-220, 2007.
                                                                                                         [8] P. R. van der Meer, A. van Staveren, A. H. M. van Roermund, “Ultra-
                                                                                                              low standby currents for deep sub-micron VLSI CMOS circuits: Smart
                                  1
                                                                                                              series switch”, In IEEE International Symposium on Circuits and
                                                                                                              Systems, pp.1-4, May 2000.
                                                                                                         [9] James T. Kao, “Subthreshold leakage control techniques for low power
                                0.5                                                                           digital circuits”, Doctor of Philosophy in Electrical Engineering and
                                                                                                              Computer Science at the Massachusetts Institute of Technology, May
                                                                                                              2001.
                                                                                                         [10] K. Nose and T. Sakurai, “Optimization of VDD and VTH for low-power
                                  0
                                                                                                              and high-speed applications,” in Asia and South Pacic design
                                      0   0.2        0.4     0.6    0.8       1.0       1.2   1.4             automation conference, pp. 469, 2000.
                                                                Time (us)
                                                                                                         [11] Wei Zhao and Yu Cao, “New generation of Predictive Technology
                                                                                                              Model for sub-45nm design exploration”, Department of Electrical
                                Figure 6. Energy dissipation comparisons of flip-flops.                       Engineering, Arizona State University, 2006.



                                                                                                       542

				
DOCUMENT INFO
Shared By:
Categories:
Tags: cmos-IEEE
Stats:
views:23
posted:8/23/2011
language:English
pages:4