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•   Lecture 1 Logic Design with CMOS
•   Lecture 2 Transmission Gates
•   Lecture 3 CMOS Chip Design Options
•   Lecture 4 Programmable Logic Structures
•   Lecture 5 Programmable Interconnect
•   Lecture 6 Programmable Gate Array
•   Lecture 7 ASIC Design Flow
4/20/2011                                     1
       Lecture 1
Logic Design with CMOS

    MOSFETS as Switches
  Basic Logic Gates in CMOS
    Complex Logic Gates
            MOSFETS as Switches
• A transistor has three terminals: gate, source, drain.
• An MOS transistor looks like a switch (conducting/on,
  non-conducting/off, not open or closed)




4/20/2011                                                  3
    Basic Logic Gates in CMOS




4/20/2011                       4
    Basic Logic Gates in CMOS
• CMOS
  Combinational Logic
     – Use Demorgan's
       theorem to reduce
       functions
     – Remove all NAND-
       NOR operations
     – Implement NMOS
       network
            • AND – Series
            • OR – Parallel
     – Create PMOS network
       by complementing
       operations.
            • AND – Parallel
            • OR – Series
4/20/2011                       5
            2-input NAND Gate




4/20/2011                       6
            2-input NOR Gate




4/20/2011                      7
    Basic Logic Gates in CMOS




4/20/2011                       8
            Complex Logic Gates
            AOI/OAI Structured Logic




4/20/2011                              9
            Complex Logic Gates
  XOR/XNOR using Structured Logic




4/20/2011                           10
            Complex Logic Gates




4/20/2011                         11
            Complex Logic Gates




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             Complex Logic Gates
                Naming of complex
            CMOS combinational logic cells




4/20/2011                                    13
                 Lecture 2
            Transmission Gates


                Multiplexers
                 Latches



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            Transmission Gate




4/20/2011                       15
            Transmission Gate




4/20/2011                       16
            2-to-1 Multiplexer




4/20/2011                        17
            4-to-1 Multiplexer




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            XOR Gate (8 Transistors)




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            XOR Gate (6 Transistors)




4/20/2011                              20
            D Latch




4/20/2011             21
            D Flipflop




4/20/2011                22
            D Flipflop




4/20/2011                23
          Lecture 3
    CMOS Chip Design Options

                    Full Custom ASICs
                Standard Cell based ASICs
                 Gate Array based ASICs
            (Channeled, Channelless and Structured GA)



4/20/2011                                                24
               VLSI Design Styles
                           ASIC


 Full Custom Design                     Semi Custom Design


                          Cell Based Design
Gate Array Based Design                         PLD Based Design
                                (ASIC)

    SPLD Based Design     CPLD Based Design     FPGA Based Design
       (PLA or PAL)            (Altera)              (Xilinx)

    PLD – Programmable Logic Device
    SPLD – Simple Programmable Logic Device
    CPLD – Complex Programmable Logic Device
    FPGA – Field Programmable Gate Array
 4/20/2011                                                    25
                       Full Custom IC
            Structural Description             Design Entry

                    Ctrl


            Mem     Reg          Comp.
                    File          Unit




                     Place & Route

                       comp
                                  PLA


                                         I/O




     ...
                       ram


                           A/D



4/20/2011                                                     26
Full Custom ASICs – Features
• Complete fabrication process
     • Total flexibility, only limited by layout rules
     • Manual design
• Features
     • Chip size limits complexity
     • Long design and fabrication time
     • Efficient use of silicon area
     • Cheap only at highest quantities (ex. uP uP,
       memories, ...)


4/20/2011                                                27
   Full Custom ASICs – When?
• It makes sense to take this approach only if
  there are no suitable existing cell libraries
  available that can be used for the entire
  design.
• This might be because existing cell libraries
  are not fast enough, or the logic cells are not
  small enough or consume too much power.
• Use full-custom design if the ASIC
  technology is new or so specialized that
  there are no existing cell libraries or because
  the ASIC is so specialized that some circuits
  must be custom designed.
• Suitable for large volumes of production.
4/20/2011                                         28
            Full Custom ASICs
• Fewer and fewer full-custom ICs are
  being designed because of the problems
  with these special parts of the ASIC.
• Advantages
     – Highest in performance & Lowest part cost
       (smallest in die size)
• Disadvantages
     – Increased design time, complexity, design
       cost and highest risk
     – Manufacturing lead time is about few years.


4/20/2011                                          29
     Standard Cell based ASICs
   Structural Description                           Design Entry

             Ctrl                                       P_Inp: process (Reset, Clock)
                                                         begin
                                                           if (Reset = '1') then
                                                              sum <= ( others => '0' );
             Reg    Comp.
       Mem                                                    input_nums_read <= '0';
             File    Unit                                     sum_ready <= '0';



                                                       add82 : kadd8 port map (
                                                          a => add_i1, b => add_i2,
                                                          ci => carry, s => sum_o);
                                                       Mult_i1 <= sum_o(7 downto 0);
             D      C       C       B


              A         C       C


             D      C       D       B   Cell library

             C      C       C       B
                                           A    B
                                          C    D

4/20/2011                                                                                 30
      Standard Cell based ASICs
• What are Standard cells?
   – Predefined & precharacterized Circuits.
   – Analogous to subroutine, class, function and
     method libraries in software
   – Primitive cells or Mega cells
   – Cells are carefully characterized to allow use
     by higher level tools
        • Synthesis (put them together in behavioral,
          structural and physical domains)
        • Analysis (function, speed, delay, power,
          testability)

 4/20/2011                                              31
            Standard Cell Layout




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            Example - Standard Cell




4/20/2011                             33
            Example - Standard Cell




4/20/2011                             34
            Standard Cell - Features
• Complete fabrication process
     • Predefined library of base functions
     • Modular similar to TTL families
• Features
     • Chip size limits complexity
     • Long turn around time
     • Cheap at high quantities
     • Standardized cell height
     • Unsuitable for regular structures
     • More flexible and compact (1:4) than gate array

4/20/2011                                                35
   Standard Cell - Descriptions
• Each cell in an ASIC cell library must contain
  the following:
   – A physical layout
   – A behavioral model
   – A Verilog/VHDL model
   – A detailed timing model
   – A test strategy
   – A circuit schematic
   – A cell icon
   – A wire-load model
   – A routing model
4/20/2011                                      36
            Gate Array based ASICs
• Prefabricated wafers
   – I/O stages predefined
   – Regular array of MOSFETs
     and interconnection
     channels
   – Interconnection defines
     functionality
• Features                       • All layers are
                                   prefabricated except
   – Size: 100 - 1M gates
                                   the metal layers
   – Short turn around time
                                 • There are three types:
   – Cheap at medium
                                    – Channeled gate arrays
     quantities
                                    – Channelless gate arrays
   – Unsuitable for regular
                                    – Structured gate arrays
     structures like RAM, PLA,
     ALU
4/20/2011                                                  37
            Gate Array Layout




4/20/2011                       38
            Gate Array Cell Layout




4/20/2011                            39
            Gate Array Programming
              3-input NAND Gate




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            Channeled Gate Arrays
 • Only the
   interconnect is
   customized
 • The interconnect
   uses the predefined
   spaces between the
   rows of the base
   cells
 • Manufacturing lead
   time is between 2
   days to 2 weeks.
4/20/2011                           41
        Channelless Gate Arrays

• Only some mask
  layers (top few) are
  customized - the
  interconnect
• Manufacturing lead
  time is between 2
  days to 2 weeks.



4/20/2011                         42
            Structured Gate Arrays
 • Only mask layers are
   customized - the
   interconnect
 • Custom blocks (the
   same for each
   design) can be
   embedded.
 • Manufacturing lead
   time is between 2
   days to 2 weeks.


4/20/2011                            43
         Lecture 4
Programmable Logic Structures

                PAL 22V10
            Programming of PALs




4/20/2011                         44
                  ASIC vs PLD
• Standard ICs
     – General-purpose processors, memory chips and
       other standard components
• ASIC (Application Specific IC)
     – Semi-custom chip design
     – Dedicated to single function, or limited range of
       functions
     – A typical ASIC is a circuit, where functions are
       designed by the customer and layout and the
       fabrication is done by the silicon vendor
     – Personalized at the factory
• PLD (Programmable Logic Device)
     – Personalized at the client site
     – (EE)PROM, PLA, PAL, CPLD/FPGA

4/20/2011                                                  45
                 What's the PLDs?
• Usage of CAD S/W
• Contents of PLD
     –   Configurable Logic Block
     –   Programmable Routing Switch Block
     –   Configurable Memory Block
     –   Input/Output Block
• Advantages of PLD
     –   Fast Prototyping
     –   Re-Programmable
     –   In-System Programmable
     –   Easy Transfer of Design Results
            • HDL to Text File Format
     – Design Security in Chips

4/20/2011                                    46
            Classifications of PLDs
• SPLD (Simple PLD)
     – PLA (Programmable Logic Array)
            • PLA is a relatively small FPD that contains two levels of logic,
              an AND-plane and an OR-plane, where both levels are
              programmable
     – PAL (Programmable Array Logic)
            • PAL is a relatively small FPD that has a programmable AND-
              plane followed by a fixed OR-plane
• CPLD (Complex PLD)
     – A more Complex PLD that consists of an arrangement of
       multiple SPLD-like blocks on a single chip.
• FPGA (Field-Programmable Gate Array)
     – FPGA is an FPD featuring a general structure that allows
       very high logic capacity.
4/20/2011                                                                    47
  Basic Configuration of PLDs




4/20/2011                       48
  Basic Configuration of PLDs




4/20/2011                       49
            Logic Allocation: PLA




4/20/2011                           50
                     CPLD
• A CPLD comprises multiple PAL-like blocks on a
  single chip with programmable interconnect to
  connect the blocks.
• CPLD Architecture




4/20/2011                                          51
      PAL 22V10 (PALCE22V10)




4/20/2011                      52
            PAL 22V10 (Macrocell)




4/20/2011                           53
 PAL 22V10 (Functional Diagram)




4/20/2011                     54
 PAL 22V10 (Functional Diagram)




4/20/2011                     55
          Lecture 5
   Programmable Interconnect




4/20/2011                      56
                 Antifuse
• An antifuse is opposite of a regular fuse.
• An antifuse is normally open until a
  programming current is forced through it.
• An antifuse is resistive and the addition of
  contacts adds parasitic capacitance. So,
  clever routing techniques are required.
• Long term reliability is an important issue
  since the properties of antifuse change over
  time.
• Popular Vendor: ACTEL
4/20/2011                                        57
            Antifuse (PLICE )
• PLICE – Programmable Low Impedance
  Circuit Element




4/20/2011                          58
            Antifuse (Metal-Metal)




4/20/2011                            59
            Antifuse – Example




4/20/2011                        60
            Antifuse – Example




4/20/2011                        61
              Static RAM
• Designers can reuse chips during
  prototyping and the system can be
  manufactured in ISP.
• Need to keep a power supplied to the
  programmable ASIC for the volatile SRAM to
  retain the connection information.
• Popular Vendor: XILINX




4/20/2011                                  62
               Static RAM
• Xilinx SRAM (static RAM) configuration cell
   – Use in reconfigurable hardware
   – Use of programmable read-only memory or
     PROM to hold configuration




4/20/2011                                      63
            Static RAM - Example




4/20/2011                          64
            Static RAM - Example




4/20/2011                          65
            EPROM and EEPROM
               Technology
• With a high (>12V) programming voltage,
  VPP, applied to the drain, electrons gain
  enough energy to “jump” onto the floating
  gate (gate1)




4/20/2011                                     66
            EPROM and EEPROM
               Technology
• Electrons stuck on gate1 raise the
  threshold voltage so that the transistor is
  always off for normal operating voltages




4/20/2011                                       67
            EPROM and EEPROM
               Technology
• UV light provides enough energy for the
  electrons stuck on gate1 to “jump” back to
  the bulk, allowing the transistor to operate
  normally




4/20/2011                                        68
          Lecture 6
  Reprogrammable Gate Array

            Xilinx Programmable GA




4/20/2011                            69
       FPGA - Generic Structure
• FPGA consists of an array of programmable basic
  logic cells surrounded by programmable
  interconnect.
                     Logic block    Interconnection switches



                                   I/O


               I/O




                                                               I/O
                                   I/O
4/20/2011                                                            70
       FPGA - Generic Structure




4/20/2011                         71
            FPGA Based Design
• Field programmable device
    – No fabrication needed for customizing
    – Predefined logic blocks
    – Unsuitable for regular structures
• Features
    – Size: Up to 2,000,000 logic gates
    – Large silicon area necessary
    – Short design and customize time
    – Cheap for small quantities
    – Compared to ASICs, FPGAs have a reduced clock speed
    – Circuit configuration downloadable (RAM or PROM)

4/20/2011                                                72
            FPGA Building Blocks
• Programmable logic blocks
    – Implement combinatorial and sequential logic
• Programmable interconnect
    – Wires to connect inputs and outputs to logic
      blocks
• Programmable I/O blocks
    – Special logic blocks at the periphery of device for
      external connections




4/20/2011                                                   73
  FPGA – Basic Logic Element
• LUT to implement combinatorial logic
• Register for sequential circuits
• Additional logic (not shown):
    – Carry logic for arithmetic functions
    – Expansion logic for functions requiring more than
      4 inputs
                                      Select



                                               Out

            A
            B
            C
                LUT           D   Q

            D

                      Clock

4/20/2011                                             74
             Look-Up Tables (LUT)
• Look-up table with N-inputs can be used to
  implement any combinatorial function of N inputs
• LUT is programmed with the truth-table

                                A
                                B
                                C      LUT       Z
                                D

                                LUT implementation

                                A
                                B
                                                     Z
                                C
                                D

             Truth-table       Gate implementation

 4/20/2011                                               75
            XC3000 CLB




4/20/2011                76
                XC3000 CLB
• A 32-bit look-up table (LUT)
• CLB propagation delay is fixed (the
  LUT access time) and independent of
  the logic function
• 7 inputs to the XC3000 CLB
     – 5 CLB inputs (A–E)
     – 2 flip-flop outputs (QX and QY)
• 2 outputs from the LUT (F and G).



4/20/2011                                77
                       XC3000 CLB
• Since a 32-bit LUT requires only five
  variables to form a unique address (32=25),
  there are several ways to use the LUT:
     – Use 5 of the 7 possible inputs (A–E, QX, QY) with
       the entire 32-bit LUT (the CLB outputs (F and G)
       are then identical)
     – Split the 32-bit LUT in half to implement 2
       functions of 4 variables each.
            • Choose 4 input variables from the 7 inputs (A–E, QX,
              QY).
            • Choose 2 of the inputs from the 5 CLB inputs (A–E).
            • Then one function output connects to F and the other
              output connects to G.
     – Split the 32-bit LUT in half, using one of the 7
       input variables as a select input to a 2:1 MUX that
       switches between F and G (to implement some
       functions of 6 and 7 variables).
4/20/2011                                                            78
            XC4000 CLB




4/20/2011                79
            XC5200 CLB




4/20/2011                80
            FPGA Design Flow




4/20/2011                      81
                Lecture 7
            ASIC Design Flow




4/20/2011                      82
            ASIC Design Flow




4/20/2011                      83
                     Design Entry
• Enter the design into an ASIC design system.
• Options of Design Entry
     – Use a Hardware Description Language (HDL)
            • VHDL or VerilogHDL
     – Use Schematic Entry
     – Use Finite State Machines
     – Other options
            • System C, System Verilog, etc




4/20/2011                                          84
            Logic Synthesis




4/20/2011                     85
            Logic Synthesis




4/20/2011                     86
             Technology Library
• The set of primitive cells that synthesis uses
  to implement a design
• For ICs: Gates, flip-flops, and latches
• For FPGAs: LUTS, muxes, flip-flops
• Cell characteristics:
     –   Function
     –   Area
     –   Input pin loads
     –   Output pin drive strengths
     –   Timing arcs

4/20/2011                                      87
            System Partitioning
   “Decomposition of a system into a set of
   smaller subsystems without affecting its
   original functionality”
    – Divide a large system into ASIC-sized
      pieces.
   Factors
        Memory space requirements
        Computation Power
   Parameters
        Interconnections between partitions
        Delay due to partitioning
        Number of terminals
        Area of each partition
        Number of partitions
4/20/2011                                     88
            Pre-Layout Simulation
• Check to see if the design functions
  correctly
• Includes only logic cell delays but no
  interconnect delays.




4/20/2011                                  89
    Floorplanning & Placement
   “Assigning locations to the blocks on a layout
   surface”
        Floorplanning – All/Some blocks are flexible
           Arrange the blocks of the netlist on the chip.
        Placement – All bocks are fixed
           Decide the locations of cells in a block.
   Factors
        Layout area
        Completion of routing
        Circuit performance
   Parameters
        Shape of the blocks
        Routing considerations
        Placement for high performance circuits
        Packaging considerations
        Pre-placed blocks
4/20/2011                                                   90
                       Routing
   “Finding the geometric layout of all the nets”
        Global & Detailed Routing
   Factors
        Regions – channel & switchbox
        Nets – signal nets, clock nets, power & ground
        nets
   Parameters
        Number of terminals
        Net width
        Via restrictions
        Boundary type
        Number of layers
        Net types

4/20/2011                                                91
                Special Routing
   Via minimization
        “Reducing the number of vias by reassigning the
        wire segments to different layers while routing”
   Over-the-cell routing
        “Using the metal layers available over the cell
        rows for routing”
   Clock routing
        “Finding the geometric layout for the clock signal
        with minimum clock skew, noise & crosstalk”
        Factors – RC parameters, type of load
   Power & ground routing
        “Finding the geometric layout for the power and
        ground signal”
        Factors – current density & area
4/20/2011                                                 92
            Circuit Extraction
• Determine the resistance and
  capacitance of the interconnect.
• Estimates of capacitance may included
  after completing the logic synthesis is
  over.




4/20/2011                               93
            Post-Layout Simulation
• Check to see the design still works with
  the added loads of the interconnect.
• Estimates of capacitance may included
  after completing the logic synthesis is
  over.
• After successfully completing the LVS
  run, the system is simulated by
  including all system and interconnect
  capacitances.
4/20/2011                                94
            Reference




4/20/2011               95
Queries ???

 Thank You

				
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