6th Responsive Space Conference RS6-2008-6004 Programmable Satellite Transceiver (PST) for Responsive Space Jason Phillips, Bill Asiano Real Time Logic, Inc. 6th Responsive Space Conference April 28–May 1, 2008 Los Angeles, CA AIAA-RS6-2008-6004 Programmable Satellite Transceiver (PST) for Responsive Space Jason Phillips Real Time Logic Inc. 8591 Prairie Trail Drive • Englewood, CO 80112; (303) 703-3834 firstname.lastname@example.org Bill Asiano Real Time Logic Inc. 12515 Academy Ridge View • Colorado Springs, CO (719) 598-2801 email@example.com ABSTRACT As the demand increases for more responsive lower costs space operations, the leadtime for fielding space assets will need to significantly decrease. The Air Force Research Laboratory (AFRL) Operation Responsive Space (ORS) initiative is pushing the boundary of quick deployment of space assets with an objective goal of the six day satellite. To meet the goals of ORS, the satellite must be adaptable to different missions, changing threats, and emerging technologies. In order to minimize integration efforts and meet these objectives, satellite subsystems will be intelligent modules that support a plug-in-play interface architecture between modules and the satellite bus. The Space Plug-and-Play Avionics (SPA) system in development by AFRL Space Vehicles Directorate addresses the space craft subsystems software and electrical interfaces. Two critical subsystem modules are the S-band Command, Control, and Telemetry (CC&T) and UHF/S-Band Mission Data radios. This paper introduces the Programmable Satellite Transceiver (PST) design concept for the CC&T. The PST as one of many Plug and Play (PnP) components supports the Space Plug-in-Play Avionics Universal Serial Bus (SPA-U) interface. The PST design is adaptable to be used in standard satellite configurations, but it can also support AFRL’s ORS PnP configuration architecture. A PnP component contains Self-Defining Data Sheet (xTEDS) which has all the data products, commands, interfaces, services, telemetry, and standard commands to define that subsystem. With a comprehensive intelligent protocol for each of the subsystems, satellite integration and test is significantly reduced and simplified. Traditional single frequency radios are set at the factory to a specific frequency and modulation type. The PST provides a modular software radio designed for space operations combining frequency agility and software configured signal processing functions in a re-programmable transceiver. Radiation tolerant parts and radiation mitigation techniques are used to enable the configurable operation in a space environment. For CC&T radio applications the modulator and demodulator can be independently tuned to any SGLS or USB frequency combination under software control. As a Mission Data radio both two-way UHF is supported along with S-Band transmit for TDRS applications using staggered PSK modulation schemes. All baseband Digital Signal Processing (DSP) functions are performed by a reconfigurable Xilinx Field Programmable Gate Array (FPGA). FPGA signal processing allows future upgrade to virtually any waveform set without hardware modifications. The ORS program objectives direct the development of technologies that support robust and flexible satellite bus designs. The PST using the SPA-U interface allows for rapid integration within these designs and provides a flexible yet modular and adaptive solution for CC&T/Mission Data radio functions. The PST design concept enables the ORS to provide a cost effective approach to rapid space asset deployment, operations, and maintenance over the life cycle of DoD space missions. KEYWORDS: Software Defined Radio, SDR, Satellite Transceiver, SGLS, USB, Command, TT&C, Telemetry, Frequency Agile, Reprogrammable,S-Band, L-Band, Waveform 1 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 BACKGROUND The use of an FPGA to implement all baseband signal The spacecraft and associated ground systems for many processing allows software based configuration of virtually any type of current or future baseband of the Department of Defense (DoD), National Aeronautics and Space Administration (NASA), and waveform modulator or demodulator and data National Oceanic and Atmospheric Administration processing. A block diagram of the SLIQ is shown in Figure 1. (NOAA) satellites were independently implemented, resulting in the use of different Radio Frequency (RF) 10 MHz LO 10 MHz LO bands and signal waveforms. The majority of the PLL 50 MHz PLL military satellite systems conform to the Space Ground RF In RF Out Link System (SGLS) standard, while most Cal In IQ Demod Dual Baseband Filters Dual ADC/DAC/Serdes Dual Baseband Filters IQ Mod Cal Out civil/scientific satellite systems conform to the Unified Front S-Band (USB) standard. Not only are the waveforms Back within each standard unique, but the RF band that is 50 MHz Clock Dual Firmware Driven Serial AGC Out Receiver Serdes used also differs. Fixed function transceivers on the DACs/ADCs AGC In spacecraft prohibit civil ground systems from Ser In 422 Data Out Serdes FPGA communicating with military spacecraft and military Ser Out (x2) XC2VP30/40/50 Drvrs/Rcvrs 16 pairs Data In ground systems from communicating with civil spacecraft. I2C Temp/ Voltage ADC Cypress 8051 Processor Config PROM RAM Recognizing that significant cost savings would result RS422 & 480 MBPS USB from more integrated satellite operations, PST is being developed to operate using the SPA-U interface Figure 1. SLIQ Block Diagram protocols. The goal of PST is development and All sensitive RF/analog functions shown above the demonstration of a space based transceiver that dashed line are housed in mini-blocks mounted on the supports both SGLS and USB frequencies and front side of the module. All digital functions below the waveforms using a single hardware platform. dashed line are comprised of Integrated Circuits (ICs) mounted directly to the back side of the module. A RT Logic SLIQ picture of the front (mini-block) side of the SLIQ In early 2004, RT Logic completed initial development module is shown in Figure 2. of the S/L band In Phase/Quadrature (I/Q) (SLIQ) modulator/demodulator module. The SLIQ utilizes direct frequency conversion techniques, configurable Electro-Magnetic Interference (EMI) shielded enclosures called mini-blocks, and Field-Programmable Gate Array (FPGA) Digital Signal Processing (DSP) to provide a small, flexible solution for ground based RF modem applications. RF configuration flexibility is enabled by the use of pin compatible mini-blocks, which allow a single small SLIQ module to host two modulators, two demodulators, or one modulator and one demodulator in any combination of three bands (S-band, L-band, or Figure 2. SLIQ Front View 70 MHz). Mini-block construction of all RF/analog Many of the techniques that resulted in a small, flexible functions maximizes isolation of sensitive RF/analog SLIQ solution were selected for the space based PST signals from other signals, particularly digital ones. implementation. Wide tuning ranges results from the use of the direct (I/Q) conversion techniques and frequency synthesizer RT Logic/SEAKR PST Team mini-blocks operating over nearly an octave in each Since RT Logic had no space-qualified products when configured band. Processing bandwidth is maximized the PST opportunity was identified, it was determined by 50 MHz quadrature sampling, which results in an that teaming with a company with this experience was instantaneous baseband signal bandwidth of 40 MHz. needed to efficiently produce a space qualified product. 2 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 SEAKR Engineering has delivered many successful space products, and also has expertise in application of Xilinx FPGAs to the space environment through their membership in the Xilinx Radiation Test Consortium (XTRC). The teaming of RT Logic and SEAKR for development of the PST has combined RT Logic signal waveform processing expertise with SEAKR Engineering’s space applications experience. PST IMPLEMENTATION The PST utilizes direct frequency conversion and FPGA processing techniques developed for the SLIQ to provide wide tuning range, wide processing bandwidth, and configuration flexibility. The SLIQ mini-block packaging approach was replaced by multi-chamber clamshell (two-sided), shielded RF module construction to improve shock and vibration tolerance and reduce assembly costs, while maintaining maximum EMI Figure 3. PST Front View shielding effectiveness. The SERializer/DESerializer Power (SERDES) functions used in the SLIQ to optimize 28V DC Supply Module to all Modules & Freq Ref shielding through minimization of high-speed digital connections were replaced by parallel interfaces in the RS-422 Modulator Power Amplifier RF Output Control/ Module PST to minimize size and power consumption. Status Module Commercial quadrature modulator and demodulator ICs Calibration were radiation tested to ensure compatibility with the Mod Data Digital Module Module (optional) space environment. Radiation tolerance of all other semiconductor components was verified through Demod Data Demodulator Module RF Input identification of radiation test results for the same or similar component built with the same IC process. Frequency to Mod, Demod, Reference & Cal Modules (Backplane) Hardware Figure 4. PST Block Diagram A picture and block diagram of the PST are shown in Figures 3 and 4. The Power Supply Module converts 28 VDC input power into all DC voltages used by the rest of the modules and the frequency reference. The Digital Module hosts the Xilinx FPGA that implements all DSP modulator/demodulator (mod/demod) algorithms and nonvolatile memory capable of storing multiple FPGA configurations. FPGA configuration scrubbing is provided to mitigate radiation effects. The module also provides external control/status and mod/demod data interfaces. The Digital Module includes internal control/status interfaces to all internal modules except the Power Amplifier. It also sends/receives parallel digitized signals to/from the Modulator, Demodulator, and Calibration modules. A high stability, low-noise oscillator located on the backplane board produces the frequency reference signals used by the Digital, Modulator, Demodulator, and Calibration Modules. 3 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 The Modulator (Mod) Module converts digitized in the presence of Linear Energy Transfers (LET) of up baseband transmit signals from the Digital Module to 37 MeV•cm2/mg, and Single Event Upsets (SEUs) FPGA to a modulated RF signal at a selected frequency. must be statistically nonexistent at that level. The That signal is amplified by the Power Amplifier preferred method of meeting this requirement was to Module to produce the final unit RF output. choose components already qualified at these radiation levels. If qualified devices cannot be found for required The Demodulator (Demod) Module amplifies, functions, a component using the same process as a translates from a selected frequency, and converts the qualified component was selected. In two cases, RF input signal to digitized baseband signals sent to the radiation testing was required to qualify commercial Digital Module FPGA. components that did not meet the first two criteria. If Mod and/or Demod Module RF input/output I/Q The Analog Devices AD8347 quadrature demodulator gain/phase/offset calibration is required and neither and AD8349 quadrature modulator ICs were tested for module must operate continuously, calibration is both TID and ELDRS effects at Radiation Assured performed periodically during non-operational intervals Devices in Colorado Springs, Colorado. No electrical using a direct connection between the Modulator and degradation was detected for either device at a total Demodulator Modules. If Mod or Demod calibration is dose of 30 krad(Si). Heavy ion effects were tested at a required and either module must operate continuously, Lawrence Berkeley National Laboratories (LBNL) calibration is performed through the addition of an cyclotron. No latchup was observed for either device optional Calibration (Cal) Module. The Cal Module is over temperature, power supply, and LET variations. capable of generating a reference signal for use in Some Single Event Functional Interrupts (SEFIs) Demod Module calibration or receiving a calibration occurred during AD8349 testing at low temperature and signal from the Mod Module during operation of the a low power supply voltage, but the equivalent rate of respective Demod/Mod Module. Simultaneous these events for a unit in LEO orbit is once in 276 calibration and operation are enabled through the use of million years. spread spectrum calibration signals at frequencies that do not interfere with normal operations. Reliability and manufacturability criteria were also established for PST component selection. Since parts A view of the PST mechanical configuration is shown screening requirements vary for different applications, in Figure 5. parts were selected that are available in versions with the highest possible space or military screening levels whenever possible. If a screened part is not available for a required function, a commercial part is upscreened through inspection, burn-in, test, and other qualification procedures to produce a fully space qualified PST. Plastic Encapsulated Microcircuits (PEMs) were determined to be acceptable for PST, since they have been successfully flown on a number of space missions. Surface mounted leadless components with leads covered by the package were not used, since they can’t be effectively inspected after installation. Firmware Figure 5. PST Mechanical Configuration RT Logic uses the term Firmware to describe a specific IC Selection FPGA configuration used for signal or data processing. Initial PST firmware development is focused on PST IC radiation specifications are 20 krad(Si) Total providing support for SGLS and USB uplink Ionizing Dose (TID) at the component level, or about demodulation and downlink modulation. A block 100 krad(Si) at the unit level which includes 100 mil diagram of the PST SGLS/USB firmware is shown in combined module and unit level aluminum shielding Figure 6. Triplication and voting functions used to effects. ICs constructed using a bipolar process must be mitigate radiation induced SEUs are not shown. Since free from Extremely Low Dose Rate Susceptibility the PST firmware is programmable, other waveforms (ELDRS). Single Event Latchup (SEL) must not occur 4 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 can be supported through additional future firmware SPECIFICATIONS* development with no hardware changes. Key PST specifications are presented in the following to/from Control/ paragraphs. *Specifications are subject to change without notice. 8051 Status μController Interface Unit level PST specifications are given in Table 1. Table 1. PST Unit Level Specifications Dimensions 6.85” W x 7” D x 3.86” H Telemetry to IQ Data Modulator Mod Modulator Weight/mass 8 lb. (3.6 kg.) Calibration Input DACs Receive only power 16 W consumption Transmit & receive 45 W from IQ Command power consumption Demod Demodulator Demodulator Data Calibration ADCs Output Power input voltage 22 V to 36 V DC Figure 6. PST Firmware Block Diagram Power input isolation 1 M ohm min. A parallel control/status interface allows the Digital Operational temperature -24° C to +61° C Module 8051 microcontroller to read and write parallel range registers within the modulator and demodulator Vibration 19 G RMS firmware. Radiation tolerance 100 krad (Si) total dose The modulator block accepts external telemetry data outside chassis that is first Bi-Phase Shift Keying (BPSK) modulated onto a subcarrier that is then Phase Modulated (PM) on an output carrier signal. The resulting digital signal is Mod/Demod Hardware & Cal Firmware sent to the Modulator Module through the Digital-to- PST modulator/demodulator hardware and calibration Analog Converter (DAC) output ports. firmware specifications are given in Tables 2 and 3. The mod and demod calibration blocks perform gain, Table 2. PST Demod Hardware & Cal Firmware phase, and offset (voltage) correction operations for the Specifications quadrature modulator and demodulator devices. Calibration allows these devices to meet stringent Frequency ranges 1760 to 1840 MHz & spurious level requirements. 2025 to 2120 MHz Input signals are received from the Demodulator Noise figure 1.3 dB Module through the Analog-to-Digital Converter (ADC) input ports. A PM demodulator is first used to Input threshold -124 dBm (narrowband signal) recover baseband or subcarrier modulation in both USB and SGLS modes. Then, USB data extracted by a Dynamic range -40 dBm to threshold subcarrier BPSK demodulator or SGLS command data extracted by Frequency Shift Keyed Amplitude Bandwidth 40 MHz Modulation (FSK-AM) demodulator is sent to the Spurious response -60 dBc (combined command data output port. hardware and firmware) Software Table 3. PST Mod Hardware & Cal Firmware Specifications The PST software provides power up sequencing, external control/status interface support, nonvolatile Frequency range 2200 to 2300 MHz memory initialization, and test capabilities. The external control/status interface allows internal parallel Frequency stability ±20 ppm max. binary registers to be written for setting controls and RF output power 5 W min. (+37 dBm) read for accessing internal status information. 5 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 Output protection No damage, open or short Communications Security (COMSEC) unit and sent to circuit the PST. The data is modulated by the PST and sent from the high power RF output through a diplexer and Spurious response -60 dBc (combined to the antenna for transmission to an earth station. hardware and firmware) Modulated uplink commands are received by the antenna and coupled to the PST RF input by the SGLS/USB Mod/Demod Firmware diplexer. Once it is demodulated within the PST, command data is decrypted by the MCU-110 and PST SGLS/USB Mod/Demod firmware specifications passed to the C&DH subsystem. The PST can be are given in Table 4. configured for either SGLS or USB modes in this Table 4. PST SGLS/USB Mod/Demod Firmware environment using pre-loaded firmware. Specifications Global Positioning System (GPS) Demod acquisition range ±150 kHz A Calibration Module can be developed that is capable Demod acquisition time 0.5 sec. of receiving either a Modulator Module calibration (SGLS or USB) signal or a GPS L1 signal (1575 MHz), or generating a Demodulator Module calibration signal. This allows SGLS demod data 1 or 2 kbps FSK- rate/modulation AM/PM modulator and demodulator calibration to be performed at infrequent intervals, with GPS processing taking USB demod data 1, 2, or 4 kbps place the majority of the time. Firmware and software rate/modulation BPSK/PM must be developed to implement GPS algorithms, but the combination of transceiver and GPS capabilities Modulator data 1 to 128 kbps BPSK/PM rate/modulation would likely reduce the size, weight, and cost of separate transceiver and GPS receiver units. APPLICATIONS Potential applications of the PST are limited only by frequency range, bandwidth, and FPGA processing resources. A few possibilities are described below. SGLS and/or USB Transceiver Figure 7 shows a PST used as a SGLS and/or USB transceiver integrated into a space vehicle. 28V DC RS-422 Control/Status RF Out Mod Data C&DH Diplexer Antenna PST Subsystem MCU-110 Demod Data RF In Figure 7. PST SGLS/USB Transceiver Application The Communications and Data Handling (C&DH) subsystem controls and monitors the PST through the direct RS-422 connection. Telemetry data from the C&DH subsystem is encrypted by a MCU-110 6 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States. AIAA-RS6-2008-6004 Tracking and Data Relay Satellite (TDRS) Cross- Links TDRS cross-link signals are within the tuning and bandwith capabilities of the PST, so these waveforms could also be supported through the development of new firmware. UHF/S-Band Mission Data Radios The PST mechanical configuration contains a spare card slot. This slot can be populated with a secondary modulator module used to convert digitized baseband mission data signals from the Digital Module FPGA to a modulated RF signal at a selected UHF/S-Band frequency. Each of the PST modulators is independently tunable across a 100 MHz output RF band allowing for simultaneous operation of both modulators. The modulators can be configured individually for independent use as a CC&T telemetry transmitter and mission data radio applications. Other Waveforms Any current or newly developed waveform within the tuning, bandwidth, and processing capabilities of the PST can be supported through firmware development. Decoupling of waveform processing algorithms from the hardware platform provides opportunities to support new requirements with minimum development costs. 7 AIAA/6th Responsive Space Conference 2008 This work is declared a work of the US Government and is not subject to copyright protection in the United States.