# Partial Scan Methodologies Survey by liaoqinmei

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```									Survey of Partial Scan
Methodologies

Zdeněk Kotásek
Faculty of Information Technology
Brno University of Technology
Božetěchova 2
Brno, Czech Republic.
E-mail:kotasek@fit.vutbr.cz
http://www.fit.vutbr.cz/~kotasek/
1
Survey of Partial Scan Methodologies

The outline of the presentation
• The reasons for partial scan
• Testability-based partial scan methodologies
• Partial scan methodologies based on test generator usage
• Partial scan methodologies based on the analysis of circuit
structure
• Our activities in the area of partial scan methodologies

2
The Reasons for Partial Scan
• One possibility how to generate test for a sequential circuit
is through automatic test pattern generation for sequential
circuits (SATPG).
• Automatic test pattern generation for sequential circuits
(SATPG) is generally considered to be a hard problem.
• Full scan design techniques attempt to alleviate this
problem by connecting all flip-flops (FFs) or latches into a
scan path during test mode so that all these elements
become easily controllable and observable.
• Thus, in a circuit designed using full scan the portion of
the circuit excluding the scan path is fully combinational.

3
The Reasons for Partial Scan

• Two reasons against the full-scan techniques exist:
- the test application time associated with full-scan may
be extremely high
- the full scan may be prohibitively expensive due to high
• The length of a test sequence for the full scan shift is
L full scan = V x (N + 1) + N,
where V is the number of test vectors,
N is the number of scanned FFs

4
The Reasons for Partial Scan

• The solution to the full scan costs - partial scan techniques.
• The reduction of test application time - arranging scan flip-
flops in parallel scan chains.
• Partial scan techniques - only a subset of FFs are
included into the scan path such that the remainder of
the circuit has certain desirable testability properties.
• The subset of FFs must be identified in some way, this
goal is solved by partial scan methodologies.

5
The classification of partial scan
methodologies

• Partial scan methodologies can be classified into 3 groups
of methodologies:
- testability-based partial scan methodologies
- partial scan methodologies based on test generator usage
- partial scan methodologies based on the analysis of circuit
structure

6
Testability-based partial scan methodologies
Basic ideas:
• These methods utilise usually gate level designs for the
analysis.
• The values representing controllability/observability
factors of circuit nodes are computed, these values are then
evaluated in a defined way.
• The function used to do this can be seen as a global
function reflecting diagnostic features of the circuit,
namely controllability/observability.
• Then, the circuit is modified, global function evaluated
again and the impact on testability factors investigated.
• The modifications which effect the global function
(testability) positively are then taken into account.      7
Testability-based partial scan methodologies

• [PARI95] Parikh, P. S. - Abramovici, M.: Testability-
Based Partial Scan Analysis, Journal of Electronic Testing:
Theory and Applications, Vol. 7, 1995, No. 1/2, pp. 62 - 70
• The following parameters are computed: detectability cost
of every line in the circuit (minimum number of clock
cycles required to detect the fault).
• 3 components of detectability cost of a line: controllability
cost (activating the fault), sequential depth (propagating its
fault effect), and enabling cost (sensitising the propagation
path).
• The result of applying the cost-based partial-scan (CoPS)
algorithms - the identification of FFs for the partial scan
8
chain.
Testability-based partial scan methodologies

Computation of Costs
• Controllability. The controllability cost of line l for value
v, denoted by Cv(l), is the minimum number of clock
cycles required to set l to value v.

Controllability computation for NAND gate output
C0=5               C1=3            C1=5
                                         C0=5
C0=4                               C1=4
a                                  b
C0=3                               C1=3

9
Testability-based partial scan methodologies

FF output controllability computations

C0=n                     Q     C0=n+1
d
C1=m                           C1=m+1
ko
c                 C0=m+1
clock                         C1=n+1

10
Testability-based partial scan methodologies

Controllability values for fanout situations

C0 = n
C1 = m
C0 = n
C1 = m

C0 = n
C1 = m

11
Testability-based partial scan methodologies

• Sequential depth. The sequential depth of line l for a value
v, denoted by Dv(l), is the number of FFs along path P
between l and a PO, where P is the easiest path to
propagate a v/ v effect from l to a PO (v is the value of l in
the good circuit, and v is the value of l in the faulty
circuit).

12
Testability-based partial scan methodologies

Sequential depth computation for AND and NAND gates
D0=3
                           D0=3          
D1=5                   D0=3                              D0=5
D1=5
D1=5                              D1=3

Sequential depth computation for FF

D0=5                               D0=4
D        Q
D1=7                               D1=6
FF
C
clock
13
Testability-based partial scan methodologies

• Enabling cost. Let P be the easiest path to propagate a fault
effect v/v from l to a PO. The enabling cost of line l for a
value v, denoted by Ev(l), is the maximum controllability
cost required to enable the propagation of a fault effect v/v
along P.

14
Testability-based partial scan methodologies

Enabling cost computation for NAND gate

E0=7
1
E1=5                                E1=7
C1=5                                 E0=5
C1=4

15
Testability-based partial scan methodologies

Enabling cost computation for FF

E0=3                                   E0=4
d             Q
E1=6                                   E1=7
ko
c
clock

16
Testability-based partial scan methodologies

• Detectability. Let f be the fault l s-a-v. The detectability
cost of fault f denoted by DET( f ), is the minimum number
of cycles required to detect f. The detectability cost of a
fault estimates the relative difficulty of detecting the fault.
DET( f ) is computed by
Det (F) = max {C v ( l ), E v ( l )} + D v ( l )
• The detectability cost of a fault estimates the relative
difficulty of detecting the fault.

17
Testability-based partial scan methodologies

• The principle of sensitivity analysis - the proposed change
to improve the testability of a circuit is not evaluated only
by the improvement in the costs of the signals directly
involved in that change, but by the improvement of the
total function (TCF) of the circuit. The TCF is calculated
by TCF=Σ DET( f ).
f

18
Testability-based partial scan methodologies

• The summation is performed for all target faults - the
TCF can then be used as a measure of the relative
difficulty of testing the circuit for the given set of faults.

• Sensitivity. The sensitivity, ζ, is the change in the TCF
value resulting from a change in the circuit (ζ = ΔTCF). In
our case, the change is scanning a particular FF.

19
Testability-based partial scan methodologies

The conclusions:
• For this type of methodologies it is typical that the
testability of the circuit under analysis is evaluated by
means of a global function, a modification (a FF is
included into the scan chain) is performed and the effect of
the modification is evaluated.
• Then, if the modification of the circuit has a positive effect
on the global function value (testability has increased), the
modification is accepted, otherwise it is refused.
• These approaches are sometimes denoted as analytical
approaches.
20
Partial scan methodologies based on test
generator usage
Basic ideas:
• These methods utilise test generator (functional or
structural test), then a methodology to identify FFs to
be included into a scan register is used.
• Agrawal, V. D. - Cheng, K. - Johnson, D. D. - Lin, T.:
Designing Circuits with Partial Scan, IEEE Design & Test
of Computers, April 1988, pp. 8 - 15
• In this methodology, functional test vectors are generated
first.
• Then, the faults in the combinational part of the circuit that
are not detected by functional vectors are designated as
target faults for scan test generation.
21
Partial scan methodologies based on test
generator usage

• A typical feature of functional vectors - designer's primary
aim is design verification and not the coverage of stuck-
faults.
• The fault coverage of functional tests - not be as high as
required for manufacturing tests => it appears that
functional vectors, augmented by scan vectors may be
a reasonable solution to increase the quality of test.
• The goal is to include the smallest possible number of
FFs in the chain, and yet attain acceptable fault
coverage.

22
Partial scan methodologies based on test
generator usage

• The concept of Option Table is introduced and utilised in
the methodology.
• The table consists of the coverage of target faults as a
function of the number of FFs in the scan register, for
every target fault it is determined how many test vectors
are available to test particular fault and which FFs will be
active.
• An example: suppose the circuit contains 4 FFs (A, B, C
and D), and there are 4 undetected faults. Table 1 shows
the FF usage data.

23
Partial scan methodologies based on test
generator usage
• The concept of Option table

Fault   # of               FFs used
possible
tests
Ti1     Ti2        Ti3
F1      2          1       A,B
F2      3          A,B     B,C        A,B,D
F3      1          A
F4      2          A,B,D   A,D

24
Partial scan methodologies based on test
generator usage

• The principle of generating the table: for each target fault,
the set of tests is generated - then, for each test vector, FFs
that must be manipulated are identified.
• The entry “1” under ti1 in the above table means that the
particular test uses no FF.
• See the row 1 (fault F1) - the fault can be detected by two
tests - the first one requires no FF to be active (set to a
defined value), for the second one A and B FFs will be set.
• The objective is to select, for a given number of FFs, a set
of tests (one per fault) to cover the largest number of
faults. This a set coverage problem.
25
Partial scan methodologies based on test
generator usage
Algorithm for FFs identification for partial scan chain
Fault simulate entire circuit with functional vectors
Generate list of undetected faults Fun
Isolate combinational portion of circuit
Map Fun onto combinational part to obtain target faults Fcomb
Begin
for every fi  Fcomb generate all tests tij, j = 1, 2, … for fi
End
Generate Option Table: Estimated fault coverage vs. FF usage
Select an option from the Option Table
In combinational model make unscanned FF I/O inaccessible26
Partial scan methodologies based on test
generator usage

Begin
For every vector generated for this option do
Randomly fill unknown bits corresponding to scan FFs
Fault simulate Fcomb
Remove detected faults from Fcomb
Generate test sequence
End

27
Partial scan methodologies based on test
generator usage
The conclusions:
• In the methodology, functional test is generated first.
• Then faults which are not detected by the functional test
are identified by means of fault simulation process.
• Option table is used to identify FFs which can be used to
cover faults undetected by functional test (coverage
problem).
• These FFs are included into the scan chain.

28
Partial scan methodologies based on test
generator usage

• Higami, Y. - Kajihara, S. - Kinoshita, K.: Partial Scan
Design and Test Sequence Generation Based on Reduced
Scan Shift Method, Journal of Electronic Testing: Theory
and Applications, Vol. 7, č.. 1/2, 1995, pp. 115 - 124
• The Partial scan algorithm was developed, called PARES -
Partial scan Algorithm based on Reduced Scan shift.

29
Partial scan methodologies based on test
generator usage

Control and observation requirements
Test   Test vector   Fault effect    detect   NSC   NSO
vector part

t1     st1=(1,1,X)   re1=(X,X,D)       F1      2      1

t2     st2=(1,X,X) re2=(X,D,X)         F2      1      2

t3     st3=(0,0,X)   re3=(X,X,D)       F3      2      1

st = (FFa,FFb, FFc)                re = (FFa,FFb, FFc)

30
Partial scan methodologies based on test
generator usage

• NSO, NSC - the length of scan shift required for ith test
vector ti for observing and controlling FFs.
• Vector sti - partial scan vector of ti and includes values of
scanned FFs.
• X in vector sti means a don´t care value.
• FFs with X are not required to be controlled.
• Vector rei shows whether fault effects of Fi are propagated
to scanned FFs or not propagated by applying ti.
• D in vector rei means the propagation of fault effects => a
FF with D is required to be observed.
31
Partial scan methodologies based on test
generator usage
• Test t1: FFa and FFb are required to be controlled, and only
FFc is required to be observed in order to detect F1.
• NSO, NSC for each test vector, when a scan chain is
configured as FFa- FFb - FFc.
• The required number of scan shift operations (for t1 - t2 - t3
sequence of tests):
2, 1, 2 before t1, t2, t3
1 after t3 application
=> 6 clock pulses + additional 3 clock pulses to apply
every test t1, t2, t3 - altogether 9 clock pulses (partial scan).

32
Partial scan methodologies based on test
generator usage
• The solution for full scan: we have 3 test vectors to be
applied into 3 FFs.
(observing) the contents of FFs.
As mentioned above:
The length of a test sequence for the full scan shift
(mentioned previously) is
L full scan = V x (N + 1) + N,
where V is the number of test vectors,
N is the number of scanned FFs
The number of clock pulses to be generated to apply the
test in full scan - 15 clock pulses.
33
Partial scan methodologies based on test
generator usage
A method of selecting scanned FFs and their
arrangement in a scan chain implemented in PARES
•   First step: test vectors are generated for the combinational
part => FFs that must be controlled and FFs to which fault
effects are propagated are found for each test vector.
•   Principle No. 1: Frequently controlled/observed FFs
should be selected as scanned FFs.
•   Principle No. 2: FFs to be controlled for more test vectors
are located close to the scan input.
•   Principle No. 3: FFs to be observed for more test vectors
are located close to the scan output.
34
Partial scan methodologies based on test
generator usage
• The effect of principles 1 - 3: required scan shift
operations are expected to be small.
• The measures Wp and Wm are calculated for each FF:
Wp (FFi) = VC(FFi) + VO(FFi)
Wm (FFi) = VC(FFi) - VO(FFi)
VC(FFi) and VO(FFi) - the number of test vectors which
require FFi to be controlled and observed
• FFs having larger Wp are selected as a scanned FF.
• FFs having larger Wm are located close to the scan input.

35
Partial scan methodologies based on test
generator usage
Example:
• The task: the selection of three scanned FFs among five
FFs.
st = (FFa,FFb,FFc,FFd,FFe)   re = (FFa,FFb,FFc,FFd,FFe)
control                      observe
st1 = (X,1,0,0,X)            re1 = (D,X,X,X,X)
st2 = (1,0,1,X,X)            re2 = (X,D,X,X,X)
st3 = (0,0,1,X,1)            re3 = (D,X,X,X,D)

X: don„t care, D: fault effect
Table 2: control and observation requirements
36
Partial scan methodologies based on test
generator usage

• The explanation of symbols in Table 2:
sti - partial vector of a test vector
rei - vector which shows the propagation of fault effects
• FFs with X (don‟t care value) are not required to be
controlled.
• D means the propagation of a fault effects to FFs => FFs
with D are required to be observed.

37
Partial scan methodologies based on test
generator usage

Table 3: VC, VO, Wp, Wm
FF        VC         VO        Wp         Wm
FFa        2          2        4          0
FFb        3          1        4          2
FFc        3          0        3          3
FFd        1          0        1          1
FFe        1          1        2          0

Consequences: the required number of scanned FFs = 3
=> FFa, FFb, FFc are selected for scan (based on the largest
Wp value ), in the order of FFc-FFb-FFa (according to Wm
value).                                                        38
Partial scan methodologies based on test
generator usage

• Consequences: on the basis of applying the methodology,
some FFs are scanned, some are not scanned => for the
unscanned FFs the clock signal must be inactive to hold
the values of FFs.
• The following figure - FF1, FF2, FF3 are scanned, FF4,
FF5 are uncanned.
• The mode control - normal operation/scan shift operation.

39
Partial scan methodologies based on test
generator usage

combinational logic

mx
FF5
mx
FF4
mx       FF3
mx
FF2
mx
sdi            FF1

sdo
clock


mode control

combinational logic

40
Partial scan methodologies based on the analysis
of circuit structure
Basic ideas:
These methods are based on the following steps:
• Structure analysis of the circuit under design,
• Identifying paths and circuit structures through which
diagnostic data (test vectors and responses to them) can be
transferred (i. e. utilised for the test application) without
any modifications,
• Identifying elements in the circuit under design which can
be tested through these structure,
• Identifying elements which cannot be tested through the
circuit structure - they must be included into the scan chain

41
Partial scan methodologies based on the analysis
of circuit structure
• [AbB85] Abadir, M. S. - Breuer, M. A.: A Knowledge
Based System for Designing Testable VLSI chips, IEEE
Design&Test, August 1985, pp. 56 - 68
• The concept of I path was introduced and utilised in the
methodology:
• Definition 1: A structure S with an input port X and an
output port Y is said to have an identity mode (I - mode),
denoted by M(S : X –> Y ), if S has a mode of operation in
which the data on port X is transferred (possibly after
clocking) to port Y.

42
Partial scan methodologies based on the analysis
of circuit structure

• Definition 2: There is an identity transfer path (I path)
from output port X of structure S1 to input port Y of
structure S2, denoted by P( S1:X –> S2:Y), if the data at
port X can be transferred unchanged to port Y.
• Every I path has a time tag and an activation plan.
• Definitions 1 and 2 represent the concepts on which
many methodologies were developed in the past and
are still developed at present.

43
Partial scan methodologies based on the analysis
of circuit structure

• The transparency of elements to data loaded to their
inputs and the transparency of data paths recognised in
the circuit under analysis - the basic property which is
evaluated during the testability analysis.
• From this point of view two basic categories of elements
can be recognised in an RTL circuit: data processors (DP)
and data transporters (DT).
• The role of registers - elements through which a test is
applied => it is important to identify all registers in the
circuit under analysis and assign a role they will cover
during the test application.
44
Partial scan methodologies based on the analysis
of circuit structure
• Further results of the research team were published in
GUPT95 - Gupta, R. - Breuer, M. A.: Partial Scan
Design of Register-Transfer Level Circuits, Journal of
Electronic Testing: Theory and Applications, Vol. 7, 1995,
No. 1/2, pp. 25 - 46
• Basic idea: RTL designs generally consist of functional
blocks and registers that are interconnected by
multiplexers and buses to maximise resource sharing.
• => the methodology is based on the identification of
certain types of elements which may be important during
the test application.
45
Partial scan methodologies based on the analysis
of circuit structure

• The concept of switches is introduced - multiplexers and
bus structures - they have the unique ability to behave as
elements which can be utilised to logically partition the
circuit under analysis.
• The objective of the methodology is to take advantage of
any switches present in the circuit.
• By using this knowledge to influence the selection of scan
storage elements, the costs of partial scan design for the
circuit can be reduced while achieving the maximum
benefit.
46
Partial scan methodologies based on the analysis
of circuit structure

Scan path

Sequential
kernel
The situation before implementing the methodology

47
Partial scan methodologies based on the analysis
of circuit structure

Scan path

Multiplexers  buses

Sequential
kernel

The situation after implementing the methodology
48
Partial scan methodologies based on the analysis
of circuit structure

• A switch is a multiplexer or a bus whose control input
line(s) are controllable during test, i. e. it should be
possible to set and hold a given multiplexer or bus in a
particular mode (I mode) while applying one or more clock
cycles to the design.
• From a test point of view both types of structures are
seen to be equivalent.

49
Partial scan methodologies based on the analysis
of circuit structure
inputs

mux

a)
outputs

bus

b)

a) Multiplexer and b) bus used as switches
50
Partial scan methodologies based on the analysis
of circuit structure

• The conclusion: the objective of the analysis - the
identification of switches and their utilisation during test
application.
• The concept of kernel - the structure in the circuit under
analysis which will be tested as a unit under test (i. e.
tested as an entity).
• Minimal kernel - the smallest part of the circuit that
included all the non-switch logic.
• Maximal kernel - the entire circuit excluding all scan
registers.

51
Partial scan methodologies based on the analysis
of circuit structure
scan register          scan register

I paths

Kmin
Kmax

scan register          scan register

The relation between maximal (Kmax) and minimal (Kmin)
kernels                                                      52
Partial scan methodologies based on the analysis
of circuit structure
Our activities in the area of „partial scan methodologies
based on the analysis of circuit structure“
• In our methodologies which we developed we concentrate
on possible role of registers during test application.
• We define following roles of registers which can be
assigned to them during the test application: TIR (Test
Input Register), TOR (Test Output Register), TDR (Test

53
Partial scan methodologies based on the analysis
of circuit structure
An example:
1     R1        n     TIR

I-path
I-path

TDR    1      R3      n      1     R2        n     TDR

DP2                   DP1

primary                                                            primary
inputs    TRV           R5                                   TRV   outputs
R4

I-path
I-path

1    R6        n     TOR

An example of an RTL circuit structure

54
Partial scan methodologies based on the analysis
of circuit structure
• Test input register (TIR) is the first register in the parallel I-path
between a primary input and a DP element. It may be either a register
whose input port is connected with a primary input in parallel or a
register which is the last one in the serial I-path through which the
test vectors for a DP element are scanned in.
• Test output register (TOR) is the last register in the parallel I-path
between the output of a DP element and a primary output. It may be
either a register whose output port is connected with a primary output
in parallel or a register which is the first one in the serial I-path
through which the test responses of a DP element are scanned out.
• One possibility how to test DP1 and DP2 through the registers R2, R3
(test drivers) and R4, R5 (test receivers), all converted to scan
registers.
55
Partial scan methodologies based on the analysis
of circuit structure
• The problem to be solved in the methodology can be described in the
following way:
• Let us have an RTL circuit in which registers are classified according
to their possible role during the test application phase. The goal is to
identify the minimum set of test input registers/test output registers
such that:
1) all test drivers are controllable from test input registers (i.e. I
paths exist between the output of test input registers and the inputs of
all test drivers),
2) all test receivers are observable in test output registers (i.e. I-
paths exist between the output of all test receivers and inputs of test
input registers).

56
Partial scan methodologies based on the analysis
of circuit structure

• Thus, the controllability/observability of DP elements is
provided through test input registers/test output registers
=> if the controllability/observability of test input
registers/test output registers is guaranteed then DP
elements are testable.
• Thus, the task we are solving is the problem of
controllability/observability of test input registers/test
output registers and the problem of covering all
TDRs/TRVs by TIRs/TORs.

57
Partial scan methodologies based on the analysis
of circuit structure
The method consists of 5 phases:
• Phase 1: The identification of elements in the circuit under
analysis.
• Phase 2: The allocation of test drivers and test receivers to
all DP elements.
• Phase 3: The allocation of test input registers to test
drivers and test output registers to test receivers.
• Phase 4: The identification of the minimal set of test input
registers through which all test drivers are controllable.
• Phase 5: The identification of the minimal set of test
output registers through which all test receivers are
observable.
58
Partial scan methodologies based on the analysis
of circuit structure
R1
An example:
MUX1
R2
ALU    R7    DP1

R3

MUX2   R8    DP2
R4

MUX3   R9    DP3
R5

R10   DP4

59
Partial scan methodologies based on the analysis
of circuit structure
The list of elements is constructed first, it has the folowing
structure.
• Type: item of the list
• Element: the name of the DP element.
• Test driver: the identification of the element test driver.
• Test input registers: the list of test input registers from
which the test driver can be controlled.
• Test receiver: the identification of the element test
• Test output registers: the list of test output registers in
which the test receiver can be observed.
60
Partial scan methodologies based on the analysis
of circuit structure
DP elements    DP1   DP2       DP3            DP4

Test drivers   R7    R8         R9            R10

R1    R3         R2            R5

Test           R2    R4         R5
Input
registers

R3

List of elements
R4

61
Partial scan methodologies based on the analysis
of circuit structure

Test drivers        R7         R8          R9          R10

Test
input                                 R3         R4            R5
R1         R2
registers

Relation between test input registers and test drivers

62
Partial scan methodologies based on the analysis
of circuit structure
The identification of the set of test input registers as candidates for the partial
scan is done in the following steps:
1) The unavoidable registers are identified: if there is a test driver which is
covered by only one test input register, then the test input register is
designated as unavoidable and must be included into the scan path. All the
test drivers covered by this node are removed from the graph.
2) For the pruning of the set of test input registers the following rules are
applied:
a) If a test input register A exists that covers the same set of test drivers as
the test input register B, then that test input register from which the test
drivers are more easily controllable is retained.
b) Let a test input register C cover a set of test drivers which form a subset
of test driver set covered by the test input register D. Then the test input
register D is retained.
63
Partial scan methodologies based on the analysis
of circuit structure
Test drivers           R7                R8

Test
input                                             R3        R4   R5
R1                R2
registers

Partial solution after applying Step 1

Register R5 is found to be an unavoidable register because it is
the only register which can control the register R10. Register
R10 was deleted from the graph together with the register R9
which is also controlled by the register R5.
64
Partial scan methodologies based on the analysis
of circuit structure
Test drivers                R7                 R8

Test
input                                                     R3   R5
R1                R2
registers
Partial solution after applying Step 2a)

Both registers R3 and R4 control the same set of test drivers,
namely R7, R8. For this purpose, the sequence of all control
signals (i.e. address, clock, enable) that must be generated to
transfer test patterns along the I-path is derived from the VHDL
model and evaluated. Register R4 was deleted.
65
Partial scan methodologies based on the analysis
of circuit structure

Test
input
R3             R5
registers
The solution after applying rule 2b)

Registers R1 and R2 cover the test driver R7 which is
covered by R3 register as well, therefore R1 and R2 can be
deleted from the graph

66
Partial scan methodologies based on the analysis
of circuit structure

• The solution: as TIR registers, R3 and R5 will be used
and included into the scan chain.
• The problem of allocating TIR registers to TDR registers is
solved as the problem of covering the set of TDRs by
TIRs.
• In the same way the problem of TOR registers will be
solved. The set of TRV registers will be covered by TORs.
• The results of this research were published at European
Test Workshop 1999 in Konstanze, Germany.

67
Partial scan methodologies based on the analysis
of circuit structure

Other results of our research in the area of developing
partial scan methodologies.
• We dealt with the analysis of I paths by means of theory
of graphs concepts and algorithms, the results were
published at European Test Conference 93 in Rotterdam.
• We also dealt with the RTL test scheduling, the results
were published at European Test Conference 93 in
Rotterdam.

68
Partial scan methodologies based on the analysis
of circuit structure

• Another approach of the RT level testability analysis is
based on the combination of analytical and evolutionary
approaches at the RT level.
• It offers solutions which are supposed to be used for
circuits with a high number of FFs - the solutions can be
denoted as suboptimal.
• The results were published at the EUROMICRO 2002,
Dortmund, September 2002.

69
Partial scan methodologies based on the analysis
of circuit structure

• Usual way how to solve a problem - to develop a model
and convert the problem to another one.
• Our approach - the structure of the circuit at RT level was
converted into a model by means of discrete mathematics
concepts. The analysis is done on this representation.
• The result: a paper published at IEEE DDECS 2002 and
PhD thesis (just under review) with the title: Formal
Approach to the Testability Analysis of RT Level
Digital Circuits.

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