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					                                 ECE 545
                                 Lecture 8

             Algorithmic State Machines

                           Sorting Example



ECE 545 – Introduction to VHDL               George Mason University
 Sources & Required Reading

• Stephen Brown and Zvonko Vranesic,
  Fundamentals of Digital Logic with VHDL Design
  Chapter 8.10
     Algorithmic State Machine (ASM) Charts
  Chapter 10.2.6
     Sort Operation
  (handouts distributed in class)




ECE 545 – Introduction to VHDL                     2
   Algorithmic State Machine (ASM)
                Charts




ECE 545 – Introduction to VHDL       3
 Algorithmic State Machine

 Algorithmic State Machine –
   representation of a Finite State Machine
   suitable for FSMs with a larger number of
   inputs and outputs compared to FSMs
   expressed using state diagrams and state
   tables.



ECE 545 – Introduction to VHDL                 4
 Elements used in ASM charts (1)
         State name


               Output signals                     0 (False)                      1 (True)
                                                                Condition
                 or actions
                                                                expression
               (Moore type)




                (a) State box                                 (b) Decision box



                                    Conditional outputs
                                  or actions (Mealy type)




                                 (c) Conditional output box


ECE 545 – Introduction to VHDL                                                              5
 Elements used in ASM charts (2)
 • State box – represents a state.
   Equivalent to a node in a state diagram or a row
   in a state table.
   Moore type outputs are listed inside of the box. It
   is customary to write only the name of the signal
   that has to be asserted in the given state, e.g., z
   instead of z=1. Also, it might be useful to write an
   action to be taken, e.g., Count = Count + 1, and
   only later translate it to asserting a control signal
   that causes a given action to take place.

ECE 545 – Introduction to VHDL                             6
 Elements used in ASM charts (3)
 • Decision box – indicates that a given condition is
   to be tested and the exit path is to be chosen
   accordingly
   The condition expression consists of one or more
   inputs to the FSM.

 • Conditional output box – denotes output
   signals that are of the Mealy type.
   The condition that determines whether such
   outputs are generated is specified in the decision
   box.
ECE 545 – Introduction to VHDL                          7
Moore FSM – Example 1: State diagram

                                  Reset

                                              w = 1
               w = 0             A z = 0               B z = 0

                                              w = 0

                                  w = 0                  w = 1



                                             C z = 1




                                              w = 1




ECE 545 – Introduction to VHDL                                       8
ASM Chart for Moore FSM – Example 1
                                         Reset



                                     A




                                 0
                                          w
                                              1

                                     B




                                 0
                                          w
                                              1


                                     C

                                          z




                                 0                1
                                          w



ECE 545 – Introduction to VHDL                        9
Mealy FSM – Example 2: State diagram



                                 Reset
                                         w = 1 z = 0


             w = 0 z = 0        A                      B   w = 1 z = 1


                                         w = 0 z = 0




ECE 545 – Introduction to VHDL                                               10
 ASM Chart for Mealy FSM – Example 2
                                         Reset




                                     A




                                 0
                                          w
                                                 1



                                     B

                                                         z




                                 0                   1
                                          w



ECE 545 – Introduction to VHDL                               11
 Control Unit Example: Arbiter (1)

                                  reset



            r1                             g1

            r2                   Arbiter   g2

            r3                             g3



                                  clock
ECE 545 – Introduction to VHDL                  12
 Control Unit Example: Arbiter (2)
                                       Reset                000


                                                     Idle

                                               0xx          1xx


                                                gnt1 g1 = 1


                                   x0x                      1xx   01x


                                                gnt2 g2 = 1


                                 xx0                        x1x     001


                                                gnt3 g3 = 1


                                                            xx1
ECE 545 – Introduction to VHDL                                            13
Control Unit Example: Arbiter (3)
                                                          r 1r 2 r 3
                                      Reset


                                                   Idle

                                              r1          r1


                                              gnt1 g1 = 1


                                      r2                  r1           r 1r 2


                                              gnt2 g2 = 1


                                 r3                       r2                r 1r 2 r 3


                                              gnt3 g3 = 1


                                                          r3


ECE 545 – Introduction to VHDL                                                           14
 ASM Chart for Control Unit - Example 3
                                        Reset



                                 Idle




                                                 1
                                            r1

                                        0            gnt1        1
                                                                      0
                                                            g1   r1

                                                 1
                                            r2
                                        0            gnt2        1
                                                                      0
                                                            g2   r2

                                 0               1
                                            r3

                                                     gnt3        1
                                                                      0
                                                            g3   r3



ECE 545 – Introduction to VHDL                                            15
                   Digital System Design
                         with VHDL




ECE 545 – Introduction to VHDL             16
 Structure of a Typical Digital System

         Data Inputs                       Control Inputs
                                 Control
                                 Signals
          Execution                            Control
             Unit                               Unit
          (Datapath)                          (Control)



        Data Outputs                       Control Outputs


ECE 545 – Introduction to VHDL                               17
 Hardware Design with RTL VHDL

                       Interface    Pseudocode



Execution Unit                                   Control Unit
                 Block                Block
                                                   ASM
                diagram              diagram




            VHDL code              VHDL code     VHDL code

ECE 545 – Introduction to VHDL                             18
                                 Sorting




ECE 545 – Introduction to VHDL             19
                Sorting - Required Interface

         Clock

         Resetn
                                 N          N
         DataIn                                 DataOut
                                 L
         RAdd
                                                Done
                                     Sort
          WrInit

          S
          (0=initialization
           1=computations)
         Rd


ECE 545 – Introduction to VHDL                            20
Simulation results for the sort operation (1)
Loading the registers and starting sorting




ECE 545 – Introduction to VHDL                  21
 Simulation results for the sort operation (2)
 Completing sorting and reading out registers




ECE 545 – Introduction to VHDL                   22
                           Sorting - Example
                                       During Sorting               After
           Before
           sorting       i=0     i=0    i=0   i=1    i=1     i=2    sorting
address                  j=1     j=2    j=3   j=2    j=3     j=3

  0            3         3       2      2     1       1      1      1
  1            2         2       3      3     3       3      2      2
  2            4         4       4      4     4       4      4      3
  3            1         1       1      1     2       2      3      4

 Legend:
                position of memory             position of memory
                                       Ri                           Rj
                   indexed by i                   indexed by j

ECE 545 – Introduction to VHDL                                            23
 Pseudocode for the sort operation

                                 for i = 0 to k – 2 do
                                       A = Ri ;
                                       for j = i + 1 to k – 1 do
                                             B = Rj ;
                                             if B < A then
                                                   Ri = B ;
                                                   Rj = A ;
                                                   A = Ri ;
                                             end if ;
                                       end for;
                                 end for;




ECE 545 – Introduction to VHDL                                     24

				
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