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Document Sample
Digital Radio Receiver
Amit Mane
System Engineer
Introduction
• Virtually all digital receivers perform channel access using
DDC
• The desired channel is translated using the digital mixer
comprised of multipliers and DDS
• The sample rate is then adjusted to match the channel
bandwidth
– CIC filter
– Two poly phase decimators
Introduction
• The functions performed in the system are
– Waveform synthesis (DDS)
– Complex multiplication
– Multirate filtering
• The overall sample rate change of the DDC is 120
• The DDS mixer has a SFDR of 102 dB
• The data rate can be upto 208 MHz
Introduction
• Innovative DRR System requires
– One Quadia
– Two UWBs
• Number of channels implemented = 40
Complete System
Block diagram
Digital Receiver Block Diagram
20 channels of I/Q @ 10
4.33 MSPS channel
DDR RAM
32--bit s of
16Mx16
I/Q @
A/D 1.0833M
12-bit SPS
A 130/208
UWB Quadia 16-bit
A Clock DCM
MSPS
A/D
1 of 2 Test Logic In = DSP1 EMIF Clk
Generato
1 of 2 Out = DSP1 EMIF Clk
Intf r
Dual Queue
VFIFO
1 of 20 channels 1 of 20 FIF
FIFO
channels O
Clock A/D CIC J4 J4 Test CFIR PFIR Spectral
Test
Data DSP1 DS
Clk Mixer Gain Flow Overflow
circuitry Mux 30:1 Link link Mux Registers
2:1 2:1 invert Mux Controlle detect P
r
FIFO FIFO
Interrupt
A/D s 10
A/D Intf NCO Test channel
B 12-bit Generator s of
130/208 I/Q @
MSPS 1.0833M
SPS
Registers Register Register
Test Controls
16-bit
A/D input select Spectral Inversion
2-bit 20-bit
Mixer Freq
Rev Code
Status DSP2 Registers
Overflow DSP
Gain DRR FIFO Thresh
Triggering detect
Test
Register
Rev Codes Interrupt
Clock DCM s
StatusRegister In = DSP2 EMIF Clk
Command DCMs locked Out = DSP2 EMIF Clk
Channel Reset
PCI FPGA
UWB
Filter Guide
Fpass= 490kHz
Fstop1= 541.666kHz
Fstop2= 1350kHz
Fs/2= 32500kHz
MATLAB Development System
DDC Frequency Response
MATLab SimuLink Development
• MATLab and Simulink
used with Xilinx System
Generator
• Simulink gateways
provide connection to
physical hardware and
connect with
Framework Logic
• End-to-end simulation
under MATLab
• JTAG link allows real
hardware to be tested
from MATLab
environment
• System Generator links
Xilinx tools for chip
design
Using Simulink and System Generator
• Simulink Block libraries are used to draw the system
• Innovative BSP provides blocks for UWB components
• Simulink blocks for DSP, data generation and viewing
• Xilinx System Generator links all blocks
Starting a
new
design!
Simulink Libraries
• Board Support Package for CS includes hardware and signal
processing components
• A/Ds, J4, DDCs ....
SimuLink Block Diagram
• The top level design has the Xilinx System Generator block
for integration with logic tools
Top Level
Design
Xilinx System Generator Integrates with
Simulink
• Compiling and fitting the design is done directly from the
Simulink environment
Design Using Simulink Blocks and Functions
• Large libraries of DSP and logic function may be directly used
• Drag-n-drop from Simulink libraries
Validating the Design
• Validate the design by including the hardware in the Simulink
• Hardware in the loop testing using JTAG
• Bit-true and cycle-true testing
Observe and
analyze real
data inside
Simulink
Flow data from
Simulink
through the
The Real
hardware and
back to Hardware
Simulink
Design Testing using Simulink
• Run real-time or Simulink test data through the actual
design
Execution
Control
VHDL Development Tools Flow
Quadia Application Logic Simulation
Multiple Channel on DSP 0
Ten Channels per DSP
Multiple Channel Operation
DSP 0 DSP 2
DSP 1 DSP 3
Spectral Inversion Testing
Before Spectral Inversion... 32.51 MHz Input
32.52 MHz Tune
fs = 129.843 MHz
9.7 kHz
Spectral Inversion Testing
32.51 MHz Input
After Spectral Inversion...
32.52 MHz Tune
fs = 129.843 MHz
531 kHz
Thank you !
