The HP 1660E and 1670E-Series Benchtop Logic Analyzers by AndyMcNelly

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The HP 1660E and 1670E-Series
Benchtop Logic Analyzers

Technical Data

                                                                                               Affordable logic analyzers
                                                                                               designed for your exact needs
HP’s new family of benchtop logic
analyzers includes four new series
of products, enabling design engi-
neers to purchase an affordable
logic analyzer that meets their
exact needs and matches their
budget. The units include a VGA
resolution color flat panel display
to help you find information quick-
ly and the well designed user inter-
face gets you to the answer in less
time. Users can use either a mouse
or the front panel to easily navigate
through the user interface. An
optional PC style keyboard is also
supported. A compact all-in-one
design also helps save space on a
crowded lab bench.
                                               Figure 1. HP’s new family of benchtop logic analyzers with color displays
The HP 1660ES-Series models come
with a built-in, 500-MHz, 2-GSa/s              _______________________________________________________________________________________
oscilloscope that can be triggered by          Model Number        HP 1660E              HP 1661E        HP 1662E          HP 1663E
the logic analyzer. Some of the                Channels            136                   102             68                34
tougher hardware debug problems                Application         General purpose logic analysis
can be found only with the digital
                                               Model Number        HP 1660EP             HP 1661EP           HP 1662EP     HP 1663EP
triggering capabilities of a logic
                                               Channels            136                   102                 68            34
analyzer and can only be solved
                                               Application         Hardware simulation and stimulus-response testing
with the analog resolution of an                                   with integrated 32-channel pattern generator
                                               Model Number        HP 1660ES            HP 1661ES            HP 1662ES     HP 1663ES
The pattern generator capability in            Channels            136                  102                  68            34
the HP 1660EP-Series allows                    Application         Parametric and mixed-signal testing with integrated
designers to substitute for missing                                two-channel oscilloscope
sub-systems during development.
                                               Model Number        HP 1670E            HP 1671E           HP 1672E
                                               Channels            136                 102                68
The HP 1670E-Series help simplify
                                               Application         Complex debugging and troubleshooting with deep memory
the capture and analysis of complex
events with 1M deep memory. Deep
memory is a valuable logic analyzer
feature for debugging embedded
microprocessor systems.

HP 1660E/ES/EP Series Logic Analyzer key                                                                                                                        HP 1660ES Series Oscilloscope
Specifications and Characteristics                                                                                                                              Key Specifications and
_______________________________________________________________________                                                                                         Characteristics
HP Model Number                     1660E/ES/EP              1661E/ES/EP                                            1662E/ES/EP         1663E/ES/EP   1664A
State and Timing                        136                      102                                                     68                 34          34      HP Model Number     1660ES, 1661ES
Channels                                                                                                                                                                            1662ES, 1663ES
Timing Analysis                     Conventional: 250 MHz all channels, 500 MHz half channels                                                                   Channels            2
                                    Transitional: 125 MHz all channels, 250 MHz half channels                                                                   Maximum Sample      2 GSa/s per channel
                                    Glitch: 125 MHz half channels                                                                                               Rate
State analysis speed                100 MHz, all channels                                                                                             50 MHz    Bandwidth           dc to 500 MHz
State Clock/Qualifiers                   6                 6                 4               2                                                          2                           (dc coupled)
Memory Depth                        4k per channel, 8k in half-channel modes                                                                                    Rise Time           700 ps
                                                                                                                                                                Vertical Resolution 8 bits
per Channel
                                                                                                                                                                Memory Depth per    32k samples
LAN Port                            Standard for all E/ES/EP models                                                                                       N/A   Channel

HP 1660EP Series Pattern Generator Key
Specifications and Characteristics
HP Model Number                                                                     1660EP, 1661EP, 1662EP, 1663EP
                                                                                                                                                                                                13.0 in. 14.5 in.
Maximum Clock Speed                        200 MHz                                            100MHz                                            50 MHz                                          (330 mm) (367 mm)
Number of Data Channels                    16                                                 32                                                32
Memory Depth, in vectors                   258,048                                            258,048                                           258,048
“IF” Command                               No                                                 No                                                Yes

HP 1670E-Series Logic Analyzer Key
Specifications and Characteristics
_______________________________________________________________________                                                                                                                         8.1 in.
HP Model Number       1670E                         1671E                     1672E                                                                                                             (205 mm)
State and Timing       136                           102                        68
________________________________________________________________________________                                                                                           17.3 inches
Timing Analysis           Conventional: 125 MHz all channels, 250 MHz half channels                                                                                        (440 mm)
State Analysis                              100 MHz, all channels                                                                                               Weight = 28.6 lbs. (13kg)
________________________________________________________________________________                                                                                Figure 3. Logic analyzer dimensions
State Clocks/           4                             4                          4                                                                              and weight
Memory Depth                  1M per channel, 2M in timing half-channel mode
per Channel

                                       quick menu keys
                                    done key      select key                         disk drive                                                                             line power             external
                          display                                      data entry keys                                                                          keyboard    module                 trigger BNC's

  H      1660ES


                                                   System    Config    Format

                                                   Trigger   Listing   Wave-

                                                   Done                Select   Clear                                           Run
                                                                                entry       C       D       E       F           Cont

                                                                                Don't                                           Stop
                                                                                care        8       9       A       B
                                                                                ±           4       5       6       7
                                                                                .           0       1       2       3           Print

                                                                                Q       W   E   R       T       Y   U   I   O      P

                                                                                A       S   D   F       G   H       J   K   L
                                                   Page                Page
                                                                                        Z   X   C       V   B       N   M

                                                                                                                                                                     *          *           *         *

                               movement keys
                                                       oscilloscope channels                                                                               RS-232-C       parallel LAN connectors
                                      power on/off                                                                                      HP-IB
                                                                                                                                        connector pattern connector       printer         * your number of pods
                                                 shift key                                                                                                          mouse connector
                                                                                                                                                  generator                               may be different
Figure 2. Diagram of logic analyzer’s front and rear panels                                                                                       (optional)
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics

_________________________              _________________________                 _________________________
Human Interface                        Alternate      The Epson FX80, LX80       Configuration Logic analyzer and
_________________________              Printers       and MX80 printers with     and Data Files oscilloscope files
          A knob and keypad
Front Panel                            Supported      an RS-232 or Centronics                   that include configura-
          make up the front-                          interface are supported                   tion and data informa-
          panel human interface.                       in the Epson 8-bit                       tion (if present) are
          Keys include control,                        graphics mode.                           encoded in a binary
          menu, display naviga-        _________________________                                format. They can be
          tion, and alpha-numer-       Hard Copy Screen images can be                           stored to or loaded
          ic entry functions.
_________________________              Output    printed in black and                           from the hard disk drive
Mouse     A DIN mouse is                         white or color from all                        or a flexible disk.
                                                 menus using the Print           _________________________
          shipped as standard                                                              Binary format
                                                                                 Recording of
          equipment. It provides                 field. State or timing
                                                 listings can be also be                   configuration/data files
          full instrument control.                                                         are stored with the
                                                                                 and Storage
          Knob functionality is                  printed in full or part
                                                 (starting from center           Times     time of acquisition and
          replicated by holding                                                            the time of storage.[1]
          down the right button                  screen) using the               _________________________
          and moving the mouse                   Print All selection.
                                       _________________________                 Acquisition Arming
          left or right. [1]           Mass Storage Files                        _________________________
_________________________                                                        Initiation   Arming is started by
Keyboard      The logic analyzer can
                                       and Software
                                       _________________________                              Run, Group Run, or the
              also be operated using   Updating the The operating system                      Port In BNC.
              a DIN keyboard. Order    Operating    resides in Flash ROM         _________________________
              the HP Logic Analyzer    System       and can be updated           Cross Arming Analyzer machines
              Keyboard Kit, model                   from the flexible disk                    and the oscilloscope
              number HP E2427B. [1]                 drive or from the                         or pattern generator
_________________________                           internal hard disk                        can cross-arm each
Input/Output, Control,                              drive. [1]                                other.
and Printing                           Mass Storage Supported by an inter-       Output              An output signal is
_________________________                                                                            provided at the Port
I/O Ports     All units ship with a                  nal hard disk drive and
                                                     by a 1.44 Mbyte, 3.5-                           Out BNC.
              Centronics parallel
                                                     inch flexible disk drive.
              printer port, RS-232,                                              PORT IN   Port In is a standard
              and HP-IB as standard                  Supports DOS and LIF
                                                     formats. [1]                Signal andBNC connection.
_________________________              _________________________                 ConnectionThe input operates at
                                       Screen Image An image file of any                   TTL logic signal levels.
LAN Interface An Ethernet LAN inter-                                                       Rising edges are valid
              face is standard. The    Files        display screen can be
                                                    stored to disk via the                 input signals.
              LAN interface comes
              with both Ethertwist                  display's Print field in
                                                    black & white or color       PORT OUT  Port Out is a standard
              and ThinLan connec-                                                Signal andBNC connection
              tors. The LAN supports                TIFF, color PCX, or
                                                    black & white                Connectionwith TTL logic
              FTP and PC/NFS con-                                                          signal levels. A rising
              nection protocols. It                 Encapsulated
                                                    PostScript™ (EPS)                      edge is asserted as a
              also works with X11                                                          valid output.
              windows packages. [1]                 formats.
_________________________                                                        Skew      Correction factors for
Program-   Each instrument is fully    ASCII DataState or timing listings        Adjustmentnominal skew between
mability   programmable from a         Files     can be stored as ASCII                    displayed timing and
           computer via HP-IB,                   files on a disk via the                   oscilloscope signals
           RS-232 and LAN con-                   display's Print field.                    are built into the oper-
           nections. [1]
_________________________                        These files are equiva-                   ating system.
HP Printer Printers which use the                lent in character width                   Additional correction
Support    HP Printer Control                    and line length to hard-                  for unit-by-unit varia-
           Language (PCL) and                    copy listings printed via                 tion can be made using
           have a parallel                       the Print All selection.
                                       _________________________                           the Skew field. An
           Centronics, RS-232 or                                                           entered skew value
           HP-IB interface are                                                             affects the next (not
           supported:                                                                      the present) acquisition
           HP DeskJet, LaserJet,                                                           display.
           QuietJet, PaintJet, and
           ThinkJet models
_________________________                                                        1] Please refer to HP 1664A Product Specifications
                                                                                    and Characteristics on page 7.
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)

_________________________                              _________________________                         _________________________
PORT IN   15 ns typical delay                          Physical Factors                                  +5 V        1/3 amp maximum
                                                       _________________________                         Accessory per pod
Arms Logicfrom signal input to a
          don't care logic
Analyzer [2]                                           Safety         IEC 348/ HD 401,                   Current
                                                                      UL 1244, and                       _________________________
          analyzer trigger.
_________________________                                                                                Channel     Each group of 34
                                                                      CSA Standard C22.2
PORT IN      40 ns typical delay                                      No. 231 (series M-89)              Assignment channels (a pod pair)
Arms         from signal input to an
                                                       _________________________                                     can be assigned to
                                                       EMC                                                           Machine 1, Machine 2
Oscilloscope immediate oscilloscope
                                                       CISPR 11:1990/EN 55011 (1991):                                or remain unassigned.
_________________________                                Group 1 Class A                                             The HP 1663E/ES/EP
Logic        120 ns typical delay                      IEC 801-2:1991/EN 50082-1 (1992):                             and the HP 1664A do
Analyzer     from logic analyzer                         4kV CD, 8 kV AD                                             not have a Machine 2.
Arms PORT trigger to signal                            IEC 801-3:1984/EN 50082-1 (1992): 3 V/m           ______________________________
OUT [2]      output.
_________________________                              IEC 801-4:1988/EN 50082-1 (1992): 1kV             State Analysis
                                                       _________________________                         _________________________
Oscilloscope 60 ns typical delay from                                                                    Maximum   100 MHz[1] all models
Arms PORT oscilloscope trigger to                      _________________________                         State
OUT          signal output.
_________________________                              Logic Analyzer Probes                             Speed*
                                                       _________________________                         _________________________
Operating Environment
_________________________                              Input       100 kΩ ±2%                            Memory
Power       115 Vac or 230 Vac,                        Resistance
                                                       _________________________                         Depth per
            –22% to +10%, single                       Input       approx. 8 pF                          Channel
            phase, 48-66 Hz, 320 VA                    Capacitance (see figure 4)
                                                       _________________________                         HP 1660E/ES/ 4k samples std.
_________________________                                                                                EP Series    Time tags on:
Temperature Instrument, 0° to 50° C                                   RT = 250Ω       CCOMP = 7.5 pF
                                                                                                                      2k samples
            (+32° to 122° F). Disk
            media, 10° to 40° C                                                                          HP 1670E  1M samples standard
            (+50° to 104°F). Probes                             CTG = 1 pF     RIN = 100kΩ        Z0 =   Series    Time Tags On:
                                                                                                  150Ω             500k samples
            and cables, 0° to 65° C                                                                                Compare Mode On:
            (+32° to 149° F)
_________________________                                                                                          250k samples
Humidity    Instrument, up to 95%,                      High Frequency Model for Probe Inputs                      Compare Mode
            relative humidity at                                                                                   and Time Tags On:
            +40° C (+140° F). Disk                     Figure 4                                                    120k samples
            media and hard drive,                      _________________________                         State Clocks Clock edges can be
            8% to 85% relative                         Minimum       500 mV peak-to-peak                              ORed together and oper-
_________________________                              Input Voltage                                                  ate in single phase, two-
                                                       Swing                                                          phase demultiplexing, or
Altitude  To 3,048 m (10,000 ft)
                                                       _________________________                                      two-phase mixed mode.
_________________________                              Minimum       250 mV or 30% of input                           Clock edge is selectable
Vibration:Random vibrations                            Input         amplitude, whichever is                          as positive, negative, or
Operating 5–500 Hz,                                    Overdrive     greater                                          both edges for each
          10 minute per axis,
                                                       _________________________                                      clock.
                                                       Threshold     –6.0 V to +6.0 V in 50-mV
          ~ 0.3 g (rms).
_________________________                                                                                          The high or low voltage
                                                                                                         State Clock
                                                       Range         increments
                                                       _________________________                         Qualifier level of up to 4 of the 6
Vibration:    Random vibrations                        Threshold     Threshold levels may be                       clocks can be ANDed
Non Operating 5–500 Hz,10 minutes per                  Setting       defined for pods                              or ORed with the clock
              axis,~ 2.41 g (rms); and                               (17-channel groups) on                        specification.
              swept sine resonant                                    an individual basis
              search, 5–500 Hz,                        _________________________                         Setup/Hold* [4]
                                                       Threshold     ± (100 mV +3% of                    one clock,      3.5/0 ns to 0/3.5 ns
              0.75 g (0-peak),                                                                           one edge        (in 0.5 ns increments)
              5 minute resonant dwell                  Accuracy*     threshold setting)
              @ 4 resonances per                       Input         ± 10 V about the                    one clock,     4.0/0 ns to 0/4.0 ns
_________________________                              Dynamic       threshold                           both edges     (in 0.5 ns increments)
[1] Please refer to HP 1664A Product Specifications    Maximum       ± 40 V peak                         multi-clock, 4.5/0 ns to 0/4.5 ns
    and Characteristics on page 7.                                                                       multi-edge   (in 0.5 ns increments)
                                                       Input Voltage
[2] Time may vary depending upon the mode of logic
    analyzer operation.

* Warranted specification.

[3] Full channel /half channel modes
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)

Minimum       3.5 ns                      Time Covered Sample period ×             Time Interval Accuracy
State Clock                               by Data [3]  memory depth
                                          _________________________                Sample    ± 0.01%
Pulse Width* [4]
_________________________                 Transitional   (HP 1660E/ES/EP Series    Period
Minimum         10.0 ns                   Timing         only) Sample is stored    Accuracy
Master to                                                in acquisition memory
Master                                                   only when the data        Channel-to- 2 ns typical,
Clock Time* [4]                                          changes. A time tag       Channel Skew3 ns maximum
                                                         stored with each          Time Interval ± (Sample Period
Minimum        10.0 ns                                   sample allows recon-
Slave to                                                                           Accuracy      Accuracy + channel-
                                                         struction of waveform
Slave                                                    display. Time covered                   to-channel skew +
Clock Time [4]
_________________________                                by a full memory acqui-                 0.01% of time interval
                                                         sition varies with the                  reading)
Minimum        0.0 ns
Master to                                                number of pattern         Maximum   Sample Period 2-8 ns :
Slave                                                    changes in the data.      Delay     8.389 ms
Clock Time [4]
_________________________                                                          After     Sample Period > 8 ns:
                                          Time Covered 16.3 µs minimum,
Minimum        4.0 ns                     by Data [3]  9.7 hrs./6.5 hrs.           Triggering1,048,575 × sample
Slave to Master                                        maximum                               period
Clock Time [4]
_________________________                 Maximum         34.4 s                   Trigger Specifications
Clock          4.0/0 ns (fixed)           Time                                     _________________________
Qualifiers                                Between                                  Trigger     Trigger setups can be
Setup/Hold [4]                            Transitions                              Macros      selected from a cate-
                                          Number of       1023-2047/682-4094                   gorized list of trigger
State         Counts the number of
                                          Captured        Depending on input                   macros. Each macro is
Tagging [5]   qualified states
                                          Transitions [3] signals                              shown in graphical
              between each stored         _________________________                            form and has a written
              state. Measurement          Glitch         (HP 1660E/ES/EP Series                description. Macros
              can be shown relative       Capture        only.) Data sample and                can be chained togeth-
              to the previous state or    Mode           glitch information is                 er to create a custom
              relative to trigger. Max.                  stored every sample                   trigger sequence.
              count is 4.29 × 109.                       period.
_________________________                                                          Pattern     Each recognizer is the
Time          Measures the time                                                    Recognizers AND combination of bit
Tagging [5]   between stored states,      Maximum      125 MHz                                 (0,1, or X) patterns in
              relative to either the                                                           each label. Ten pattern
                                          Timing Speed
              previous state or to the                                                         recognizers are avail-
              trigger. Max. time          Sample        8 ns minimum, 8.38 ms                  able.
              between states is
                                          Period        maximum                    Minimum     >125 MHz timing modes:
              34.4 sec. Min. time
                                          Minimum       3.5 ns                     Pattern and 13 ns + channel-to-
              between states is 8 ns.
                                          Glitch Width*                            Range       channel skew
Time Tag   8 ns or 0.1% (whichever                                                 Recognizer ≤125 MHz timing modes:
                                          Maximum      Sample Period – 1 ns        Pulse Width 1.01 x (1 sample period
Resolution is greater)
_________________________                 Glitch Width                                         +1 ns + channel-to-
Timing Analysis
_________________________                 Memory         2048 samples                          channel skew )
                                          Depth per                                _________________________
Conventional Data stored at selected
Timing       sample rate across all       Channel
             timing channels.             Time Covered Sample Period × 2048:       [3] Full Channel /Half Channel Modes
                                          by Data      16.3 µs minimum,
HP 1660 Series                                                                     [4] Specified for an input signal VH= – 0.9V, VL = – 1.7V,
                                                       17.1 sec maximum
Sample        4 ns/2 ns minimum,                                                       slew rate = 1V/ns, and threshold = –1.3V
Period [3]    8.38 ms maximum
                                                                                   [5] Time or-state-tagging (Count Time or Count State)
                                                                                       is available in the full-channel state mode. There is
HP 1670 Series                                                                         no speed penalty for tag use. Memory is halved
Sample        8 ns/4 ns minimum,                                                       when time or state tags are used unless a pod pair
                                                                                       (34-channel group) remains unassigned in the
Period [3]    41 ms/10 ms maximum                                                      Configuration menu.

                                                                                   * Warranted specification.
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)

_________________________                 _________________________               _________________________
Range          Recognize data which is    Maximum       125 MHz                   Trigger   Displayed as a vertical
Recognizers    numerically between or     Sequencer                                         dashed line in the
               on two specified pat-      Speed                                             timing waveform, state
               terns (ANDed combina-                                                        waveform and X-Y
               tion of zeros and/or       State         12                                  chart displays and as
               ones). Two range recog-    Sequence                                          line 0 in the state listing
               nizers are available.      Levels                                            and state compare dis-
Range Width 32 channels
_________________________                 Timing    10
                                                                                  Activity  Provided in the
Edge/Glitch Trigger on glitch or          Sequence
                                                                                  IndicatorsConfiguration, State
Recognizers edge on any channel.          Levels
                                          _________________________                         Format, and Timing
            Edge can be specified         Timers        Timers may be Started,              Format menus for moni-
            as rising, falling or                       Paused, or Continued at             toring device-under-
            either.                                     entry into any sequence             test activity while set-
                                                        level after the first.              ting up the analyzer.
Edge/Glitch    2 (in timing mode only)
                                                                                  Labels    Channels may be
Recognizers                               Timers        2
                                                                                            grouped together and
                                                                                            given a 6-character
Edge/Glitch Sample Period 2-8 ns:         Timer Range   400 ns to 500 seconds
                                                                                            name called a label. Up
Recovery Time 28 ns
                                                                                            to 126 labels in each
              Sample Period > 8 ns:       Timer         16 ns or 0.1% whichever
                                                                                            analyzer may be
              20 ns + sample period
_________________________                 Resolution    is greater
                                                                                            assigned with up to 32
Qualifier A user-specified term                                                             channels per label.
          that can be any state, no       Timer         ± 32 ns or ± 0.1%,
                                                                                            Trigger terms may be
          state, any recognizer,          Accuracy      whichever is greater
                                                                                            given an 8-character
          (pattern, ranges or                                                               name.
          edge/glitch), any timer,        Timer         70 ns
          or the logical combina-         Recovery Time
                                          _________________________               Measurement Functions
          tion (NOT, AND, NAND,           Acquisition, Measurement                Markers   Two markers (x and o)
          OR, NOR, XOR, NXOR) of                                                            are shown as dashed
          the recognizers and
                                          and Display Functions
                                          _________________________                         lines in the display.
_________________________                 Run       Starts acquisition of
                                                                                  Time      The x and o markers
                                                    data in specified trace
Branching Each sequence level                                                     Intervals measure the time
          has a branching qualifi-                                                          interval between events
          er. When satisfied, the         Stop      In single trace mode or                 occurring on one or
          analyzer will branch to                   the first run of a repeti-              more waveforms or
          the sequence level                        tive acquisition, stop                  states (available in state
_________________________                           halts acquisition and                   when time tagging is on).
                                                    displays the current
OccurrenceQualifiers may be                                                       Delta States The x and o markers
                                                    acquisition data. For
Counters  specified to occur up to                                                             measure the number of
                                                    subsequent runs in
          1,048,575 times before                                                               tagged states between
                                                    repetitive mode, stop
          advancing to the next                                                                any two states (state
                                                    halts acquisition of
          level. Each sequence                                                                 only).
                                                    data and does not
          level has its own                                                       Patterns  The x or o marker can
                                                    change current display.
          counter. The maximum                                                              be used to locate the
          occurrence count is             Trace ModeSingle mode acquires
                                                                                            nth occurrence of a
_________________________                           data once per trace
                                                                                            specified pattern
                                                    specification; repetitive
Storage       Each sequence level                                                           before or after trigger.
                                                    mode repeats single
Qualification has a storage qualifier                                                       The o marker can also
                                                    mode acquisitions until
(state only)  that specifies the states                                                     find the nth occurrence
                                                    stop is pressed or until
              that are to be stored.
_________________________                                                                   of a pattern before or
                                                    pattern time interval or
                                                                                            after the x marker.
                                                    compare stop criteria
                                                    are met.
HP 1660E and 1670E-Series
Logic Analyzer Specifications
and Characteristics (cont.)

Statisticsx to o marker statistics        Data Display
                                          _________________________                               label. When data display
          are calculated for              Display   State listing, state                          is “Symbol”, mnemonic
          repetitive acquisitions.        Modes     waveforms, state chart,                       is displayed where the
          Patterns must be speci-                   state compare listing,                        bit pattern occurs.
          fied for both markers,                    compare difference list-
          and statistics are kept                                                  Range          User can define a
                                                    ing, timing waveforms,
          only when both pat-                                                      Symbols        mnemonic covering a
                                                    timing listing, interleaved
          terns can be found in                                                                   range of values.
                                                    time-correlated listing of
          an acquisition.                           two state analyzers (time
          Statistics are minimum                                                   Symbol         Symbolic information
                                                    tags on), and time-corre-
          x to o time, maximum x                                                   Utility        extracted from popular
                                                    lated state listing with
          to o time, average x to                                                                 object module formats
                                                    timing waveforms on the
          o time, and ratio of                                                                    can also be used.
                                                    same display.
          valid runs to total runs.
_________________________                                                          Number of 1000 maximum.
                                          State X-Y     Plots value of a speci-
Compare       Performs post-process-      Chart Display fied label (on y-axis)     Symbols
Mode          ing bit-by-bit                            versus states or another   System      SPA includes state
Functions     comparison of the                         label (on x-axis). Both    Performance histogram, state
              acquired state data and                   axes can be scaled.        Analysis    overview and time inter-
              compare image data.         _________________________
                                          State     Displays state                             val measurements to aid
Compare       Created by copying a        Waveform  acquisitions                               in the software opti-
Image         state acquisition into      Display   in waveform format.                        mization process. These
              the compare image
                                          _________________________                            tools provide a statisti-
              buffer. Allows editing of   Timing    Displays timing                            cal overview of your
                                          Listing   acquisition in listing                     synchronous design.
              any bit in the compare
                                          Display   format.                        _________________________
              image to a 1, X or O.       _________________________
Compare       Each channel (column)       Waveform                                 The HP 1664A
Image         in the compare image        Display                                  Specifications and
Boundaries    can be enabled or dis-                                               Characteristics
              abled via bit masks in                                               ______________________________
              the compare image.          Accumulate    Waveform display is
                                                        not erased between         The HP 1664A is a low-cost version of
              Upper and lower ranges                                               the HP 1660E/ES/EP-series logic ana-
              of states (rows) in the                   successive acquisitions.
                                                                                   lyzer family. The HP 1664A has some
              compare image can be        Overlay Mode Multiple channels can       specifications and characteristics that
              specified. Any data bits                 be displayed on one         are different from the HP 1660E/ES/EP-
              that do not fall within                  waveform display line.      series logic analyzers.
              the enabled channels                     When waveform size is
              and the specified range                  set to large, the value   The HP 1664A:
              are not compared.                        represented by each     • Supports a maximum of 50 MHz state
Stop        Repetitive acquisitions                    waveform is displayed     acquisition
Measurement may be halted when                         inside the waveform in • Weight 26 pounds (11.8 kg)
            the comparison                             the selected base.      • Altitude To 15,000 ft (4,752 m)
            between the current           Displayed    24 lines maximum on     • Boots from the floppy disk drive—it
            state acquisition and the     Waveforms one screen. Up to 96         does not have flash ROM
            current compare image                      lines may be specified  • It cannot be upgraded to include an
            is equal or not equal.
_________________________                              and scrolled through.     oscilloscope or pattern generator
                                          _________________________ • The mouse and keyboard connectors
Compare   Reference Listing               Bases        Binary, octal, decimal,
Mode      display shows the                                                      are HP HIL standard
                                                       hexadecimal, ASCII      • For the optional keyboard order
Displays  compare image and                            (display only), user-
          bit masks; difference                                                  HP E2427A
                                                       defined symbols, two's • It does not support the symbol utility
          listing display highlights                   complement.
          differences between the         _________________________ • It does not support the software per-
          current state                   Symbols                                formance analysis (SPA) software
          acquisition and the                                                  • It does not have a real time clock
                                          Pattern      User can define a       • It does not have a hard disk drive
          compare image.
_________________________                 Symbols      mnemonic for the spe- • It does not have a LAN port
                                                       cific bit pattern of a
HP 1660ES-Series
Oscilloscope Specifications
and Characteristics

__________________________________     __________________________________          ______________________________
General Information
________________________________       Horizontal
                                       ________________________________ Events Delay Triggers on the nth edge
                                                                                               or pattern as specified
Model       HP 1660ES, 1661ES,         Time Base        0.5 ns/div to 5 s/div                  by the user. Time-quali-
Numbers     1662ES, 1663ES
________________________________       Range
                                       ________________________________                        fication is applied only
Number of   2                          Time Interval ± [(0.005% of ∆t)                         to the 1st of n patterns.
________________________________       Measurement + (2×10 – 6 × delay            Auto-Trigger Self-triggers if no trig-
                                       Accuracy         setting) + 150 ps]                     ger condition is found
Maximum     2 GSa/s per channel        [9] [10]
Sample Rate                                                                                    ~ 50 ms after arming.
                                       ________________________________ ________________________________
                                       Oscilloscope Triggering
                                       ________________________________ Measurement Functions
Bandwidth   dc to 500 MHz                                                         ________________________________
[6] [10]    (real time, dc coupled)    Trigger Level Bounded within chan-
________________________________                                                  Time Markers Two markers (x and o)
                                       Range            nel display window
                                       ________________________________                        measure time intervals
Rise Time   700 ps
[7] [10]                               Trigger          dc to 50 MHz:                          manually, or automati-
________________________________                                                               cally with statistics.
                                       Sensitivity [10] 0.063 × Full Scale        ________________________________
Vertical    8 bits full scale                           50 MHz to 500 MHz:        Voltage      Two markers (a and b)
________________________________                        0.125 × Full Scale
                                       ________________________________ Markers                measure voltage and
Memory Depth32k samples                Trigger Modes                                           voltage differences.
Oscilloscope Probing                                                              Automatic    Period, frequency,
________________________________       Immediate        Triggers immediately      Measurementsrise time, fall time,
Input Coupling1 MΩ: ac,dc                               after arming condition is              +width, –width, peak-to-
              50 Ω: dc only                             met. (Arming condition                 peak voltage, over-
________________________________                        is Run, Group Run,                     shoot, and undershoot.
Input R [10]  1MΩ ± 1%                                  cross arming signal, or
              50Ω ± 1%                                  Port In BNC signal).
Input C       ~ 7pF
________________________________       Edge           Triggers on rising or
                                                      falling edge from chan-
Probes      Two HP 1160A probes;                      nel 1 or 2.
Included    10:1, 10 MΩ, 9 pF
            1.5 meters
________________________________       Pattern       Triggers on entering or
Vertical (at BNC)                                    exiting logical pattern
________________________________                     specified across chan-
Maximum       1 MΩ : ±250 V                          nels 1 or 2. Each chan-
Safe Input    50 Ω : 5 V rms                         nel can be specified as
Voltage                                              high (H), low (L), or don't
________________________________                     care (X) with respect to
Vertical      16 mV full scale to                    the level settings in the
Sensitivity   40 V full scale                        edge trigger menu.
Range                                                Patterns must be
(1:1 Probe)
________________________________                     >1.75 ns in duration to
                                                     be recognized.
Probe Factors Any integer ratio from
              1:1 to 1000:1
________________________________       Time-QualifiedTriggers on the exiting
                                       Pattern       edge of a pattern which
Vertical (dc) ± 1.25% of full scale                  meets the user-speci-
Gain                                                 fied duration criterion.
Accuracy [8]
________________________________                     Greater than, less than,
dc Offset     ± 2V to ± 250V                         or within range duration
                                                     criterion can be used.        [6] Upper bandwidth reduces by 2.5 MHz for every
Range         (depending on the                                                        degree C above 35°C.
(1:1 probe)   vertical sensitivity)                  Duration range is 20 ns
________________________________                     to 160 ns. Recovery           [7] Rise time calculated as tr =      0.35
                                                     time after valid patterns                                        bandwidth
dc Offset     ± [1.0% of channel
Accuracy [10] offset + 2.0% of full                  with invalid duration is      [8] Vertical gain accuracy decreases 0.08% per
               scale]                                <12 ns.
                                       ________________________________                degree C from software calibration temperature.
Voltage       ± [1.25% of full scale                                               [9] Specification applies at the maximum sampling
                                                                                       rate. At lower rates, replace 150 ps in the formula
Measurement + offset accuracy                                                          with ( 0.15 × sample interval) where sample inter-
Accuracy [10] + 0.016 V/div]
 ______________________________                                                        val is defined as 1/sample rate.

Channel-to- dc to 50 MHz – 40 dB                                                   [10] Specifications (valid within ± 10°C of auto-calibra-
Channel       50 MHz to 500 MHz                                                         tion temperature)
Isolation     – 30 dB
HP 1660EP-Series Pattern
Generator Characteristics

Maximum memory depth                                                  258,048 vectors
Number of output channels at 100 MHz to 200 MHz clock                 16
Number of output channels at ≤100 MHz clock                           32
Maximum number of “IF Condition” blocks at ≤50 MHz clock              1
Maximum number of different macros                                    100
Maximum number of lines in a macro                                    1024
Maximum number of parameters in a macro                               10
Maximum number of macro invocations                                   1,000
Maximum loop count in a repeat loop                                   20,000
Maximum number of repeat loop invocations                             1,000
Maximum number of Wait event patterns                                 4
Number of input lines to define a wait pattern                        3
Maximum width of a label                                              32 bits
Maximum number of labels                                              126

Lead Set Characteristics

HP 10474A 8-channel probe lead set        Provides most cost effective lead set for the
                                          HP 1660EP-series clock and data pods. Grabbers are
                                          not included.
HP 10347A 8-channel probe lead set        Provides 50 Ω coaxial lead set for unterminated signals,
                                          required for HP 10465A ECL Data Pod (unterminated).
                                          Grabbers are not included.

Data Pod Characteristics

Output type                10H125 with 100 Ω series
Maximum clock              200 MHz
Skew (note 1)              typical < 2 ns; worst case = 4 ns
Recommended lead set       HP 10474A

                                          100 Ω

Output type                74ACT11244 with 100 Ω series; 10H125 on non 3-state channel 7 (note 2)
3-state enable             negative true, 100 KΩ to GND, enabled on no connect
Maximum clock              100 MHz
Skew (note 1)              typical < 4 ns; worst case = 12 ns
Recommended lead set       HP 10474A

                                          100 Ω

HP 10464A ECL DATA POD (TERMINATED)                                                                          Clock Pod Characteristics
Output type                  10H115 with 330 Ω pulldown, 47 Ω series
Maximum clock                200 MHz                                                                         10460A TTL CLOCK POD

Skew (note 1)                typical < 1 ns; worst case = 2 ns                                               Clock output type         10H125 with 47 Ω
                                                                                                                                       series; true & inverted
Recommended lead set         HP 10474A
                                                                                                             Clock output rate         100 MHz maximum

                                                          47 Ω                                               Clock out delay           11 ns maximum in 9
               10H115                                                                                                                  steps
                                           330 Ω                                                             Clock input type          TTL – 10H124
                                                      – 5.2 V                                                Clock input rate          dc to 100 MHz
                                                                                                             Pattern input type        TTL – 10H124
HP 10465A ECL DATA POD (UNTERMINATED)                                                                                                  (no connect is logic 1)
Output type                  10H115 (no termination)                                                         Clock-in to clock-out     approximately 30 ns
Maximum clock                200 MHz                                                                         Pattern-in to recognition approx. 15 ns + 1 clk
Skew (note 1)                typical < 1 ns; worst case = 2 ns                                                                         period

Recommended lead set         HP 10347A                                                                       Recommended lead set      HP 10474A

                                                                                                                                                  47Ω        CLKout
                 10H115                                                                                                  10H125

HP 10466A 3-STATE TTL/3.3 VOLT DATA POD                                                                                 10H124
Output type                  74LVT244 with 100 Ω series; 10H125 on non 3-state channel 7 (note 2)
3-state enable               negative true, 100 KΩ to GND, enabled on no connect                             10463A ECL CLOCK POD
Maximum clock                200 MHz                                                                         Clock output type         10H116 differential
Skew (note 1)                typical < 3 ns; worst case = 7 ns                                                                         unterminated; and
                                                                                                                                       differential with 330 Ω
Recommended lead set         HP 10474A                                                                                                 to –5.2V and 47 Ω

                                                  100 Ω                                                      Clock output rate         200 MHz maximum
                                                                                                             Clock out delay           11 ns maximum in 9
                74LVT244                                                                                                               steps
                                                                                                             Clock input type          ECL – 10H116 with
                                                                                                                                       50 KΩ to –5.2v
Note 1: Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND;
worst case skew numbers are a calculation of worst case conditions through circuits.                         Clock input rate          dc to 200 MHz

Note 2: Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping   Pattern input type        ECL – 10H116 with
this output back into the 3-state enable line, the channel can be used as a 3-state enable.                                            50 KΩ (no connect is
                                                                                                                                       logic 0)
                                                                                                             Clock-in to clock-out     approximately 30 ns
Data Cable Characteristics Without a Data Pod
                                                                                                             Pattern-in to recognition approx. 15 ns + 1 clk
The HP 1660EP data cables without a data pod provide an ECL terminated (1 KΩ to –5.2V) differen-
tial signal (from a type 10E156 or 10E154 driver). These are usable when received by a differential          Recommended lead set      HP 10474A
receiver, preferably with a 100 Ω termination across the lines. These signals should not be used
single ended due to the slow fall time and shifted voltage threshold (they are not ECL compatible).
16522A DATA CABLE Output
HP 1660EP Data CableOUTPUT
                                                                                                                                       VBB                  50 KΩ
                                         –5.2 V                                                                                                  –5.2 V

                                                                                                                                        –5.2 V

                                               1 KΩ
                                                                                                                                             330 Ω

                                                                                                                        10H116                            47 Ω   CLKout
        or                                                                   Differential
      10E154                                                                 Output

                                               1 KΩ

                                         –5.2 V
Probing Alternatives for
the HP 1660E/ES/EP
and 1670E-Series Logic

Probing the device under test is           Probing Alternative       Advantages                          Limitations
both one of the potentially most           General Purpose           Most flexible method. Works in       Can be cumbersome
difficult and certainly one of the         Lead Sets and Surface     conjunction with SMD clips and Wedge when connecting
most important tasks in debugging          Mount Grabbers            adapters listed below. Included with a large number
a digital design. That is why HP                                     logic analyzer purchase.             of channels
provides a wider variety of probing        Ultra-Fine Pitch Surface  Smallest IC clips in the industry to date Same as above plus
                                           Mount Device Clips        (down to 0.5 mm). Works with both logic   small incremental cost
solutions than anyone else in the
                                                                     analyzer and scope probing systems.
industry—each with a different set
                                           HP Wedge probe adapter    Compressible dual conductors between      Same as above plus
of advantages particular to a given        for QFP Packages          adjacent IC legs make 3-8 adjacent signal small incremental cost
situation. We like to think of it as                                 leads available to logic analyzer and
helping you get your signals off to                                  scope probing systems.
a great start.                             Elastomeric and Locator   Provides access to all signal leads for  Requires minimal
                                           Base Solutions for Genericgeneric QFP packages (including custom keep out area.
                                           QFP Packages              ICs). Uses combination of one probe      Moderate to significant
                                                                     adapter and four flexible adapters, plus incremental cost.
                                                                     general-purpose lead sets.
                                           Direct Connection to      Very reliable and convenient probing      Requires advance
                                           Device Under Test via     system when frequent probing              planning to integrate
                                           Built-In Connectors       connections are required (mfg. or field   into design process.
                                                                     test for example). Connectors can be      Moderate (normal
                                                                     located at optimal position in the device density) to significant
                                                                     under test. Can work in conjunction with  (high density)
                                                                     HP provided inverse assemblers.           incremental cost.
                                           HP Analysis Probes        Support for over 200 different      Requires moderate
                                           for Specific Processors   processors and buses. Includes      clearance around
                                           and Buses                 reliable logic analyzer probe       processor or bus.
                                                                     pod connectors, logic analyzer      Moderate to significant
Figure 5. General-purpose lead sets                                  configuration files and device      extra cost depending on
                                                                     specific inverse assemblers.        specific processor or bus.

Figure 6. Ultra-fine pitch surface mount
device clips

                                           HP Wedge Probe Adapter
                                           IC leg spacing   Number of signals Number of Wedges in pack    HP model number
                                           0.5 mm                  3                     1                   HP E2613A
                                           0.5 mm                  3                     2                   HP E2613B
                                           0.5 mm                  8                     1                   HP E2614A
                                           0.65 mm                 3                     1                   HP E2615A
                                           0.65 mm                 3                     2                   HP E2615B
                                           0.65 mm                 8                     1                   HP E2616A

Figure 7. HP Wedge probe adapters for
QFP package

Probing Solutions
Package type         Pin Pitch   Elastomeric solutions         Locator base solutions
304-pin PQFP/CQFP   0.5 mm                                    HP E5331A probe adapter
                                                              HP E5333A flexible adapter
240-pin PQFP/CQFP   0.5 mm     HP E5363A probe adapter        HP E5315A probe adapter
                               HP E5371A 1/4-flexible adapter HP E5316A flexible adapter
                                                              HP E5330A rigid adapter
208-pin PQFP/CQFP   0.5 mm     HP E5374A probe adapter        HP E5318A probe adapter
                               HP E5371A 1/4-flexible adapter HP E5316A flexible adapter
                                                              HP E5330A rigid adapter
184-pin PQFP/CQFP   0.5 mm                                    HP E5343A probe adapter
                                                              HP E5316A flexible adapter
                                                              HP E5330A rigid adapter
176-pin PQFP        0.5 mm     HP E5348A probe adapter
                               HP E5349A 1/4-flexible adapter
160-pin QFP         0.5 mm     HP E5377A probe adapter
                               HP E5349A 1/4-flexible adapter
160-pin PQFP/CQFP   0.65 mm    HP E5373A probe adapter        HP E5319A probe adapter
                               HP E5349A 1/4-flexible adapter HP E5316A flexible adapter
                                                              HP E5330A rigid adapter
144-pin PQFP/CQFP   0.65 mm    HP E5361A probe adapter
                               HP E5340A 1/4-flexible adapter
                                                                                                Figure 8. Elastomeric probing solution
144-pin TQFP        0.5 mm     HP E5336A probe adapter
                               HP E5340A 1/4 flexible adapter

                                  Probe cables                                                  Probe cables
                                  from logic                                                    from logic
                                  analyzer                                                      analyzer

                                                                                 HP E5346A

HP Analysis Probes for Specific
Processors and Buses
Please see Processor and Bus                                                                    Termination
                                                                                                adapter (HP
Support for HP Logic Analyzers                                                                  part number
(pub. no. 5966-4365E) for detailed                             Internal                         01650-63203)
information and ordering instruc-                              termination
tions for HP Analysis Probes. This
                                                               Optional shroud
document also contains additional                              (HP part number                  20-pin connector
and up to date information on the                              E5346-44701)                     (HP part number
other probing alternatives                                                                      1251-8106 2 x 10 pin
                                                               Mictor                           header with 0.1” x
described previously.                                          (HP part                         0.1” spacing)

                                             Figure 9. High density direct                      Figure 10. Normal density direct
                                             connection solution                                connection solution
 Accessories for the
 HP 1660ES Series Logic

 Oscilloscope Probes

 HP 1160 Family of Miniature
 Passive Probes
 The HP 1160 family of miniature
 probes was developed as a result of
 intensive market research on prob-
 ing. We developed a probe with a
 browser that won’t slip off the test
 point being probed and short to
 some adjacent point. The browser
 uses a crown point that digs into
 solder, and won’t slip. These probes   Figure 11. HP 1160 probes and accessories
 include a variety of ground leads
 and 50 mil SMD clips for attaching
 to different grounding points. Each
 HP 1660ES series logic analyzer
 ships with the HP 1160 family
 passive probes.

 Each HP 1160 family probe includes:
•1 probe assembly
•1 general-purpose retractable hook
•1 browser
•2 barrel insulators
•4 spring grounds
•1 alligator ground lead
•1 socketed ground lead
•1 dual lead adapter
•2 SMD grabbers
•1 spare browser pogo pin
•1 spare probe tip                      Figure 12. HP 1182A standard testmobile
•1 screwdriver
•1 users’ reference
•3-year warranty

                                        Figure 13. HP 1184A deluxe testmobile
HP 1660E/ES/EP Series
Ordering Information

HP 1660E/ES/EP and 1670E Series Benchtop Logic Analyzers
HP 1660E       136 Channel Color Logic Analyzer
HP 1661E       102 Channel Color Logic Analyzer
HP 1662E       68 Channel Color Logic Analyzer
HP 1663E       34 Channel Color Logic Analyzer
HP 1660ES      136 Channel Color Logic Analyzer with 2 channel, 500 MHz oscilloscope
HP 1661ES      102 Channel Color Logic Analyzer with 2 channel, 500 MHz oscilloscope
HP 1662ES      68 Channel Color Logic Analyzer with 2 channel, 500 MHz oscilloscope
HP 1663ES      34 Channel Color Logic Analyzer with 2 channel, 500 MHz oscilloscope
HP 1660EP      136 Channel Color Logic Analyzer with 32 channel, 100 Mvectors/sec pattern generator
HP 1661EP      102 Channel Color Logic Analyzer with 32 channel, 100 Mvectors/sec pattern generator
HP 1662EP      68 Channel Color Logic Analyzer with 32 channel, 100 Mvectors/sec pattern generator
HP 1663EP      34 Channel Color Logic Analyzer with 32 channel, 100 Mvectors/sec pattern generator
HP 1670E       136 Channel Color Logic Analyzer with 1M deep acquisition memory
HP 1671E       102 Channel Color Logic Analyzer with 1M deep acquisition memory
HP 1672E       68 Channel Color Logic Analyzer with 1M deep acquisition memory
HP 1664A       34 Channel Monochrome Logic Analyzer

HP 1660E/ES/EP Series and HP 1670E Series Product Options
Opt OB1        Additional User Manual
Opt OB3        Add Service Manual
Opt OBF        Add Programming Manual
Opt ICM        Rack Mount Kit
Opt IBP        MilStd 45662 Calibration
Opt ABJ        Japanese localization of user manual
Opt UK9        Front Panel Cover
Opt W30        3-year extended repair service
Opt W50        5-year extended repair service

HP 1660EP Series Product Options for the Pattern Generator
At least one clock pod and lead set must be ordered for the pattern generator of the HP 1660EP Series.
Also, order a data pod for every eight output channels used. There is a total of one clock pod and four
data pods on each HP 1660EP series pattern generator.
011            TTL Clock Pod and Lead Set
012            Tri-State TTL/3.3V Data Pod and Lead Set
013            Tri-State TTL/CMOS Data Pod and Lead Set
014            TTL Data Pod and Lead Set
021            ECL Clock Pod and Lead Set
022            ECL (terminated) Data Pod and Lead Set
023            ECL (unterminated) Data Pod and Lead Set
HP 1660E/ES/EP Series
Ordering Information

Probing Alternatives for HP Benchtop Logic Analyzers

HP 10467-68701          0.5 mm SMD clips (Qty 4)
HP E2613A               HP Wedge, 0.5mm, 3 signal (Qty1)
HP E2613B               HP Wedge, 0.5mm, 3 signal (Qty 2)
HP E2614A               HP Wedge, 0.5mm, 8 signal (Qty 1)
HP E2615A               HP Wedge, 0.65mm, 3 signal (Qty1)
HP E2615B               HP Wedge, 0.65mm, 3 signal (Qty 2)
HP E2616A               HP Wedge, 0.65mm, 8 signal (Qty. 1)
HP E5346A               High Density Termination Adapter
HP E5346-44701          Shroud for High Density T.A.
HP E5346-68701          Mictor High Density Connector (Qty 5)
HP 01650-63203          Normal Density Termination Adapter
HP 1251-8106            Normal Density 20-pin Connector

Optional Oscilloscope Probes for HP 1660ES Series Logic Analyzers

HP 1145A                2 Channel, 750 MHz Active Probes
HP 1142A                External Power Supply for HP 1145

Testmobiles for HP Benchtop Logic Analyzers
HP 1182A                Standard Testmobile
HP 1184A                Deluxe Testmobile

Accessories for HP Benchtop Logic Analyzers

HP E2427B               DIN (PC-Style) Keyboard
HP E2427A               HIL Keyboard (HP 1664A only)
HP 1540-1066            Soft Carrying Case
HP 5062-7379            Rack Mount Kit (same as option ICM)

HP 1660E Series Post Purchase Upgrades
The following two upgrades can be added to an HP 1660E Series logic analyzer at a later date if
the additional functionality is desired.

HP E2460ES         Upgrade to add two-channel, 500-MHz bandwidth, 2-GSa/s, 32k memory
                   oscilloscope to an HP 1660E Series model
HP E2495A          Upgrade to add thirty-two channel, 100 MVectors/sec, 256k memory
                   pattern generator to an HP 1660E Series model

Replacement Part Numbers for Logic Analyzer Probes
HP 5959-9333       Five gray probe leads
HP 5959-9334       Five short ground leads
HP 01650-61608     16-Channel probe lead set
HP 5090-4356       Surface-mount grabbers (package of 20)
HP 5959-0288       Throughhole grabbers (package of 20)

Replacement Model Numbers for Pattern Generator Probing
As a convenience, the individual model numbers for the HP 1660EP series pattern generator
clock/data pods and lead sets are listed here. Normally these are ordered as product options at the
time of purchase. They are listed here for any future needs that may arise.

HP 10460A          TTL Clock Pod for the HP 1660EP-Series
HP 10461A          8-channel TTL Data Pod for the HP 1660EP-Series
HP 10462A          8-channel 3-state TTL/CMOS Data Pod for the HP 1660EP-Series
HP 10463A          ECL Clock Pod for the HP 1660EP-Series
HP 10464A          8-channel ECL (terminated) Data Pod for the HP 1660EP-Series
HP 10465A          8-channel ECL (unterminated) Data Pod for the HP 1660EP-Series
                   (use HP 10347A lead set)
HP 10466A          8-channel 3-state TTL/3.3V Data Pod for the HP 1660EP-Series
HP 10474A          8-channel Probe Lead Set for the HP 1660EP-Series
HP 10347A          8-channel (50-ohm Coaxial) Probe Lead Set
Related HP Literature                                                                       For more information about
______________________________________________________________________________              Hewlett-Packard test and measurement
Title                                              Publication Description HP Pub. Number
______________________________________________________________________________              products, applications and services,
Logic Analysis and Emulation Solutions Version 3.0 CD-Rom                  5965-7502E
______________________________________________________________________________              visit our web site:
Processor and Bus Support for HP Logic Analyzers Configuration Guide       5966-4365E
______________________________________________________________________________              For more information on HP 1660 and
                                                                                            1670E-Series benchtop logic analyzers,
Warranty Information                                                                        visit our website:
All Hewlett-Packard products described in this document are warranted                       You can also contact one of the follow-
against defects in material and workmanship for a period of one year from                   ing centers and ask for a test and mea-
date of shipment. Three-year and five-year return-to-HP repair services are                 surement sales representative. If you
                                                                                            plan to purchase a new logic analyzer
also available. Refer to individual product manuals for detailed descrip-                   within the next 3 months and have
tions and terms of warranty. As an added benefit to HP 1664A customers,                     budget approved for the purchase, HP
this product comes standard with a three-year return to HP warranty.                        can arrange for you to test drive a unit.

PostscriptTM is a trademark of Adobe Systems Incorporated.                                  United States:
                                                                                            Hewlett-Packard Company
                                                                                            Test and Measurement Call Center
                                                                                            P.O. Box 4026
                                                                                            Englewood, CO 80155-4026
                                                                                            1 800 452 4844
                                                                                            Hewlett-Packard Canada Ltd.
                                                                                            5150 Spectrum Way
                                                                                            Mississauga, Ontario
                                                                                            L4W 5G1
                                                                                            (905) 206 4725
                                                                                            European Marketing Centre
                                                                                            P.O. Box 999
                                                                                            1180 AZ Amstelveen
                                                                                            The Netherlands
                                                                                            (31 20) 547 9900
                                                                                            Hewlett-Packard Japan Ltd.
                                                                                            Measurement Assistance Center
                                                                                            9-1, Takakura-Cho, Hachioji-Shi,
                                                                                            Tokyo 192-8510, Japan
                                                                                            (81) 426 56 7832
                                                                                            Latin America:
                                                                                            Latin American Region Headquarters
                                                                                            5200 Blue Lagoon Drive
                                                                                            9th Floor
                                                                                            Miami, Florida 33126
                                                                                            (305) 267 4245/4220
                                                                                            Australia/New Zealand:
                                                                                            Hewlett-Packard Australia Ltd.
                                                                                            31-41 Joseph Street
                                                                                            Blackburn, Victoria 3130
                                                                                            1 800 629 485 (Australia)
                                                                                            0 800 738 378 (New Zealand)
                                                                                            Asia Pacific:
                                                                                            Hewlett-Packard Asia Pacific Ltd
                                                                                            17-21/F Shell Tower, Times Square,
                                                                                            1 Matheson Street, Causeway Bay,
                                                                                            Hong Kong
                                                                                            (852) 2599 7777

                                                                                            Technical information in this document
                                                                                            is subject to change without notice.

                                                                                            5968-0327E                           11/98
                                                                                            Printed in the U.S.A.

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