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									           CMOS Detector Technology

   Markus Loose             Alan Hoffman           Vyshnavi Suntharalingam
   Rockwell Scientific   Raytheon Vision Systems      MIT Lincoln Laboratory

                    Scientific Detector Workshop, Sicily 2005

CMOS - 1
                   General CMOS Detector Concept

                          CCD Approach                     CMOS Approach

                               Photodiode                Photodiode       Amplifier

                         Charge generation &                Charge generation,
                          charge integration                charge integration &
                                                        charge-to-voltage conversion

                                                                        Multiplexing of
                                                                        pixel voltages:
    Array Readout                                                        Successively
                              Charge transfer                         connect amplifiers
                            from pixel to pixel                        to common bus

                                                           Various options possible:
                                                      - no further circuitry (analog out)
    Sensor Output                                      - add. amplifiers (analog output)
                        Output amplifier performs
                                                       - A/D conversion (digital output)
                       charge-to-voltage conversion

CMOS - 2
                          Common CMOS Features
 • CMOS sensors/multiplexers utilize the same process as modern
       – Many foundries available worldwide
       – Cost efficient
       – Latest processes available down to 0.13 µm

 • CMOS process enables integration of many additional features
       –   Various pixel circuits from 3 transistors up to many 100 transistors per pixel
       –   Random pixel access, windowing, subsampling and binning
       –   Bias generation (DACs)
       –   Analog signal processing (e.g. CDS, programmable gain, noise filter)
       –   A/D conversion
       –   Logic (timing control, digital signal processing, etc.)

 • Electronic shutter (snapshot, rolling shutter, non-destructive reads)
       – No mechanical shutter required
 • Low power consumption
 • Radiation tolerant (by process and by design)

CMOS - 3
                           Astronomy Application: Guiding
• Special windowing can be used to
  perform full-field science integration in
  parallel with fast window reads.
     Simultaneous guide operation and science
      data capture within the same detector.
• Two methods possible:
  – Interleaved reading of full-field and window
            • No scanning restrictions or crosstalk issues
            • Overhead reduces full-field frame rate
  – Parallel reading of full-field and window
            • Requires additional output channel
            • Parallel read may cause crosstalk or conflict
            • No overhead  maintains maximum full-field
              frame rate

              Full field row                       Window                    Full field row

              Full field row                  Full field row            Full field row

                     Window                                    Window

 CMOS - 4
                Stitching Enables Large Sensor Arrays
 • The small feature size of modern CMOS processes limits the maximum
   area that can be exposed in one step (so-called reticle) to about 22 mm.
 • However, larger chips can produced by breaking up the design into
   smaller sub-blocks that fit into the reticle.
    – Sub-blocks are exposed one after               Stitched CMOS Sensor
      another                                     horiscan1           horiscan2
    – Some blocks are used multiple
    – Ultimate limit is given by wafer size   1
                                                  array       array        array


                                              V   array       array        array

            V    V V     array
            1    2 3                          V   array       array        array

CMOS - 5
                                        Monolithic CMOS
 • A monolithic CMOS image sensor combines the photodiode and the
   readout circuitry in one piece of silicon
       – Photodiode and transistors share the area => less than 100% fill factor
       – Small pixels and large arrays can be produced at low cost => consumer
                                       applications (digital cameras, cell phones, etc.)
     3T Pixel


                                    Read Bus

                                                  photodiode transistors
     4T Pixel

                TG             SF
    Pinned PD
           p+        n+
                p-sub          Select
                                    Read Bus

CMOS - 6
                Complete Imaging Systems-on-a-Chip
• Monolithic CMOS technology has enabled highly integrated,
  complete imaging systems-on-a-chip:
    – Single chip cameras for video and digital still photography
    – Performance has significantly improved over last decade and is
      better or comparable to CCDs for many applications.
    – Especially suited for high frame rate sensors (> Gigapixel/s) or
      other special features (windowing, high dynamic range, etc.)
• However, monolithic CMOS is still limited with respect to
  quantum efficiency:                                                    2 Mpixel HDTV CMOS Sensor
    – Photodiode is relatively shallow
      => low red response                           Quantum Efficiency of a CMOS sensor
    – Metal and dielectric layers on
      top of the diode absorb or                                                           Si PIN
                                                                                        NIR AR coating
      reflect light
      => low overall QE
    – Backside illumination possible,                                                        Si PIN
                                                                                          UV AR coating
      but requires modification of
      CMOS process
 • Microlenses increase fill factor:                            3T pixel
                                                               w/ microlenses

 CMOS - 7
              Sensor Chip Assembly (SCA) Structure:
  Hybrid of Detector Array and ROIC Connected by Indium Bumps

                                    Detector Array

        Indium bump

                                   Detector Array

                      Silicon Readout Integrated Circuit (ROIC)

Mature interconnect technique:
    – Over 4,000,000 16,000,000 indium bumps per SCA demonstrated
    – 99.9% interconnect yield
• Also called a Focal Plane Array (FPA) or Hybrid Array
 CMOS - 8
                                                   CMOS SCA Revolution
           Number of Pixels per Array
                                                   MWIR arrays
                                        1E+08      Moore's law with 18 month doubling time





                                            1980    1985             1990            1995    2000   2005   2010
                                                               Year First used in Astronomy
    • Large CMOS hybrids revolutionized infrared astronomy
    • Growth in size has followed "Moore's Law" for over 20 years
           – 18 month doubling time

CMOS - 9
                        Three Most Common Input Circuits
                                for CMOS ROICs

              Circuit              Advantages             Disadvantages           Comments

SFD                                                  • gain fixed by detector
(Source Follower per       •   simple                  and ROIC input           Most common
Detector)                  •   low noise               capacitance              circuit in IR
also called "Self          •   low FET glow          • detector bias changes    astronomy
Integrator"                •   low power               during integration
                                                     • some nonlinearity

CTIA                       • very linear
(Capacitance               • gain determined by      • more complex circuit     Very high gains
Transimpedance               ROIC design (Cfb)       • FET glow                 demonstrated
Amplifier)                 • detector bias remains   • higher power

DI                         • large well capacity
(Direct Injection)         • gain determined by      • poor performance at      Standard
                             ROIC design (Cint)        low flux                 circuit for high
                           • detector bias remains                              flux
                           • low FET glow
                           • low power

  CMOS - 10
                Temperature and Wavelengths of
              High Performance Detector Materials

                                   Si PIN
                                            SWIR HgCdTe

                                                 MWIR HgCdTe

                                                                   Si:As IBC

            Approximate detector temperatures for dark currents << 1 e-/sec
CMOS - 11
     Detector Material Choices for CMOS Hybrid Arrays

   Detector      Spectral      Operating               General Comments
   Material     Range*, m     Temp***, K
                                                • All detectors can have:
 Si PIN          0.4 – 1.0        ~ 200            – 100% optical fill factor
                                                   – 100% internal QE (total QE
 InGaAs         0.9** – 1.7       ~ 130               depends on AR coat)
                                                          • Exception: Si:As is 40-70%
 HgCdTe:                                                    between 5 and 10 m
  1.7m         0.9** – 1.7      ~ 140
  2.5 m        0.9** – 2.5       ~ 90          • ROICs are interchangeable
  5.2 m        0.9** – 5.2       ~ 50            among detectors (except Si:As)
  10 m            5 – 10        ~ 25?
                                                • HgCdTe and InGaAs require
 InSb            0.4 – 5.2        ~ 35            special packaging due to CTE
                                                  mismatch between detector and
 Si:As IBC        5 – 28           ~7             ROIC

      * Long wave cutoff is defined as 50% QE point
      ** Spectral range can be extended into visible range by removing substrate
      *** Approximate detector temperatures for dark currents << 1 e-/sec

CMOS - 12
                                  Process Comparison
                        CCD                                          CMOS
                > 35 years of evolution              Economics of scale accelerate progress
                  “Trailing edge” fabs               Lower fabrication cost, Foundry access
    High resistivity (deep depletion) substrates      Epi doping optimized for digital CMOS
   Controlled temperature ramps & stress control               Scalable to 300mm
                    Buried channel                        Complex implant engineering
               Multiple oxidation cycles                 Rapid Thermal Processing (RTP)

            Single gate dielectric thickness            Multiple gate dielectric thicknesses

                                                         Complementarily doped polysilicon
            Doped polysilicon (single type)
                                                     Silicided polysilicon and FET source/drain
              Highly nonplanar surfaces                         Fine-line patterning
              Conservative design rules                Multiple metal layers (dense routing)
                                                     Highly suitable for long-term space-based
     Vulnerable to space-radiation-induced traps

                                               2m                      2m                    2m
                              Four-Poly OTCCD        180-nm SRAM cell          Stacked via to poly
CMOS - 13
              Limitations of Standard Bulk CMOS APS
                                                                        Pixel Layout
 • Fill factor tradeoff
       – Photodetector and pixel transistors share
         same area
       – PD from Drain-Substrate or Well-Substrate
 • Low photoresponsivity
       – Shallow, heavily doped junctions
       – Limited depletion depth
       – Absorption and reflection in poly, metal, and
         oxide layers
       – Surface recombination at Si/SiO2 interface
       – QE*FF > 60% is good, many < 20%                                       VDD

 • High leakage                                                                             OUT
       – LOCOS/STI, salicide
                                                                        n+                            p+
       – Transistor short channel effects                                             Field Oxide
                                                           p-well            n-Well

 • Substrate bounce and transient coupling               p-epi
                                                         p+ Substrate

CMOS - 14
                           Advantages of Vertical Integration
Conventional Monolithic APS                               3-D Pixel

                                    3T                                    PD

                         A/D, CDS, …

    • Pixel electronics and detectors            • 100% fill factor detector
      share area
                                                 • Fabrication optimized by
    • Fill factor loss                             layer function
    • Co-optimized fabrication
                                                 • Local image processing
    • Control and support electronics
                                                    – Power and noise
      placed outside of imaging area
                                                 • Scalable to large-area focal
CMOS - 15
                    Approaches to 3D Integration
                            (To Scale)



                                                                     10 m

            10 m
                           Photo Courtesy of RTI   10 m

 Bump Bond used to           Two-layer stack with   Two-layer stack using
flip-chip interconnect      insulated vias through Lincoln’s SOI-based vias
   two circuit layers          thinned bulk Si

CMOS - 16
             Comparison CMOS vs. CCD for Astronomy

         Property                  CCD                    Hybrid CMOS
Resolution             > 4k x 4k               2k x 2k in use, 4k x 4k demonstrated
Pixel pitch            10 – 20 µm              18 – 40 µm, < 10 µm demonstrated
Typ. wavelength        400 – 1000 nm           400 – 1000 nm with Si PIN
coverage                                       400 – 5000 nm with InSb or HgCdTe
Noise                  Few electrons           Few electrons with multiple sampling
Shutter                Mechanical              Electronic, rolling shutter
Power Consumption      High                    Typ. 10x lower than CCD
Radiation              Sensitive               Much less susceptible to radiation
Control Electronics    High voltage clocks, at Low voltage only,
                       least 2 chips needed    can be integrated into single chip
Special Modes          Orthogonal Transfer,    Windowing, Guide Mode,
                       Binning,                Random Access, Reference Pixels,
                       Adaptive Optics         Large dynamic range (up the ramp)

Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a
number of significant advantages, specifically for large mosaic focal plane arrays.
 CMOS - 17

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