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					Ultra-Deep submicron technology

             Etienne Sicard
                  Insa

         etienne.sicard@insa-tlse.fr
      http://intrage.insa-tlse.fr/~etienne

              E. Sicard - ultra deep submicron
Summary

• Ultra-deep submicron technology
• Specific features
• Embedded Memory
• Magnetic RAM
• SOI
• conclusion



                 E. Sicard - ultra deep submicron
1. Ultra-deep submicron technology
  2.0    Micron Sub-micron              Deep-sub                Ultra  Nano
              80286                      micron               Deep-sub
                      80386
  1.0                          486                             micron
                                           pentium
  0.3                                               pentium II
  0.2                                                    Pentium IV
                                                           Itanium
  0.1

  0.05
  0.03

         83    86     89      92      95       98      01       04   07
                               Year
                           E. Sicard - ultra deep submicron
1. Ultra-deep submicron technology




 • Multiple technological options to optimize performance
 • Faster & bigger chips
 • Agreements to handle tremendous costs
   (ST,Philips,Motorola,TSMC)
                    E. Sicard - ultra deep submicron
 2. Specific features

                                                            Multiple metal layers

          Stacked vias
                                                            Low K dielectric to
 Copper to speed up                                         reduce couplings
  signal transport


High K dielectric to
 reduce leakage                                                        Improved
                                                                    tretch isolation

                                        Multiple MOS
                                          options
                         E. Sicard - ultra deep submicron
2. Specific features

                                                • High Speed: normal MOS
                                                • Very high speed: critical
                                                     path
                                                • Low leakage: for low power
3-6 MOS                                         • High voltage: for I/Os
 options                                        • Double-gate: for embedded
                                                     EEPROM
                                                • RF : optimized for GHz
                                                     amplifiers


                  E. Sicard - ultra deep submicron
    2. Specific features
                                   Ultra High Speed
   Low Leakage                                                                EEProm
                                                              High Voltage




                                                  RF                         MRam
                     High Speed
Application-oriented MOS device
Same basic mechanism
New physical properties in EEPROM and MRam
                                  E. Sicard - ultra deep submicron
2. Specific features

                                                                     2.5V
        1.2V
                                   1.2V
                                                                      1.2V

       1.2V                    1.2V
                                                                   2.5V
High Speed           Low leakage                          High Voltage


              1.8V                                            2.5V
              Example in 0.12µm technology
                       E. Sicard - ultra deep submicron
2. Specific features
               Option layer




Simple access to low leakage,                          Option layer
high voltage and isolated Pwell                         properties
                    E. Sicard - ultra deep submicron
2. Specific features
                    Low leakage




                      High speed




                      High voltage

Simulation of the 3 MOS options

                    E. Sicard - ultra deep submicron
2. Specific features
                                                 Small Ion
                                                 reduction



 Ioff ~10nA                             Ioff ~100pA

        High speed                                      Low leakage


Low leakage MOS has higher Vt, slight Ion reduction
Low leakage MOS has 1/100 Ioff of high speed MOS
                     E. Sicard - ultra deep submicron
2. Specific features

0.1µm process (TSMC+ST+IBM+…)

       Type of MOS    Effective            Oxide       Ioff    Ion
                      channel length       thickness
                      (µm)
       Ultra-high     0.07                 16 Å        Very    Very
       speed                                           high    high
       High speed     0.09                 16 Å        High    High
       Low leakage    0.09                 24 Å        Low     Medium
       High voltage   0.2                  50 Å        Low     Low


 Each MOS is optimized for a target customer application
 Towards a world-wide standard process which will ease design
                            E. Sicard - ultra deep submicron
3. Embedded Memory

• 80% of a system-on-chip
• Bottleneck for bandwidth

                      Cmos Embedded memories



                    Volatile                          Non volatile



    eDRAM                SRAM                 ROM          EEPROM    FRAM

                             E. Sicard - ultra deep submicron
3. Embedded Memory


                               CS
             CB




 Parasitic capacitance: 2fF         Specific capacitance: 3-30fF
                              E. Sicard - ultra deep submicron
3. Embedded Memory

Double-Gate MOS


                  2nd Poly

              Floating Poly




Used in EPROM, EEPROM and Flash memories
                  E. Sicard - ultra deep submicron
  3. Embedded Memory

      Double-Gate MOS
                                                           Ids
Ids

                                                                 Single gate
       Single gate
                                                                    Double gate

             Vds                                                          Vds

                                                           Gate discharged
Gate charged




                        E. Sicard - ultra deep submicron
3. Embedded Memory
Double-Gate MOS: write/erase by tunneling
             12V                                            0V
                       “Hot”            “Cold”
                       electron         electron
                       Tunneling        Tunneling

  0                                     12V
                          Vdd



          Accelerate

           write                                           erase
 Dense but slow
                        E. Sicard - ultra deep submicron
 4. Magnetic RAM

Dense, fast, non-volatile: universal memory
  Silicium, Cobalt et Nikel




 2 stage magnetic states



A high magnetic field changes the state of the material          equal to
                                                                 I=5mA
                              E. Sicard - ultra deep submicron
      4. Magnetic RAM                   Column

                                                     i/2                   i/2



                     Line
                                i/2                         i/2

                            Write                          Erase
               i/4
i/4                    Principles:
                       Write: i/2 on the line, i/2 on the column gives a current
                       high enough to change the state
                       Read: i/4 on the line, i/4 on the column and monitor the
                       attenuation of current due to magnetic state

Read                    E. Sicard - ultra deep submicron
  5. Silicon-On-insulator
The next major evolution?
    CMOS compatible

    Less distance between nMOS
    and pMOS

    Less capacitance

    Less leakage                          >50%
                                          faster
                                          circuits

                                                                       Kink effect
     Fully or partially depleted?
                                    E. Sicard - ultra deep submicron
6. Conclusion

 • The ultra-deep submicron technologies introduce new features

 • Low leakage MOS targeted for low power

 • High voltage MOS introduced for I/O interfacing

 • Double-poly MOS for EPROM/Flash memories

 • Embedded memory are key components for System-on-chip

 • Magnetic RAM to become the “universal memory”

 • SOI has many promising features, some design issues pending


                          E. Sicard - ultra deep submicron

				
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posted:8/8/2011
language:Romanian
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