# CS1104_ Computer Organisation_3_

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```					  CS1104: Computer Organisation

http://www.comp.nus.edu.sg/~cs1104

Lecture 7: Combinational Circuits
MSI Components
Lecture 7
Combinational Circuits: MSI Components
   Useful MSI circuits
   Decoders
   Implementing Functions with Decoders
   Decoders with Enable
   Larger Decoders
   Standard MSI Decoders
   Implementing Functions with Decoders (2)
   Reducing Decoders

CS1104-7              Lecture 7: Combinational Circuits:   2
MSI Components
Lecture 7
Combinational Circuits: MSI Components
 Encoder
 Demultiplexer
 Multiplexer
 Multiplexer IC Package
 Larger Multiplexers
 Standard MSI Multiplexer
 Implementing Functions with Multiplexers
 Implementing Functions with Smaller Multiplexers

CS1104-7             Lecture 7: Combinational Circuits:   3
MSI Components
Useful MSI circuits
 Four common and useful MSI circuits are:
     Decoder
     Demultiplexer
     Encoder
     Multiplexer
 Block-level outlines of MSI circuits:
decoder                           encoder
code                 entity    entity                 code

mux       data        data        demux    output
input

select                          select
CS1104-7                       Useful MSI circuits                      4
Decoders (1/5)
 Codes are frequently used to represent entities, e.g.
your name is a code to denote yourself (an entity!).
 These codes can be identified (or decoded) using a
decoder. Given a code, identify the entity.
 Convert binary information from n input lines to (max.
n
of) 2 output lines.
 Known as n-to-m-line decoder, or simply n:m or nm
decoder (m  2n).
 May be used to generate 2n (or fewer) minterms of n
input variables.

CS1104-7                     Decoders                       5
Decoders (2/5)
 Example: if codes 00, 01, 10, 11 are used to identify
four light bulbs, we may use a 2-bit decoder:
2x4
F0           Bulb 0
2-bit   X Dec F            Bulb 1
1
code    Y
F2         Bulb 2
F3         Bulb 3

 This is a 24 decoder which selects an output line
based on the 2-bit code supplied.
   Truth table:        X Y F0 F1 F2                F3
0   0    1     0     0      0
0   1    0     1     0      0
1   0    0     0     1      0
1   1    0     0     0      1

CS1104-7                     Decoders                      6
Decoders (3/5)
 From truth table,            X
0
Y F0
0 1
F1 F2 F3
0 0 0
circuit for 24             0   1 0    1 0 0
decoder is:                 1   0 0    0 1 0
1   1 0    0 0 1
 Note: Each output is
a 2-variable minterm                              F0 = X'.Y'
(X'.Y', X'.Y, X.Y' or
X.Y)                                              F1 = X'.Y

F2 = X.Y'

F3 = X.Y

X   Y
CS1104-7                     Decoders                               7
Decoders (4/5)
 Design a 38 decoder.
F0 = x'.y'.z'
x     y   z F0   F1   F2   F3   F4   F5   F6   F7
0     0   0 1    0    0    0    0    0    0    0                  F1 = x'.y'.z
0     0   1 0    1    0    0    0    0    0    0
0     1   0 0    0    1    0    0    0    0    0                  F2 = x'.y.z'
0     1   1 0    0    0    1    0    0    0    0
1     0   0 0    0    0    0    1    0    0    0                  F3 = x'.y.z
1     0   1 0    0    0    0    0    1    0    0
1     1   0 0    0    0    0    0    0    1    0                  F4 = x.y'.z'
1     1   1 0    0    0    0    0    0    0    1
F5 = x.y'.z

 Application? Binary-                                                F6 = x.y.z'
to-octal conversion.                                              F7 = x.y.z

x   y   z
CS1104-7                                        Decoders                         8
Decoders (5/5)
 In general, for an n-bit code, a decoder could select
up to 2n lines:

n-bit          n to 2n           up to 2n
code      :   decoder      :   output lines

CS1104-7                     Decoders                      9
Decoders: Implementing Functions (1/5)
 A Boolean function, in sum-of-minterms form a
decoder to generate the minterms, and an OR gate to
form the sum.
 Any combinational circuit with n inputs and m outputs
can be implemented with an n:2n decoder with m OR
gates.
 Good when circuit has many outputs, and each
function is expressed with few minterms.

CS1104-7               Decoders: Implementing              10
Functions
Decoders: Implementing Functions (2/5)
 Example: Full adder                         x   y   z   C S
0   0   0   0 0
S(x, y, z) = S m(1,2,4,7)                 0   0   1   0 1
0   1   0   0 1
C(x, y, z) = S m(3,5,6,7)                 0   1   1   1 0
1   0   0   0 1
1   0   1   1 0
1   1   0   1 0
1   1   1   1 1
3x8   0
Dec   1                             S
2
x    S2         3
y    S1         4
5                             C
z    S0         6
7

CS1104-7                 Decoders: Implementing                 11
Functions
Decoders: Implementing Functions (3/5)
3x8   0
x   y   z   C S
1
Dec                                            0   0   0   0 0
1   0                            S   0   0   0   1   0 1
2   0                                    0   1   0   0 1
0 x   S2         3   0                                    0   1   1   1 0
0 y   S1         4   0                                    1   0   0   0 1
5   0                            C   0   1   0   1   1 0
0 z   S0         6   0                                    1   1   0   1 0
7   0                                    1   1   1   1 1

CS1104-7                      Decoders: Implementing                         12
Functions
Decoders: Implementing Functions (4/5)
3x8   0
x   y   z   C S
0
Dec                                            0   0   0   0 0
1   1                            S   1   0   0   1   0 1
2   0                                    0   1   0   0 1
0 x   S2         3   0                                    0   1   1   1 0
0 y   S1         4   0                                    1   0   0   0 1
5   0                            C   0   1   0   1   1 0
1 z   S0         6   0                                    1   1   0   1 0
7   0                                    1   1   1   1 1

CS1104-7                      Decoders: Implementing                         13
Functions
Decoders: Implementing Functions (5/5)
3x8   0
x   y   z   C S
0
Dec                                            0   0   0   0 0
1   0                            S   1   0   0   1   0 1
2   0                                    0   1   0   0 1
1 x   S2         3   0                                    0   1   1   1 0
1 y   S1         4   0                                    1   0   0   0 1
5   0                            C   1   1   0   1   1 0
1 z   S0         6   0                                    1   1   0   1 0
7   1                                    1   1   1   1 1

BRAVO!!!

CS1104-7                      Decoders: Implementing                         14
Functions
Decoders with Enable (1/2)
 Decoders often come with an enable signal, so that
the device is only activated when the enable, E=1.
 Truth table:
F0 = EX'Y'
E X   Y   F0 F1 F2 F3
1 0   0   1 0 0 0
1 0   1   0 1 0 0                               F1 = EX'Y
1 1   0   0 0 1 0
1 1   1   0 0 0 1
0 X   X   0 0 0 0                               F2 = EXY'

F3 = EXY
 Circuit:

X       Y   E

CS1104-7                    Decoders with Enable                        15
Decoders with Enable (2/2)
 In the previous slide, the decoder has a one-enable
signal, that is, the decoder is enabled with E=1.
 In most MSI decoders, enable signal is zero-enable,
usually denoted by E‟ (or E). The decoder is enabled
when the signal is zero.
E X   Y    F0 F1 F2 F3           E'   X   Y   F0 F1 F2 F3
1 0   0    1 0 0 0               0    0   0   1 0 0 0
1 0   1    0 1 0 0               0    0   1   0 1 0 0
1 1   0    0 0 1 0               0    1   0   0 0 1 0
1 1   1    0 0 0 1               0    1   1   0 0 0 1
0 X   X    0 0 0 0               1    X   X   0 0 0 0

Decoder with 1-enable            Decoder with 0-enable

CS1104-7                      Decoders with Enable                     16
Larger Decoders (1/6)
 Larger decoders can                              3x8
Dec       0       F0 = w'x'y'
w      S2             1       F1 = w'x'y
be constructed from                x      S1             :       :
smaller ones.                      y      S0             :
7
:
F7 = wxy

 For example, a 3-to-8
decoder can be
constructed from two          w
2x4
Dec      0       F0 = w'x'y'
S1
2-to-4 decoders (with         x
y                S0
1
2
F1 = w'x'y
F2 = w'xy'
one-enable), as                                      E       3       F3 = w'xy

follows:
2x4
Dec      0       F4 = wx'y'
S1            1       F5 = wx'y
S0            2       F6 = wxy'
E       3       F7 = wxy

CS1104-7                    Larger Decoders                                            17
Larger Decoders (2/6)
3x8
Dec   0   F0 = w'x'y'
w   S2         1   F1 = w'x'y
2x4         1                  x   S1         :   :
0 w                   0        F0 = w'x'y'
Dec         0                                 :   :
0 x      S1           1        F1 = w'x'y    y   S0
S0
0                                 7   F7 = wxy
0 y                   2
0
F2 = w'xy'
E      3        F3 = w'xy

1 = enabled
2x4         0
Dec     0        F4 = wx'y'
S1           1
0    F5 = wx'y
S0           2
0    F6 = wxy'
0
E      3        F7 = wxy

0 = disabled

CS1104-7                         Larger Decoders                          18
Larger Decoders (3/6)
3x8
Dec   0   F0 = w'x'y'
w   S2         1   F1 = w'x'y
2x4         0                  x   S1         :   :
0 w                   0        F0 = w'x'y'
Dec         1                                 :   :
0 x      S1           1        F1 = w'x'y    y   S0
S0
0                                 7   F7 = wxy
1 y                   2
0
F2 = w'xy'
E      3        F3 = w'xy

1 = enabled
2x4         0
Dec     0        F4 = wx'y'
S1           1
0    F5 = wx'y
S0           2
0    F6 = wxy'
0
E      3        F7 = wxy

0 = disabled

CS1104-7                         Larger Decoders                          19
Larger Decoders (4/6)
3x8
Dec   0   F0 = w'x'y'
w   S2         1   F1 = w'x'y
2x4         0                  x   S1         :   :
1 w                   0        F0 = w'x'y'
Dec         0                                 :   :
1 x      S1           1        F1 = w'x'y    y   S0
S0
0                                 7   F7 = wxy
0 y                   2
0
F2 = w'xy'
E      3        F3 = w'xy

0 = disabled
2x4         0
Dec     0        F4 = wx'y'
S1           1
0    F5 = wx'y
S0           2
1    F6 = wxy'
0
E      3        F7 = wxy
BRAVO!!!
1 = enabled

CS1104-7                         Larger Decoders                          20
Larger Decoders (5/6)
 Construct a 4x16                      w       S3
4x16
Dec     0   F0
decoder from two 3x8                 x       S2
1   F1
decoders with 1-enable.              y       S1
:   :
:   :
z       S0          15   F15

3x8
w                            Dec    0        F0
x                       S2
1        F1
y                       S1          :        :
z                       S0          7        F7
E

3x8
Dec    0        F8
S2
1        F9
S1          :        :
S0          7        F15
E

CS1104-7                 Larger Decoders                                  21
Larger Decoders (6/6)
 Note: The input, w and its complement, w', is used to
select either one of the two smaller decoders.
 Decoders may also have zero-enable and/or negated
outputs. (Normal outputs = active high; negated
outputs = active low.)
 Exercise: What modifications must be made to
provide an ENABLE input for the 3x8 decoder (2
slides ago) and the 4x16 decoder (previous slide)
created?
 Exercise: How to construct a 4x16 decoder using five
2x4 decoders with enable?

CS1104-7                 Larger Decoders                    22
Standard MSI Decoders (1/2)
 74138 (3-to-8 decoder)

74138 decoder module.
(a) Logic circuit.
(b) Package pin configuration.

CS1104-7             Standard MSI Decoders                       23
Standard MSI Decoders (2/2)

74138 decoder module.
(c) Function table.

Negated outputs

74138 decoder module.
(d) Generic symbol.
(e) IEEE standard logic symbol.
Source:The Data Book Volume 2,
Texas Instruments Inc.,1985

CS1104-7                   Standard MSI Decoders                      24
Decoders: Implementing Functions
Revisit (1/2)
 Example: Implement the following logic function
using decoders and logic gates
f(Q,X,P) =  m(0,1,4,6,7) =  M(2,3,5)
 We may implement the function in several ways:
 Use a decoder (with active-high outputs) with an OR gate:
f(Q,X,P) = m0 + m1 + m4 + m6 + m7
 Use a decoder (with active-low outputs) with a NAND gate:
f(Q,X,P) = ( m0' . m1' . m4' . m6' . m7' )'
 Use a decoder (with active-high outputs) with a NOR gate:
f(Q,X,P) = ( m2 + m3 + m5 )'       [ = M2.M3.M5]
 Use a decoder (with active-low outputs) with an AND gate:
f(Q,X,P) = m2' . m3' . m5'
CS1104-7                    Decoders: Implementing                   25
Functions (2)
Decoders: Implementing Functions
Revisit (2/2)
0         f(Q,X,P)                            0
3x8   1         =  m(0,1,4,6,7)              3x8   1
Dec   2                                       Dec   2
Q     A         3           f(Q,X,P)       Q        A         3        f(Q,X,P)
B         4                                   B         4
X                                          X
5                                             5
P     C         6                          P        C         6
7                                             7

(a) Active-high decoder with OR gate.        (b) Active-low decoder with NAND gate.

0                                             0
3x8   1                                       3x8   1
Dec   2            f(Q,X,P)                   Dec   2        f(Q,X,P)
Q     A         3                          Q        A         3
B         4                                   B         4
X                                          X
5                                             5
P     C         6                          P        C         6
7                                             7

(c) Active-high decoder with NOR gate.      (d) Active-low decoder with AND gate.

CS1104-7                         Decoders: Implementing                                 26
Functions (2)
Reducing Decoders (1/13)
 Example:
F(a,b,c) =  m(4,6,7)
 Using a 38 decoder (assuming 1-enable and
active-high outputs).
3x8   0
Dec   1
2
a       S2         3
b       S1         4
5        F
c       S0         6
7
EN

1

CS1104-7                     Reducing Decoders       27
Reducing Decoders (2/13)
 We have seen that a decoder may be constructed from
smaller decoders.
   Below are just some ways of constructing a 38 decoder.
(Explore other ways youself!)
 Using two 24 decoders with an inverter.
2x4
a                Dec       0
b           S1             1
c           S0             2
E        3
a'

2x4
Dec       0
S1             1
S0             2
E        3
a
CS1104-7                    Reducing Decoders            28
Reducing Decoders (3/13)
 Using two 24 decoders and a 12 decoder.

2x4
Dec       0
b         S1             1
c         S0             2
E        3
1x2
Dec 0                       a'
a    S
1
E                     2x4
Dec       0
1               S1             1
S0             2
E        3
a

Verify this circuit yourself!

CS1104-7                           Reducing Decoders           29
Reducing Decoders (4/13)
 Using four 12 decoders                              1x2
Dec 0
and a 24 decoder.                          c   S
1
E

1x2
Dec 0
c   S
2x4                               1
Dec 0                          E
a   S1       1
b   S0       2                         1x2
E  3                         Dec 0
c   S
1
1                              E

1x2
Dec 0
c   S
1
Verify this circuit yourself!                      E

CS1104-7                           Reducing Decoders                 30
Reducing Decoders (5/13)
 Using smaller decoders, sometimes we may be able
to save some decoders.
 Example: F(a,b,c) =  m(4,6,7)
2x4
Dec       0    Question: Do we really
b   S1             1
c   S0             2    need this decoder for F?
E        3
1x2
Dec 0                 a'
a   S
1
E               2x4
Dec       0
1          S1             1             F
S0             2
E        3
a

CS1104-7                     Reducing Decoders                          31
Reducing Decoders (6/13)
 So we can save a decoder.
1x2
2x4
Dec 0                          0
a    S                          Dec
1       b       S1         1   F
E          c       S0         2
E    3
1

 Similarly, we can save 2 small decoders below.
1x2
2x4                  Dec 0
c    S
Dec 0                    1
a   S1       1                 E
b   S0       2                            F
E  3
1x2
Dec 0
1             c    S
1
E

CS1104-7                     Reducing Decoders            32
Reducing Decoders (7/13)
 Second example: F(a,b,c) =  m(0,1,2,3,6)

2x4
Dec   0
b   S1         1
c   S0         2        Question: Can we
this?
1x2
2x4
Dec 0                  0
a   S                  Dec
1   b   S1         1
E                     2
F
c   S0
E     3
1

CS1104-7                     Reducing Decoders                  33
Reducing Decoders (8/13)
 Second example: F(a,b,c) =  m(0,1,2,3,6)
 Yes, we may remove the top 24 decoder, and
connect the appropriate output from the 12 decoder
directly to the OR gate.

1x2
2x4
Dec 0                       0
a    S                       Dec
1      b     S1         1
E         c     S0         2   F
E   3
1

Verify that this circuit is correct!

CS1104-7                           Reducing Decoders          34
Reducing Decoders (9/13)
 Third example: F(a,b,c) =  m(0,3,4,7)
We have the same pattern
2x4                 of outputs from the 2
Dec   0
b   S1         1             decoders (i.e. we take the
c   S0         2             first and fourth outputs
E     3             from each decoder). Can
1x2
2x4
Dec 0                  0                     F
a     S                  Dec
1   b   S1         1
E      c   S0         2
E     3
1

CS1104-7                      Reducing Decoders                                35
Reducing Decoders (10/13)
 Third example: F(a,b,c) =  m(0,3,4,7)
 If we have the same pattern of outputs from 2 or
more decoders at the second level, we may keep one
decoder, and use an OR gate on the corresponding
outputs from the first-level decoder.

1x2
2x4
Dec 0                               0   F
a    S                               Dec
1              b     S1         1
E                 c     S0         2
E     3
1

Verify that this circuit is correct!

CS1104-7                           Reducing Decoders            36
Reducing Decoders (11/13)
 Third example: F(a,b,c) =  m(0,3,4,7)
 Can we still simplify the circuit?
This may be eliminated. (why?)

1x2
2x4
Dec 0                                 0                      F
a     S                                 Dec
1               b      S1         1
E                  c      S0         2
E     3
1
Because this is (a' + a) = 1

Result:                   2x4
Dec   0                            F
b   S1         1
c   S0         2
E    3

1
CS1104-7                         Reducing Decoders                                     37
Reducing Decoders (12/13)
 Summary:
 If no outputs are needed from a 2nd-level decoder, just
remove the decoder.
 If all outputs are needed from a 2nd-level decoder, remove
the decoder, and connect the corresponding output from the
1st-level decoder to the OR gate.
 If the set of outputs is the same for 2 or more decoders at the
2nd level, keep one of the decoders and remove the rest.
Add an OR gate to take in the appropriate outputs from the
1st-level decoder.
 The above procedure may not guarantee a circuit that
has the least number of decoders. However, it is easy
to follow. (To obtain the optimal circuit in general, we need to play
around with the inputs to the decoders, which may be hard.)

CS1104-7                       Reducing Decoders                            38
Reducing Decoders (13/13)
 Apply what you learned to verify the circuit below for
this function: F(a,b,c,d) =  m(0,1,2,3,4,5,12,13)

2x4
Dec   0
a    S1         1
2x4
b    S0         2                                  0   F
Dec
E     3               c       S1         1
d       S0         2
1                                 E     3

CS1104-7                          Reducing Decoders                      39
Encoder (1/5)
 Encoding is the converse of decoding.
 Given a set of input lines, where one has been
selected, provide a code corresponding to that line.
 Contains 2n (or fewer) input lines and n output lines.
 Implemented with OR gates.
 An example:
F0               D0
Select via           F1      4-to-2
switches                                   2-bits
F2     Encoder   D1   code
F3

CS1104-7                     Encoder                           40
Encoder (2/5)
 Truth table:
F0 F1   F 2 F3      D1   D0
1 0     0 0         0    0
0 1     0 0         0    1
0 0     1 0         1    0
0 0     0 1         1    1
0 0     0 0         X    X
0 0     1 1         X    X
0 1     0 1         X    X
0 1     1 0         X    X
0 1     1 1         X    X
1 0     0 1         X    X
1 0     1 0         X    X
1 0     1 1         X    X
1 1     0 0         X    X
1 1     0 1         X    X
1 1     1 0         X    X
1 1     1 1         X    X

CS1104-7                    Encoder             41
Encoder (3/5)
 With the help of K-map (and don‟t care conditions),
can obtain:
D0 = F1 + F3
D1 = F2 + F3
which correspond to circuit:
F0
F1
D0
Simple 4-to-2 encoder
F2
F3                     D1

CS1104-7                        Encoder                           42
Encoder (4/5)
 Example: Octal-to-binary encoder.
 At any one time, only one input line has a value of 1.
 Otherwise, need priority encoder (not covered).

Inputs                   Outputs
D0   D1   D2   D3   D4   D5   D6   D7   x   y   z
1    0     0   0    0    0    0    0    0   0   0
0    1     0   0    0    0    0    0    0   0   1
0    0     1   0    0    0    0    0    0   1   0
0    0     0   1    0    0    0    0    0   1   1
0    0     0   0    1    0    0    0    1   0   0
0    0    0    0    0    1    0    0    1   0   1
0    0     0   0    0    0    1    0    1   1   0
0    0     0   0    0    0    0    1    1   1   1

CS1104-7                                Encoder                    43
Encoder (5/5)
 Example: Octal-to-binary encoder.

D0
D1                               x = D 4 + D5 + D6 + D7
D2
D3                               y = D 2 + D3 + D6 + D7
D4
D5
D6
D7                               z = D 1 + D3 + D5 + D7

An 8-to-3 encoder

Exercise: Can you design a 2n-to-n encoder without the K-map?

CS1104-7                       Encoder                               44
Demultiplexer (1/2)
 Given an input line and a set of selection lines, the
demultiplexer will direct data from input to a selected
output line.
 An example of a 1-to-4 demultiplexer:
Outputs

Y0 = D.S1'.S0'   S1 So   Y0   Y1   Y2   Y3
0 0     D    0    0    0
Y1 = D.S1'.S0
Data D     demux
0 1     0    D    0    0
Y2 = D.S1.S0'    1 0     0    0    D    0
1 1     0    0    0    D
Y3 = D.S1.S0

S1 S0
select

CS1104-7                   Demultiplexer                               45
Demultiplexer (2/2)
 The demultiplexer is actually identical to a decoder
with enable, as illustrated below:

Y0 = D.S1'.S0'
2x4
S1      Decoder           Y1 = D.S1'.S0
S0                        Y2 = D.S1.S0'
E              Y3 = D.S1.S0

D

Exercise: Provide the truth table for above demultiplexer.

CS1104-7                         Demultiplexer                      46
Multiplexer (1/5)
 A multiplexer is a device which has
(i) a number of input lines
(ii) a number of selection lines
(iii) one output line
 It steers one of 2n inputs to a single output line, using
n selection lines. Also known as a data selector.

2n:1
inputs       Multiplexer    output
:

...
select

CS1104-7                      Multiplexer                      47
Multiplexer (2/5)
 Truth table for a 4-to-1 multiplexer:
I0   I1    I2   I3   S1   S0      Y                 S1   S0    Y
d0   d1    d2   d3   0    0       d0                0    0     I0
d0   d1    d2   d3   0    1       d1                0    1     I1
d0   d1    d2   d3   1    0       d2                1    0     I2
d0   d1    d2   d3   1    1       d3                1    1     I3

Inputs                                             Inputs
I0        0                                         I0
I1           4:1
1                                         I1
MUX
I2        2       Y            Output               I2             mux      Y
I3        3                                         I3
S1 S0
S1 S0
select                                              select

CS1104-7                                        Multiplexer                                 48
Multiplexer (3/5)
 Output of multiplexer is
“sum of the (product of data lines and selection lines)”
 Example: the output of a 4-to-1 multiplexer is:
Y = I0.(S1'.S0') + I1.(S1'.S0) + I2.(S1.S0') + I3.(S1.S0)

 A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is
n                         n
made from an n: 2 decoder by adding to it 2 input
lines, one to each AND gate.

CS1104-7                          Multiplexer                          49
Multiplexer (4/5)
I0                                        I0

I1                                        I1
Y                           Y
I2                                        I2

I3                                        I3

0 1 2 3
2-to-4
Decoder

S1 S0                                    S1   S0

Four-to-one multiplexer design.

CS1104-7                          Multiplexer                  50
Multiplexer (5/5)
 An application:

Helps share a single communication line among a number
of devices.
At any time, only one source and one destination can use
the communication line.

CS1104-7                      Multiplexer                        51
Multiplexer IC Package
 Some IC packages have a few multiplexers in each
package. The selection and enable inputs are
common to all multiplexers within the package.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
B1                                       E’   S Output Y
1    X  all 0‟s
B2                                       0    0 select A
B3                                       0    1 select B
S
(select)
(enable)
CS1104-7                   Multiplexer IC PackageMultiplexer                     52
Larger Multiplexers (1/6)
 Larger multiplexers can be constructed from smaller
ones.
 An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):
I0                                     S2   S1   S0   Y
I1     4:1                             0    0    0    I0
I2    MUX
I3                                     0    0    1    I1
0    1    0    I2
2:1                0    1    1    I3
S1 S0         MUX             Y
I4
1    0    0    I4
I5                                     1    0    1    I5
4:1
I6                                     1    1    0    I6
MUX          S2
I7                                     1    1    1    I7

S1 S0

CS1104-7                  Larger Multiplexers                           53
Larger Multiplexers (2/6)
When
I0
I1                          S2S1S0 = 000   S2   S1   S0   Y
4:1    I0
I2     MUX                                 0    0    0    I0
I3                                         0    0    1    I1
2:1
I0             0    1    0    I2
S1 S0        MUX          Y         0    1    1    I3
I4                                         1    0    0    I4
I5      4:1                                1    0    1    I5
I6     MUX     I4    S2
1    1    0    I6
I7                                         1    1    1    I7

S1 S0

CS1104-7                       Larger Multiplexers                        54
Larger Multiplexers (3/6)
When
I0
I1                          S2S1S0 = 001   S2   S1   S0   Y
4:1    I1
I2     MUX                                 0    0    0    I0
I3                                         0    0    1    I1
2:1
I1             0    1    0    I2
S1 S0        MUX          Y         0    1    1    I3
I4                                         1    0    0    I4
I5      4:1                                1    0    1    I5
I6     MUX     I5    S2
1    1    0    I6
I7                                         1    1    1    I7

S1 S0

CS1104-7                       Larger Multiplexers                        55
Larger Multiplexers (4/6)
When
I0
I1                          S2S1S0 = 110   S2   S1   S0   Y
4:1    I2
I2     MUX                                 0    0    0    I0
I3                                         0    0    1    I1
2:1
I6             0    1    0    I2
S1 S0        MUX          Y         0    1    1    I3
I4                                         1    0    0    I4
I5      4:1                                1    0    1    I5
I6     MUX     I6    S2
1    1    0    I6
I7                                         1    1    1    I7

S1 S0

BRAVO!!!

CS1104-7                       Larger Multiplexers                        56
Larger Multiplexers (5/6)
 Another implementation of an 8-to-1 multiplexer using
smaller multiplexers:
When
I0         2:1    I0      S2S1S0 = 000      S2   S1   S0   Y
I1        MUX                               0    0    0    I0
0    0    1    I1
I2      2:1        I2    S0                               0    1    0    I2
I3     MUX                                                0    1    1    I3
I0
1    0    0    I4
4:1              1    0    1    I5
S0                              MUX          Y
1    1    0    I6
I4      2:1 I4                                            1    1    1    I7
I5     MUX
S2 S1
S 0 I6           2:1
I7          MUX     I6
Q: Can we use only 2:1 multiplexers?
S0
CS1104-7                             Larger Multiplexers                             57
Larger Multiplexers (6/6)
 A 16-to-1 multiplexer
can be constructed from
five 4-to-1 multiplexers:

CS1104-7                  Larger Multiplexers   58
Standard MSI Multiplexer (1/2)

74151A 8-to-1 multiplexer. (a) Package configuration. (b) Function table.

CS1104-7                     Standard MSI Multiplexer                           59
Standard MSI Multiplexer (2/2)

74151A 8-to-1 multiplexer. (c) Logic diagram. (d) Generic logic symbol.
(e) IEEE standard logic symbol.
Source: The TTL Data Book Volume 2. Texas Instruments Inc.,1985.
CS1104-7                      Standard MSI Multiplexer                        60
Multiplexers: Implementing Functions
(1/3)
 A Boolean function can be implemented using
multiplexers.
 A 2n-to-1 multiplexer can implement a Boolean function
of n input variables, as follows:
 (i) Express in sum-of-minterms form.
Example: F(A,B,C) = A'B'C + A'BC + AB'C + ABC'
= S m(1,3,5,6)
 (ii) Connect n variables to the n selection lines.
 (iii) Put a '1' on a data line if it is a minterm of the function,
'0' otherwise.

CS1104-7                     Multiplexers: Implementing                    61
Functions
Multiplexers: Implementing Functions
(2/3)
F(A,B,C) = S m(1,3,5,6)

This method works because:
0       0
1       1                Output = m0.I0 + m1.I1 + m2.I2 + m3.I3
0       2
1       3 mux    F                + m4.I4 + m5.I5 + m6.I6 + m7.I7
0       4
1
1
5
6
Supplying „1‟ to I1,I3,I5,I6 , and „0‟ to
0       7                 the rest:
A B C            Output = m1 + m3 + m5 + m6

CS1104-7                  Multiplexers: Implementing                   62
Functions
Multiplexers: Implementing Functions
(3/3)
 Example: Use a 74151A to implement:
f(x1,x2,x3) =  m(0,2,3,5)

Realization of f(x1,x2,x3) = m(0,2,3,5).
(a) Truth table.
(b) Implementation with 74151A.

CS1104-7                      Multiplexers: Implementing   63
Functions
Using Smaller Multiplexers (1/6)
 Earlier, we saw how a 2n-to-1 multiplexer can be used to
implement any Boolean function of n (input) variables.
 However, we can use a single smaller 2(n-1)-to-1
multiplexer to implement any Boolean function of n
(input) variables.
 In particular, the earlier function
F(A,B,C) =  m(1,3,5,6)
can be implemented using a 4-to-1 multiplexer (rather
than an 8-to-1 multiplexer).

CS1104-7               Using Smaller Multiplexers            64
Using Smaller Multiplexers (2/6)
 Let‟s look at this example:
F(A,B,C) = S m(0,1,3,6) = A‟B‟C‟ + A‟B‟C + A‟BC + ABC‟
A‟B‟
1     0
1     1
0     2                           1         0
1     3 mux     F                 C         1         F
0     4                                         mux
0     5                           0         2
1     6                           C'        3
0     7
A B C                                    A B

 Note: Two of the variables, A, B, are applied as
selection lines of the multiplexer, while the inputs of
the multiplexer contain 1, C, 0 and C'.
CS1104-7                     Using Smaller Multiplexers                 65
Using Smaller Multiplexers (3/6)
 Procedure
1) Express boolean function in “sum-of-minterms” form.
e.g. F(A,B,C)= S m(0,1,3,6)
2) Reserve one variable (in our example, we take the least
significant one) for input lines of multiplexer, and use the rest
for selection lines.
e.g. C is for input lines, A and B for selection lines.

CS1104-7                    Using Smaller Multiplexers                      66
Using Smaller Multiplexers (4/6)
3) Draw the truth table for function, but grouping inputs by
selection line values, and then determine multiplexer inputs
by comparing input line (C) and function (F) for
corresponding selection line values.

A   B   C   F   Mux
Input
0   0   0   1
1                        1   0
0   0   1   1
C              1         F
0   1   0   0                                    mux
C                        0   2
0   1   1   1
1   0   0   0                                3
0
1   0   1   0
1   1   0   1                                    A B
C’
1   1   1   0

CS1104-7                   Using Smaller Multiplexers                     67
Using Smaller Multiplexers (5/6)
 Alternative: What if we use A for input lines, and B, C
for selector lines?
A   B   C   F   Mux                  A    B    C      F
Input
0   0   0   1                        0    0    0      1
1
0   0   1   1                        0    0    1      1
0   1   0   0                                             A‟ (when BC = 00)
0   1   1   1
C                    0    1    0      0
1   0   0   0
0                    0    1    1      1   A‟ (when BC = 01)
1   0   1   0
1   1   0   1                        1    0    0      0
C’
1   1   1   0                        1    0    1      0   A (when BC = 10)
1    1    0      1
A                   0                1    1    1      0
1           F                         A‟ (when BC = 11)
mux
2
3

B C
CS1104-7                            Using Smaller Multiplexers                           68
Using Smaller Multiplexers (6/6)
 Example: Implement using a 74151A the function:
f(x1,x2,x3,x4) =  m(0,1,2,3,4,9,13,14,15)

CS1104-7             Using Smaller Multiplexers         69
End of file

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