CS1104_ Computer Organisation

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					   CS1104: Computer Organisation

          School of Computing
    National University of Singapore
              Lecture 1: Introduction

             Computer Organisation/Architecture
             Machine Organisation
             Buses
             Instruction Set Architecture (ISA)
             Questions
             Clock Cycles
             Central Processing Unit (CPU)

CS1104-P2-1                 Introduction           2
              Lecture 1: Introduction

         Code Execution
         Memory

CS1104-P2-1            Introduction     3
       Computer Organisation/Architecture

       Computer organisation: electronics
          engineer’s view of a computer system.
         Computer architecture: assembly
          programmer’s view of a computer system –
          an abstract view.
         In practice, difficult to distinguish the two.
         Who needs to study this? Software
          engineers, embedded systems programmers,
          computer engineers.

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    Computer Organisation/Architecture (2)

       In-depth understanding of the inner-workings
          of modern computers, and trade-offs present
          at the hardware/software boundary.
         Emphasis is on the concept understanding
          and not on the hardware implementation.
         Textbook: Computer Organizations and
          Design (The hardware/software interface)
          by David A. Patterson and John L. Hennessy,
          Morgan Kaufmann, 2nd ed, 1998.
         Read Chapter 1.2 and 1.3.
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               Machine Organisation
       von Neumann architecture: Programs and
          data are stored in memory (stored-memory
         Consists of processor, memory and devices.
         Data are carried along buses between

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                Machine Organisation (2)


              Processor   Memory          Devices

                          Cache            Input



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       Bus: A communication path between
         Data bus, control bus, address bus.
         Bus width: the number of lines (bits).
         Data bus width usually coincides with word
          size, which is also usually the register size.
         Address bus width determines the
          addressable address range. A n-bit address
          bus can address up to 2n locations.

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      Instruction Set Architecture (ISA)
       Computer Architecture = Instruction Set +
          Machine Organisation.
         The Instruction Set serves as the interface
          between hardware and software.
         ISA: “… the attribute of a [computing] system as
          seen by the programmer, i.e. the conceptual structure
          and functional behavior, as distinct from the
          organization of the data flows and controls the logic
          design, and the physical implementation.” – Amdahl,
          Blaaw and Brooks, 1964.

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   Instruction Set Architecture (ISA) (2)

                    Compiler     Firmware
                                                 Instruction Set
      Processor   Memory organization       I/O system

                   Datapath & Control

                     Digital Design                PART 1
                     Circuit Design
                                             Electrical Engineering
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   Instruction Set Architecture (ISA) (3)
       Some examples of ISAs:
                 Digital Alpha   (v1, v3)               1992-97
                 HP PA-RISC      (v1.1, v2.0)           1986-96
                 Sun Sparc       (v8, v9)               1987-95
                 SGI MIPS        (MIPS I,II,III,IV,V)   1986-96
                 Intel           (8086,80286,80286,     1978-96

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   Instruction Set Architecture (ISA) (4)
       Issues concerning an ISA design:
               Organisation of programmable storage
               Data types and data structures: encoding and
                 Instruction set
                 Instruction formats
                 Modes of addressing and accessing data items
                  and instructions
                 Exceptional conditions

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      1)      Computer architecture is a study of
              a)   instruction set architecture only.
              b)   programming language only.
              c)   machine organisation only.
              d)   (a) and (c) [Answer]
              e)   (a), (b) and (c)
      2)      Instruction set architecture is an important
              interface between
              a)   digital circuit and datapath control.
              b)   application software and operating system.
              c)   application software and hardware organisation. [Answer]
              d)   compiler and programming language.
              e)   high-level programming language and assembly

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                           Questions (2)
      3)      Which of the following does not belong to the
              definition of an ISA?
              a)   Instruction formats and types.
              b)   Compilation of a C program into machine code. [Answer]
              c)   Encoding and representation of data in memory.
              d)   Modes of addressing and accessing data in memory.
              e)   None of the above.
      4)      Which of the following statements is true?
              a)   Hardware implementation of machine organization is
                   part of the instruction set architecture definition.
              b)   Instruction set architecture is an interface between the
                   assembly language and the machine language.
              c)   A Pentium II processor running at 450 MHz & a Pentium
                   II processor running at 500 MHz have the same ISA. [Ans]
              d)   Computer architecture is a subset of the instruction set
              e)   None of the above.
CS1104-P2-1                       Introduction                         14
                            Questions (3)
      5)      Which of the following statements is true about
              a)   If two machines can read and understand the same
                   piece of memory data, they must have the same ISA.
              b)   If two machines have the same ISA, they must have the
                   same performance.
              c)   In general, executable codes for one ISA cannot be run
                   on another, different ISA. [Answer]
              d)   The ISA of a processor defines the hardware
                   implementation of the processor.
              e)   None of the above.
      6)      State whether this statement is true or false:
                   “Changing the hardware machine organisation will
                   definitely change the instruction set architecture (ISA).”
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                            Questions (4)
      7)      Which of the following can be considered as part of
              the ISA design?
              a)   Specification of high level languages such as JAVA or
              b)   Compiler that translates high level language programs
                   into machine language codes.
              c)   Machine instruction types such as “ADD” or “LOAD”.
              d)   Data accessing method by the processor.
              e)   Implementation of hardware functional units in the
              [Answer: (c), (d)]

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                             Clock Cycles
       A synchronous system is synchronised
         according to a clock.
                    Rising edge

     Falling edge
                             Clock period

       A clock cycle is the duration between two
         consecutive rising (falling) edges, and its
         duration is also known as the clock period.

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                   Clock Cycles (2)
       The clock frequency is the reciprocal of clock
         period, measured in Hertz (Hz): number of
         cycles per second. A clock with period of
         250ns (nano-seconds) has a frequency of


       Clock A has twice the clock period than that of
         clock B, and half the frequency of B’s.
CS1104-P2-1               Introduction               18
          Central Processing Unit (CPU)
       CPU = Control Unit + ALU + Registers.
       Control Unit: monitors and directs sequences
          of instructions.
         ALU (Arithmetic-Logic Unit): performs simple
          arithmetic and logical operations.
               Examples: Add, subtract, and, or, invert, increment, etc.
                               A                   B

                                                       R = A op B
                                     ALU               n-bits operations

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      Central Processing Unit (CPU) (2)
       Registers: Fast memories in the CPU, storing
          operands, temporary results and status
         General-purpose registers and special
                 PC (program counter)
                 ACC (accumulator)
                 IR (instruction register)
                 MAR (memory address register)
                 MBR (memory buffer register) or MDR (memory data

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                        Code Execution

                   Program in                      Link multiple
               High-level language          machine-language programs
                 (C, Pascal, etc)                to one program

                 Compile program                Load program into
              into assembly language            computer’s memory

                Assemble program
                                                Execute program
               to machine language

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                        Code Execution (2)
       Instruction execution cycle:                Fetch
         fetch, decode, execute.
           Fetch: fetch next instruction          Decode
                  (using PC) from memory into
                  IR.                              Operand

                 Decode: decode the                Fetch

                  instruction.                     Execute
                 Execute: execute instruction.

CS1104-P2-1                       Introduction    Instruction   22
       Memory stores programs and data.
       Definitions:
               1 byte = 8 bits
               1 word: in multiple of bytes; a unit of transfer
                  between main memory and registers, usually size
                  of register.
                 1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) =
                  220 bytes; 1 GB (giga-bytes) = 230 bytes; 1TB
                  (tera-bytes) = 240 bytes.
       Desirable properties: fast access, large
          capacity, economical cost, non-volatile.
         However, most memory devices do not
          possess all these properties.
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                     Memory (2)
       Memory hierarchy:
                                          Fast, expensive
                                          (small numbers),

                main memory

                 disk storage
                                          Slow, cheap
                magnetic tapes            (large numbers),

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                          Memory (3)
       Data transfer:
                                            Address   Memory
                             Up to 2k
              Processor                         1
                            locations.          2
                          k-bit address bus     3
                MAR                             4
                           n-bit data bus

                            Control lines
                             (R/W, etc.)

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                         Memory (4)
       A memory unit stores binary information in groups of
          bits called words.
         The data consists of n lines (for n-bit words). Data
          input lines provide the information to be stored
          (written) into the memory, while data output lines
          carry the information out (read) from the memory.
         The address consists of k lines which specify which
          word (among the 2k words available) to be selected
          for reading or writing.
         The control lines Read and Write (usually combined
          into a single control line Read/Write) specifies the
          direction of transfer of the data.

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                       Memory (5)
       Block diagram of a memory unit:
                                              n data
                                            input lines

                                k           Memory unit
              k address lines
                                              2k words
                                           n bits per word


                                               n data
                                             output lines

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                              Memory (6)
       The Write operation:
               Transfers the address of the desired word to the
                  address lines.
                 Transfers the data bits (the word) to be stored in
                  memory to the data input lines.
                 Activates the Write control line (set Read/Write to
       The Read operation:
               Transfers the address of the desired word to the
                  address lines.
                 Activates the Read control line (set Read/Write to
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                             Memory (7)
       The Read/Write operation:
               Memory Enable Read/Write    Memory Operation
                    0            X      None
                    1            0      Write to selected word
                    1            1      Read from selected word

       Two types of RAM: Static and dynamic.
               Static RAMs use flip-flops as the memory cells.
               Dynamic RAMs use capacitor charges to
                represent data. Though simpler in circuitry, they
                have to be constantly refreshed.
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                            Memory (8)
       A single memory cell of the static RAM has
           the following logic and block diagrams:


   Input                S    Q                  Output   Input      BC        Output


                 Logic diagram                               Block diagram

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                 Memory (9)

 Logic construction
   of a 4 x 3 RAM
   (with decoder and
   OR gates):

CS1104-P2-1            Introduction   31
                         Memory (10)
       An array of RAM chips: memory chips are
          combined to form larger memory.
         A 1K x 8-bit RAM chip:

                               RAM 1K x 8

               Input data 8   DATA (8)        (8)
                                                        Output data
                 Address 10   ADRS (10)
              Chip select     CS
              Read/write      RW

                    Block diagram of a 1K x 8 RAM chip

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                               Memory (11)
                                                      Input data
                 Lines         Lines                    8 lines
                11 10          0–9                                    0–1023
                                                                  DATA (8)     (8)
                                                                  ADRS (10)
                         decoder                                        1K x 8

                          S0   0                                   1024 – 2047
                               1                                  DATA (8)     (8)
                          S1   2                                  ADRS (10)
                               3                                  CS
                                                                        1K x 8

                                                                   2048 – 3071
              Read/write                                          DATA (8)     (8)
                                                                  ADRS (10)
                                                                        1K x 8

                                                                   3072 – 4095

     4K x 8 RAM.                                                 DATA (8)
                                                                  ADRS (10)

                                                                        1K x 8       Output
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                                      Memory (12)
                                            addresses                       19-bit internal chip address



                 512K x 8                           512k X 8
                memory chip                        memory chip     D31-24              D23-16              D 15-8   D7-0

       19-bit                     8-bit data
      address                   input/output            Another example:
                                                        Organization of a 2M  32 memory module
                  Chip select
                                                        using 512K  8 static memory chips.

CS1104-P2-1                                         Introduction                                                           34
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