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					                                       CSC Muon Trigger
                                                     Jay Hauser

                                                 Director‟s Review
                                               Fermilab, Apr 30, 2002


                                                     Outline
• The CSC muon trigger design
• Project scope
• Fall 2000 prototype test
• Pre-production prototype to be tested Summer 03
• Conclusions

 Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                  1
                          CMS Endcap Muon System

• 3 or 4 stations
• Each CSC chamber has
  six planes:
   1. Radial cathode strips for
      precision muon position
      and bend direction
      measurement
   2. Anode wires for timing
      (bunch ID) and non-bend
      position measurement




 Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002   2
                                  Geometric Coverage


                                                        ME4 descoped




Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002         3
                                  Trigger requirements
  Cathode LCT
         • Identify cathode track segment.
           Pt trigger based on angle of LCT
         • For Pt threshold of 20-40 GeV requires
           Dp/p < 30% (in order to limit single
           muon trigger rate in Level-1 to a few
           KHz)
         • Track hits must be located to within ½
           strip width in each chamber layer
  Anode LCT
         • Form anode track segment.
         • Tag bunch crossing of track segment
           with > 92 % efficiency per chamber



Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002    4
                     CSC Trigger Efficiency vs. PT

               10
                         20
                                       40                Trigger threshold
                                                    60   defined at 90%
                                                         efficiency

                                                         Sharper turn-on for
                                                         better PT resolution
                                                         Require ME1 for good PT
                                                         resolution
                                                         1.2 < || < 2.4




Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                      5
                     CSC Trigger Efficiency vs. 



                                                        Loose: 2 or more stations
                                                          including ME1 in endcap,
                                                          but any two in DT/CSC
                                                          overlap region
                                                          ~97% efficiency


                                                        Tight: 3 or more stations
                                                           including ME1 in endcap
                                                           and MB1 in DT/CSC
                                                           overlap
                                                           ~70% efficiency
                                                           but better PT resolution




Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                       6
                              CSC Single Muon Rate
                                                            || < 2.1




                                                        Require “tight” track
                                                        conditions (   70%)
                                                        to get acceptable
                                                        rate from
                                                        standalone CSC
                                                        trigger


                                                        Rate must be less
                                                        than few kHz
Multiply by 5 for L = 1034
Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002               7
                      Endcap Muon Trigger Primitive
                              Generation
                Clock Control Board                                 Trig Motherboard
                                                                                                 DDU Board
                                                                             DAQ Motherboard
         Slow Control                  D T D T D T D T D T CMT DT D T DT D
                                       MM M MM MMM MM C P M MM MM MM M
                                     CBB B BB BBB BB BCB BB BB BB B
                                     O

   Muon Sector Receiver              N
                                     T
                                     R                                           Readout Data
      Lev-1 Trigger                  O
                                     L
                                     L
                                     E

  Trigger-Timing-Control             R


                                                                             Peripheral Crate
                                                                               on iron disk
                                                                                                    FED Crate in XSC55


                                          CFEB CFEB CFEB CFEB CFEB                Cathode Front-end Board



        LV Distribution                           LVDB    ALCT
            Board                                                                 Anode LCT Board



                                                                                 Anode Front-end Board
                                                CSC


Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                              8
                      Trigger Motherboard (TMB)
 Source of CSC trigger primitives for 1 chamber: sent on backplane
 to Muon Port Card (MPC)
 Other functions:
        Generates Cathode LCT trigger with input from CFEB (comparator)
        Matches ALCT and CLCT; sends anode hits to DMB.



                                                           Main FPGA
                                                            (on back)
                                                         XILINX XCV1000E
  Input
connectors                                                Mezzanine board
From 5 CFEB’s




                                                             Input
                                                           connectors
                                                            From ALCT
Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                      9
                            CSC Sectors Data Mapping




Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002   10
                             CSC Muon Trigger Scheme
    On-Chamber                                                                   3-D Track-Finding
    Trigger Primitives                                          Muon             and Measurement
                                                Trigger
Strip FE cards                                Motherboard       Port
                                                                Card                  Sector           Sector
                                                                                      Receiver         Processor
                                                     LCT                    OPTICAL

        FE
                                                                  PC                     SR                 SP
                         LCT
                                                    TMB                     3 / port card
        FE
                                                            2 / chamber                      3 / sector
            Wire LCT card
Wire FE cards                                                       In
                                                                 counting
                                  RIM                              house
                                                                                      CSC Muon Sorter
                           RPC Interface                          RPC       DT
                             Module                                    4        4      4

                                     Combination of all              Global  Trigger              Global L1
                                     3 Muon Systems                                           4
    Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                    11
                            Scope of CSC Trigger Project
 Baselined with 24 crates, reduced to 6 in 1998, now 1:
Prototype version tested Fall 2000:
Board               # units       Responsibility
MPC                    48         Rice                     New version (SR/SP combined)
Sector                 24         UCLA                     Board        # units   Responsibility
Receiver
Sector                 12         Florida                  MPC            48      Rice
Processor                                                  SR/SP          12      Florida
Clock and               6         Rice                     Clock and      1       Rice
Control                                                    Control
Board                                                      Board
CSC Muon                1         Rice                     CSC Muon       1       Rice
Sorter                                                     Sorter

Crates,                 6         Florida                  Crates,        1       Florida
Backplanes                                                 Backplanes
DDU                     1         Florida/Ohio             DDU            1       Florida/Ohio
readout                           State                    readout                State
   Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                     12
                        Prototype Test in Fall 2000
• Muon Port Card produces CSC muon segment
  data
• Data sent over Giga-bit optical link
• Sector Receiver receives and formats data
• Formatted data sent over backplane
• Sector Processor links CSC muon segments
  into track, assigns PT, f, 
• Hardware operated at full 40 MHz speed
• Results compared bit-for-bit with simulation
• Perfect agreement attained


 Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002   13
                                        Track Finder Prototype
        FY 2000 focus was on producing and testing a Track
         Finder prototype:
                                                                                                     Items produced:
                                                                                                     •   Backplane (Florida)
                                                                                                     •   Sector Processor (Florida)
                                                                                                     •   Muon Port Card (Rice)
                                                                                                     •   Clock and Control Board (Rice)
       DAQ System (VME, Bit3 Controller, PC running Windows NT)                                      •   Sector Receiver (UCLA)
                                                                                                     •   Test software support (all)




                                                                           FIFO
         Port                                  Sector                             Sector




                                                                                              FIFO
FIFO




                       FIFO



                                        FIFO




         Card                                  Receiver    FIFO                   Processor
                              100m                                Custom
                              Optical                             Back
                              Links                               plane




        Results included in Trigger TDR (Oct. 2000):
             > Input data bits loaded into Port Card or SR
             > Data clocked through MPC SR SP at full speed
             > Results examined for validity

        Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                14
                             Muon Port Card Prototype

                                                               VME
                                                               Interface



Optical
links




                                                             Main FPGA
                                                             on Daughter
                                                             Card




     Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002          15
                            Sector Receiver Prototype

   Optical                                                                  UCLA
Receivers and
 HP Glinks

                                                                         SRAM LUTs




                                           Front FPGAs      Back FPGAs

    Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                   16
                        Sector Processor Prototype
                         Final Selection Unit Extrapolation Units
                                   XCV150BG352             XCV400BG560




                                                                               Florida



12 layers
10K vias
17 FPGAs
12 SRAMs
25 buffers



                 Assignment Units Track Assemblers Bunch Crossing
                   XCV50BG256 &     256k x 16 SRAM    Analyzer
                       2M x 8 SRAM                                XCV50BG256

   Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                          17
                        1st Track-Finder Crate Tests
                           Custom Backplane                 Clock Control   Muon Port Card
    Bit3                   (Florida)                        Board (Rice)    (Rice):
    VME
    Interface

Sector Processor
(Florida):



                                                                                Prototype crate
                                                                                 for original six
                                                                               crate design tests
Sector Receiver                                                                 very successful
(UCLA):
                                                                                but latency too
                                                                                     high --
                                                                                 New design in
                                                                                      2001

                                                                                100m optical
                                                                                fibers
    Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                 18
                                           New EMU Trigger Design:
                                            U. Florida Track-Finder
                                           Track -Finder crate (1.6 Gbits/s optical links)
                                                                                                      SP 2002 Card
Clock and Control                                                                                   (3 Sector Receivers +
      Board                                      SR SR SR SR SR SR              SR SR SR SR SR SR     Sector Processor)




                                                                          CCB
                         BIT3 Controller
                                                                                                         (60 sector)




                                                                     MS
                                                  / / / / / /                    / / / / / /
                                                 SP SP SP SP SP SP              SP SP SP SP SP SP
                                                                                                           From MPC
                                                                                                           (chamber 4)
   Muon Sorter
                                                                                                           From MPC
                                                                                                           (chamber 3)

                                                                                                           From MPC
                                                                                                           (chamber 2)
        From
   Trigger Timing                                                                                          From MPC
       Control                                                                                            (chamber 1B)

                                                                                                           From MPC
                                                                                                          (chamber 1A)
        To
   Global Trigger                                                                                          To DAQ




                   Power consumption : ~ 1000W per crate
                   16 optical connections per SP
                   Custom backplane for SP  CCB and MS connections

Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                       19
                                            New 1-Crate Design Meets
                                              Latency Requirement
                     First prototype dataflow                                                                              Pre-production prototype data flow
                                   From Muon Port Cards                                                                                        From Muon Port Cards




                                                                    Sector Receiver st.2,3


                                                                                             Sector Receiver st.4
                                             Sector Receiver st.1
                      Optical receivers                                                                                                            Optical receivers


            1          Front FPGAs                                                                                               1                   Front FPGAs


            1          Lookup tables                                                                                             1                  Lookup tables                     To DT
                        Channel link                                                                                                 SR/SP board
                        transmitters                                                                                             0
                                                                                                                                      Bunch crossing analyzer (not implemented)
            4
                                 Channel link receivers                                                                          1




                                                                                                                       Latency
                                                                                                                                                  Extrapolation units
  Latency




            2          Bunch crossing analyzer (not implemented)                                                                 1
                                                                                                                                               9 Track Assembler units

                                                                                                                                     Sector Processor
            3                      Extrapolation units
                                                                                                                                          FPGA
                                                                                                                                 1                                 Final selection
                                                                                                                                      Pt precalculation for
            2              9 Track Assembler units (memory)                                                                                                        unit 3 best out
                                                                                                                                            9 muons
                                                                                                                                                                         of 9
                                                                                                  Sector Processor




            3              Final selection unit 3 best out of 9
                                                                                                                                 1    Output multiplexor
            3              Pt precalculation for best 3 muons

                                                                                                                                 1               Pt assignment (memory)
            2                   Pt assignment (memory)


Total: 21 BX                        To Muon Sorter                                                                   Total: 7 BX                     To Muon Sorter
            Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                                                                    20
                              Description of CSC Trigger
                                  System Elements
• MPC (Muon Port Card)
  • Source of muon segment data from chambers
• SR/SP (Sector Receiver/Sector Processor)
  • Links segments into tracks with known momentum
• CCB (Clock & Control Board)
  • Clocking and interface to global control system
• CSC Muon Sorter
  • Collects tracks for transmission to Global Muon Trigger
• Track Finder crate backplane
• DDU (Detector-Dependant Unit)
  • For readout, used for diagnostics for the trigger


  Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002       21
                            New MPC Design (Rice)
                               9U x 400 MM BOARD                                          VME J1
                                                                                         CONNECTOR
                                                                       VME
                                                                    INTERFACE


  UCLA MEZZANINE                                                                CCB
  CARD (XCV600E)
                                                                                CCB


                                                                                TMB_1
                              OPTO            SER          CCB
                                                        INTERFACE               TMB_2
                                                                                           CUSTOM
   3 OPTICAL                                            SORTING                 TMB_3    PERIPHERAL
                                                         LOGIC
   CABLES TO                                                                             BACKPLANE
                              OPTO            SER                               TMB_4
   SECTOR                                                 INPUT
   PROCESSOR                                               AND                  TMB_5
                                                         OUTPUT
                                                           FIFO                 TMB_6
                              OPTO            SER
                                                                                TMB_7
FINISAR FTRJ-8519-1-2.5
OPTICAL TRANSCEIVERS
                                                                                TMB_8
 TLK2501 SERIALIZERS                                      FPGA
                                                                                TMB_9



                                                                          SN74GTLP18612 GTLP TRANSCEIVERS


Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                             22
                        Optical Link Radiation Tests
Three serializers: up to 270 kRad TID.
No permanent damage or SEU
Two Finisar optical modules: No errors up to 70 kRad.
Failed at
 ~70kRad
(well above
~10 kRad TID
inner CSC
dose for
10 years)

-- Rice


   Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002   23
                           Sector Processor 2002 Board
                                     Layout Converter
                                         DC-DC
                        Phi Global LUT
                     Eta Global LUT                              EEPROM
                 Phi Local LUT
  EEPROM                                                                  EEPROM

  Indicators
                                                                       VME/CCB
                                                                       FPGA
    TLK2501
  Transceiver

Front FPGA                                                                From CCB

                                                                       PT LUT     TRANSITION
 DDU FPGA                                                                 To MS   BOARD WITH
                                                                                  LVDS
                                                                                  TRANSCEIVERS

                                                             Main
      Optical                                                FPGA
  Transceiver                                              Mezzanine              TO/ FROM
                                                           Card                   BARREL



   Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                             24
                                           ME1 SR LUT Triad
      FRONT                   CLCT PAT# - 4   PHIL LUT                       PhiB_L - 6   ETAG LUT       PhiB_G - 5    MAIN
      FPGA          A18       Q-4             256K x 18        Phi_L -10     Phi_L - 2    512K x 18                    FPGA
                              CLCT_ID - 8                                   CSC_ID - 4                   Eta_G - 7
                                                Flow           PhiB_L - 6                   Flow
                              L/R -1                                        WG_ID - 7
                                               Through                                     Through
                    C3                                                                     SRAM
                                               SRAM
                              CSC_ID – 4
                    A11       WG_ID – 7
                                                                                                  CSC ID - 4

                                 CLK40P1
                    C3


                                                                                          PHIG LUT       Phi_G -12
                    D16                               16 Bit                Phi_L - 10
                                                                             WG_ID - 5    512K x 36
                                                      Transc                CSC_ID - 4      Flow         Phi_DT - 12
                                                      eiver                               Through
                     C2
                                                                                           SRAM
                     C4
                               CLK40P2
                                                                                                                                 To DT
                    D12
                                                                                               16 Bit

                                                                                               Transc
                    C2                                                                         eiver

                          Legend: A – Address Lines
                                  D - Data Lines                                                                        CLK40
      CLK40                       C – Control Lines

 • 45 synchronous memories for conversion of 15 track segments
                                  CLK – Clock


 • >64 MB per board  Need high VME bandwidth, broadcast
   capability to identical chips, and crate broadcast capability to SPs
Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                           25
                              Main Sector Processor
                      9xD24
                                     FPGA
            ME2/       9xD5                      C3
            ME4                    MAIN                                                         MUX
           STUBS       3xD1        FPGA         3xD12 + 4xD1


                      6xD24
                                                 3xA22
            ME1       6xD9                                      PT    3xD8
           STUBS                                               LUT
                      2xD1                       3xC4

                                                                                   3xD8

            DT
           STUBS      2xD25                                    TRAN
                                                 D8                   3xD8

                                                 3xC1
                       C2                        C1
            DDU        C4
            INT                                                         Legend:
                       D32                                              G – Number of Signal Groups
                                                                        GxAn – G Groups of n Address Lines
                                                                        GxCn – G Groups of n Control Lines
                      C2                                                GxDn - G Groups of n Data Lines
                      C9                                       CFG
            CCB                                                ROM      TRAN - Transceiver
                     CLK40                       C3                     CCB&VME Int – Combined CCB and VME Interface
             &        A8
            VME                                                         CFG ROM – Configuration ROM
                       D16                                              CLK40 – Clock 40 MHz
            INT
                                                                        DDU- INT – Readout Interface



     • Placed on mezzanine card
     • Firmware written in “Verilog++” and implemented in ORCA
       as well
     • Latency only 4 BX
Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                  26
                      CCB for Track Finder Crate
• Same CCB for peripheral and Track Finder crates
• 20 sets (main 9U board + Altera-based mezzanine card)
  have been fabricated so far
• 15 boards are assembled and tested
• 2 boards will be used for Track Finder tests (UF & Rice)

                                                        TTCrx
                                                        mezzanine board




Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                     27
                                                Sorter FPGA
                                                                                                 MUON 1
                                                                                       DFF
TMB 1                                        MUX                      PIPELINE
                                DFF                                              MUX
                                                                  4    MUON 1

                                                                                       FIFO_B
                       VME
                                FIFO                                                   MUON
                                 A                                                       1

                                                                                          VME
                                             MUX                      PIPELINE
                                DFF                                                              MUON 2
                                                                       MUON 2          DFF
                                                              4

                       VME
                                FIFO                                                   FIFO_B
                                 A                                                     MUON
                                                                                         2

TMB 2                                                                                     VME
  •
  •                                                                                    DFF       MUON 3
  •
TMB 9

VME                                                                                    FIFO_B
                                                                                       MUON
                                                                           54
                                 SORTER “3 OUT OF 18”                                    3

CCB             CCB                            9                                          VME    WINNER
             INTERFACE


      Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                     28
                      CSC Track Finder Backplane

                                        Standard VME 64x J1/P1 backplane
                             A24/D16 (but D32 possible using address lines)




                                                                                                                                                   SRSP 10



                                                                                                                                                                            SRSP 12
                                                                                                                                                             SRSP 11
                                SRSP 1

                                         SRSP 2

                                                  SRSP 3

                                                           SRSP 4

                                                                    SRSP 5

                                                                             SRSP 6




                                                                                                                        SRSP 7

                                                                                                                                 SRSP 8

                                                                                                                                          SRSP 9
                                                                                      Clock and control



                                                                                                          Muon sorter
   Standard VME
  J2/P2 backplane




                             Custom GTLP 6U backplane
Signals
specified,
routing to
commence

  Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                                                                                                29
                                   Mirror CSC DAQ Path

OSU now
                                                                                        CSC DDU
plans 20°
                                                                                        designed
slices to
                                                                                        by Ohio
equalize
                                                      15 optical fibers                 State Univ.
bandwidth


                                                                                          36


Sector
                                                 12 optical fibers
Processors
send L1                                                                   DDU   SLINK     +1
data

   Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                                       30
                          CSC Trigger Status/Plans
Prototype 1 tests now complete
Prototype 2 and production follow EMU
  components to optimize technology
MPC, SP, CCC modules, backplane* milestones:
   • Apr-02 Prototype 2 designs done
      • Freeze CSC-DT interface
      • Determine DDU compatibility with OSU module for EMU
   • Nov-02 Prototype 2 construction done
   • Apr-03 Prototype 2 testing done
   • Sep-03 Final designs done
   • Oct-04 Production done
   • Apr-05 Installation done
      (*backplane schedule ~3 months ahead of above dates to
        provide platform for testing and integration)
Muon Sorter module: only 1, design by Jan-04
 Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002         31
                                      CSC „02 Milestones
Syst.          Item                Action                 Date     Status Comment
CSC            Bckpl               Specified Dec-01       Done     OK
CSC            Bckpl               Proto done             Jun-02   Delay: Aug-02 OK
CSC            CCB                 Proto done             Jun-02   Delay: Aug-02 OK
CSC            SR/SP               Proto done             Sep-02   Delay: Nov-02 OK
CSC            Bckpl               Proto tested           Sep-02   Delay: Apr-03 OK
CSC            MPC                 Proto done             Sep-02   OK
CSC            CCB                 Proto tested           Sep-02   Delay: Apr-03 OK




  Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                         32
                                                    Personnel
• Professors
     • Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA),
       Paul Padley (Rice)

• Postdocs
     • Song Ming Wang (Florida), Benn Tannenbaum (UCLA), Slava
       Valouev (UCLA)

• Students
     • Bobby Scurlock (Florida),Jason Mumford (UCLA)

• Engineers
     • JK (UCLA), Alex Madorsky (Florida), Mike Matveev (Rice), Ted
       Nussbaum (Rice)

• Collaborating engineers (all PNPI)
     • Victor Golovtsov, Lev Uvarov


Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002                      33
                     Coordination and Oversight
• Four institutions: Rice, UCLA, UF, UW
• Central link to all documentation:
     • http://afs-web.hep.wisc.edu/~wsmith/cms/trig_pm.html

• Monthly progress reports
• Videoconferences ~6 weeks
• 2-day meetings 3x or 4x per year, rotate between Rice,
  UCLA, and UF, minutes posted
     • UF, March 22-23, 2002
     • UCLA, Dec. 14-15, 2001
     • Rice, Aug 14-15, 2001
     • etc



Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002         34
                                                  Conclusions
• First Track Finder system prototyped successfully in Fall
  2000
   • Exact match to CMS OO simulation package
• Second generation pre-production prototype is well
  underway with significant improvements
• Present and future activities
   • 2001: R&D on optical links, FPGA logic, memory look-ups, backplane
     technology, and DAQ readout
   • 2002: build the 2nd generation prototype
   • 2003: test with multiple CSC chambers, cosmic rays and/or structured
     beam, tweaks for final design (if necessary)
   • 2004: full production
   • 2005: installation
• No trouble expected: all-digital system with off-the-shelf
  components, well-defined internal and external interfaces,
  and a stable and capable engineering team

  Jay Hauser, Fermilab Director‟s Review, Apr. 30, 2002             35

				
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