Operational amplifiers (referred to as "op amp") is a high magnification of the circuit unit. In the actual circuit, the feedback network is usually composed of a combination of functional modules. Since the early analog computer used to implement mathematical operations, so the name "op-amp." Op amp is a name from a functional point of view of circuit elements, can be achieved by the discrete devices, can also be achieved in the semiconductor chip. With the development of semiconductor technology, most of the op amp is a single-chip form. A wide range of op amp, which is widely used in the electronics industry.
EET 323 1 Operational Amplifier design with BJT & MOSFET Technology Daniel L. Longstreet Abstract—Operational amplifiers (Op-Amp) are used in linear AC operations and are widely used in electronic industry. What follows are two operational amplifier designs using bipolar junction Transistor (BJT) Technology and metal oxide semiconductor field effect transistor (MOSFET) Technology. These designs will focus in the input stage and gain stages. The BJT will be modeled as an Op-Amp and characterized. Index Terms—Operational amplifiers, Power electronics. Fig. 1. Operational amplifier I designed the cascode current mirror for a current of 2mA I. INTRODUCTION using the SSM2210 transistor arrays to bias the input stage and A N operational amplifier is made up of several transistors. The Bipolar Junction Transistor (BJT) is widely used with different configurations, and different transistors for different the gain stage. VCC and VEE = ±20V. models of op-amps. The op-amp has an inverting input and a RC1 = RC2 = 10k non-inverting input with one output as in Fig. 1. The op-amp IC = 1mA is powered by ±VDC. re' = 26 Section II will have a BJT Design, Section III will show the results of the simulation of the BJT design, Section IV will 40v − 1.4v have a MOSFET design, and Section V will conclude with a Ic = = 2.14mA few notes. 18kΩ The gain of the input stage is II. BJT OP-AMP DESIGN 10kΩ I designed a three stage operation amplifier with BJT using a Av1 = = 192 cascode current mirror to bias the input stage and the gain 2re ' stage. I added two emitter followers on the inputs to increase input impedance. I also added emitter followers on the gain Input impedance is stage to match impedances from the input stage. I used four different transistors for this design. Zin = β × β × re' NTE912 SSM2210 β1 = 100 β3 = 605 Zin = 100 × 100 × 26Ω VA = 100V VA = 40V Zin = 260kΩ SSM2210 2N3906 The common mode gain is β3 = 165 β4 = 300 − Rc VA = 40V VA = 100V ACM = re'+2 RT − 10kΩ = 26Ω + 2 × 20kΩ * 605 = −0.000413 Manuscript received March 20, 2008. This work was supported in part by Oregon Institute of Technology. D. L. Longstreet is with the Oregon Institute of Technology, Portland, OR 97006 USA (corresponding author to provide phone: 503-866-5561; e-mail: firstname.lastname@example.org). EET 323 2 The common mode rejection ratio is Av1 CMRR = 20 Log ACM TABLE I – Characteristic of the BJT OP-Amp CMRR = 113dB Parameter Condition Dan's Units OPAMP Input Offset TA = 25°C 111 mV Voltage The gain stage consists of a differential pair with an active Input Offset TA = 25°C 200 A load. The differential stage is biased with the cascode current Current mirror. Input Bias TA = 25°C 9.1 A Current The gain of this stage is the output resistance of the active load Input TA = 25°C 400 k divided by 2(Re+re'). Also I ran into the problem of reduce Resistance voltage swing as the voltage at the emitters of the differential Output VS = ±15V ±5 V amplifiers was not close to zero but was around 8.3V. I Voltage Swing RL ≥ 1k centered my voltage around 14V for a max swing of ±6V. Output Short TA = 25°C 45 mA 40V Circuit Current Ro = = 40kΩ 1mA CMRR TA = 25°C 60 dB f = 1 kHz 40kΩ Bandwidth TA = 25°C 2 MHz Av 2 = = 770 Slew Rate 0.2 V/ s 2 × 26Ω . The output stage was design for low output impedance. I used a common emitter to drop the voltage from 14V to around IV. MOSFET DESIGN 1.4V and then used a Darlington pair to reduce my output impedance. The DC out put component was 0.5V. This could be adjusted by changing the amount of voltage drop across the I was not as happy with the MOSFET OP-Amp Design as I had common emitter amplifier in the previous stage. so difficulties with centering my voltage from the differential Ignoring loading effect (as I believe that I can as I designed gain stage. Besides that everything was straight forward. I each stage accordingly) the over all calculated gain was about designed a cascode current mirror for a current of 2mA. This 150,000. bias the differential pair and the active loads. I used the CD4007 transistor array to model my design. III. BJT OP-AMP SIMULATIONS N-Channel KP = 111 After the design process was finished I build and tested my Vto = 2v design. I had problems getting the cascode current mirrors to function correctly so a removed them and replace them with a P-Channel basic current mirror. This did reduce my CMRR but I was still KP = 55 satisfied with the results. I look at the open loop gain, Vto = -1.5V measured the common mode gain and measured the input Id = k (Vgs − Vto ) 2 impedance. I tested my design with a negative feedback network with a gain of -10 and a non-inverting gain of 1. The 2mA = 111µ (Vgs − 2v ) 2 results can be seen if fig. XX in the appendix. Vgs = 6.24v Implementing a cascode current mirror the bias resistor is 40 − 2 * 6.24 Rbias = 2mA Rbias = 13.76kΩ I modeled my design in LTSpice and got a simulated open loop gain of around 10,000. Also I connect a negative feed back network to control the gain with a gain of -10. as seen in Fig. 2. You can see in Fig. 3 that this design does not allow for more then 1.2Vp swing. EET 323 3 Fig. 2. MOSFET inverting amplifier Av = -10 Fig. 3. MOSFET inverting amplifier Av = -10 V. CONCLUSION There are a few things that I should have done differently in the BJT design. I could have added emitter resistors to increase the input impedance or I could have used the SSM2210 with a Beta of 605 at 1mA. That would have increased Zin to 9.5M . I should have picked transistors with a higher early voltage to get more gain when used as an active load and better CMRR when used as a current mirror. I still need no learn more about voltage shifters and output stages to improve the BJT design. I was not very satisfied with my MOSFET design but I do understand the current mirror and active loads. EET 323 4 APPENDIX Fig. 4. BJT OP-Amp Design Fig. 5. MOSFET OP-Amp design EET 323 5 Fig. 9. BJT OP-Amp Measuring Slew Rate. SR = 0.2 v/ s Fig. 6. BJT OP-Amp Open loop gain Fig. 10. BJT OP-Amp Measuring Common mode gain ACM = 0.001 Fig. 7. BJT OP-Amp with negative feedback Av = -10 Daniel L. Longstreet is pursuing his Bachelor of Science in Electronic Engineering Technology from the Oregon Institute of Technology in Portland, OR USA and is expected to graduate June 2009. He also has an Associates of Science in Industrial Electronics from the Technical College of the Fig. 8. BJT OP-Amp Non-inverting Av = 1 LowCounrty Beaufort, SC. USA May 2005. He is working at TriQuint Semiconductor in Hillsboro Oregon as a RF Test Technician.
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