Docstoc

ELEN Advanced Logic Design

Document Sample
ELEN Advanced Logic Design Powered By Docstoc
					ELEN 468
Advanced Logic Design
Lecture 18
MIPS Microprocessor




             ELEN 468 Lecture 18   1
Computer Architecture
  CISC
     Complex Instruction Set Computer
     Intel’s x86, Motorola’s 680x0
  RISC
     Reduced Instruction Set Computer
     Any computer architecture defined after 1984
     MIPS
          Microcomputer without Interlocked Pipeline Stages
          Millions of Instructions Per Second
          Strongly pipelined architecture
          DEC’s Alpha, HP’s Precision



                         ELEN 468 Lecture 18                   2
Registers
  32 32-bit (word) registers
      $a0 - $a3: argument registers
      $v0 - $v1: return values
      $ra: return address register
      $sp: stack pointer
      $fp: frame pointer
      $gp: global pointer
      $zero: always equals 0
      $s0 - $s7: preserved on a procedural call
      $t0 - $t9: not preserved by callee on a procedural
      call

                     ELEN 468 Lecture 18               3
Arithmetic Operations
 add a, b, c # a = b + c
 add $t0, $s1, $s2
 sub a, b, c   #a=b–c
 sub $s0, $t0, $t1

Arithmetic operations occur only on registers




                     ELEN 468 Lecture 18        4
Data Transfer
 lw $t0, 8($s3) # load $t0 with data from memory
               # base address in $s3, offset 8
 sw $t0, 48($s3) # store word

    …         …
                       Byte – 8 bits
   12        101
    8        110       Word – 32 bits
    4         10
                       Memory in words
    0        1001
                       Address to byte level
  Address   Memory

                     ELEN 468 Lecture 18           5
MIPS Fields
R-type          op            rs             rt            rd    shamt       funct

              6 bits        5 bits        5 bits       5 bits    5 bits     6 bits
I-type          op            rs             rt                 address

         op: basic operation, also called opcode
         rs: the first register source operand
         rt:
            R-type: the second register source operand
            I-type: destination register
         rd: the register destination operand
         shamt: shift amount in shift instructions
         funct: selects the specific variant of the operation in op field, also
     called function code
      address: offset of memory address in data transfer instructions

                                     ELEN 468 Lecture 18                             6
Examples of Machine Code
  op   rs   rt   rd   shamt      funct

  0    18   19   17      0        32     add $s1, $s2, $s3

  0    18   19   17      0        34     sub $s1, $s2, $s3



  op   rs   rt        address

  35   18   17          100              lw $s1, 100($s2)

  43   18   17          100              sw $s1, 100($s2)



                  ELEN 468 Lecture 18                        7
Some Other Instructions
 beq $s3, $s4, L1    #   go to branch L1, if equal
 bne $s3, $s4, L1    #   go to branch L1, if not equal
 j L1                #   jump to branch L1
 jr $t0              #   jump based on $t0
 slt $t0, $s1, $s2   #   set value of $t0 to 1, if less than
 sll $t2, $s0, 8     #   reg $t2 = reg $s0 << 8 bits
 srl $t2, $s0, 8     #   reg $t2 = reg $s0 >> 8 bits
 addi $sp, $sp, 4    #   $sp = $sp + 4
 nop                 #   do nothing




                     ELEN 468 Lecture 18                       8
MIPS Addressing Mode
  Register addressing: the operand is a register
  Base or displacement addressing: the
  operand is at the memory whose address is
  the sum of a register and a constant
  Immediate addressing: the operand is a
  constant
  PC (Program Counter)-relative addressing:
  address is the sum of PC and a constant in
  the instruction

                 ELEN 468 Lecture 18          9
Steps for MIPS Instructions
1. Fetch instruction from memory
2. Read registers while decoding the
   instruction
3. Execute the operation or calculate an
   address
4. Access an operand in data memory
   (for lw and sw)
5. Write the result into a register
               ELEN 468 Lecture 18     10
Implement Instruction Fetch


                                             Add


                                         4

    PC   Read
         address
                       Instruction
          Instruction
          memory


                   ELEN 468 Lecture 18             11
Datapath for R-type Instructions
              5   Read                                      Control
                  register 1         Read             32
                                     data 1
              5   Read
                  register 2
Instruction
                               Registers
                                                           ALU
              5                                              Result   32
                  Write
                  register
                                     Read             32
                  Write              data 2
                  data

                                Reg_write



                                ELEN 468 Lecture 18                   12
Example of Instruction Execution Time

 Instruction   Instruction   Register   ALU     Memory   Register   Total
                  fetch       read    operation access    write     time

     lw            2            1            2      2       1        8

     sw            2            1            2      2                7

  R-format         2            1            2              1        6
 (add, sub)

  Branch           2            1            2                       5




                              ELEN 468 Lecture 18                    13
Unpipelined vs. Pipelined
                        2        4        6     8        10   12    14      16        18

lw $t1, 8($s1)     IF   ID ALU            MEM WB

lw $t2, 16($s2)   IF: Instruction fetch             IF    ID ALU   MEM WB
                  ID: Instruction decode
lw $t3, 12($s3)       and read register             MEM: Memory access           IF
                  ALU: Execution or                 WB: Write back to reg
                      address calculation

lw $t1, 8($s1)     IF       ID ALU         MEM WB

lw $t2, 16($s2)             IF       ID ALU      MEM WB

lw $t3, 12($s3)                      IF       ID ALU     MEM WB

                                 ELEN 468 Lecture 18                                   14
Instruction Sets for Pipelining
  All instructions have the same length
  There are only a few instruction formats
  Memory operands only appear in loads
  or stores
  Operands must be aligned in memory



               ELEN 468 Lecture 18      15
Pipeline Hazards
  Situations when the next instruction
  cannot execute in the following clock
  cycle
     Structural hazards
     Control hazards
     Data hazards



                   ELEN 468 Lecture 18    16
Structural Hazards
  Hardware cannot support the combined
  instructions that we want to execute in
  the same clock cycle
  Example: if there is only one memory,
  then memory access and instruction
  fetch cannot be executed
  simultaneously
  Solution: add hardware

               ELEN 468 Lecture 18     17
Control Hazards
  Decision-making depends on the result of an
  instruction that has not been finished
  Example: PC following a branch instruction
  depends if branch is taken or not
  Solutions
     Predict: execute next instruction anyway, if branch
      is taken, retract the decision
     Dynamic prediction based on smart guess



                     ELEN 468 Lecture 18              18
Data Hazards
  An instruction cannot be executed until a data
  is available from another instruction
  Example: add $s0, $t1, $t2
             sub $t2, $s0, $t3
  Solution:
     Bypassing: result can be fed to next instruction
      execution without loading to a register




                     ELEN 468 Lecture 18                 19

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:4
posted:8/4/2011
language:English
pages:19