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					                 1048: Computer
                  Organization
            Lecture 5 – Datapath and
                    Control


Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-1
                   Introduction
• In this lecture, we will try to implement simplified MIPS
  which contain
   – Memory reference instructions: lw, sw
   – Control flow instructions: beg, j
   – Arithmetic-logical instructions: add, sub, and, or, slt
• Design principles
   – Make the common case fast
   – Simplicity favors regularity
• Two types of circuits/function units
   – Combinational: elements that operate on data values
   – Sequential: elements that contain state

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-2
                          Outline
• Part A: Designing a Single-Cycle Processor
• Part B: Designing a Multicycle Processor




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-3
                Part A Outline
• Designing a processor
• Building the datapath
• A single-cycle implementation
• Control for the single-cycle CPU
   – Control of CPU operations
   – ALU controller
   – Main controller




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-4
How to Design a Processor?
1. Analyze instruction set (datapath requirements)
   – The meaning of each instruction is given by the register
      transfers
   – Datapath must include storage element
   – Datapath must support each register transfer
2. Select set of datapath components and establish clocking
   methodology
3. Assemble datapath meeting the requirements
4. Analyze implementation of each instruction to determine
   setting of control points effecting register transfer
5. Assemble the control logic

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-5
  Step 1: Analyze Instruction Set
• All MIPS instructions are 32 bits long with 3 formats:
   – R-type:       31     26        21        16         11            6            0
                      op         rs        rt        rd        shamt       funct
                      6 bits    5 bits    5 bits    5 bits      5 bits     6 bits
   – I-type:       31      26        21        16                                   0
                      op         rs        rt                 immediate
                      6 bits    5 bits    5 bits               16 bits
   – J-type:       31      26                                                       0
                      op                      target address
                      6 bits                      26 bits

• The different fields are:
   –   op: operation of the instruction
   –   rs, rt, rd: source and destination register
   –   shamt: shift amount
   –   funct: selects variant of the “op” field
   –   address / immediate
                                                                                        5A-6
   –   target address: target address of jump
      Our Example: A MIPS Subset
•   R-Type:
     – add rd, rs, rt
     – sub rd, rs, rt 31         26             21         16           11              6             0
     – and rd, rs, rt      op               rs         rt         rd          shamt          funct
     – or rd, rs, rt       6 bits          5 bits     5 bits     5 bits        5 bits        6 bits
     – slt rd, rs, rt
•   Load/Store:         31       26             21         16                                         0
     – lw rt,rs,imm16       op              rs         rt                 immediate
     – sw rt,rs,imm16      6 bits          5 bits     5 bits                16 bits
•   Imm operand:
     – addi     rt,rs,imm16
•   Branch:
     – beq rs,rt,imm16
•   Jump:
                        31       26             21         16                                         0
     – j target
                                 op                         address
                                 6 bits                       26 bits
            Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                 5A-7
  Logical Register Transfers
• RTL gives the meaning of the instructions
• All start by fetching the instruction, read registers, then
  use ALU => simplicity and regularity help
  MEM[ PC ] = op | rs | rt | rd | shamt | funct
     or     = op | rs | rt | Imm16
     or     = op | Imm26 (added at the end)
  Inst          Register transfers
  ADD           R[rd] <- R[rs] + R[rt];   PC <- PC + 4
  SUB           R[rd] <- R[rs] - R[rt];   PC <- PC + 4
  LOAD          R[rt] <- MEM[ R[rs] + sign_ext(Imm16)];       PC <- PC + 4
  STORE         MEM[ R[rs] + sign_ext(Imm16) ] <-R[rt];       PC <- PC + 4
  ADDI          R[rt] <- R[rs] + sign_ext(Imm16)];       PC <- PC + 4
  BEQ           if (R[rs] == R[rt]) then PC <- PC + 4 + sign_ext(Imm16)] || 00
                                   else PC <- PC + 4

         Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)         5A-8
Requirements of Instruction Set
• After checking the register transfers, we can see
  that datapath needs the followings:
   – Memory
        • store instructions and data
   – Registers (32 x 32)
        • read RS
        • read RT
        • Write RT or RD
   –   PC
   –   Extender for zero- or sign-extension
   –   Add and sub register or extended immediate (ALU)
   –   Add 4 or extended immediate to PC

        Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-9
                          Outline
• Designing a processor
• Building the datapath
• A single-cycle implementation
• Control for the single-cycle CPU
   – Control of CPU operations
   – ALU controller
   – Main controller




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-10
Step 2a: Datapath Components
• Basic building blocks of combinational logic
  elements :
                  CarryIn                           Select
    A
        32    Adder                             A
                                                    32




                                                         MUX
                            Sum
                      32                                            Y
                                                               32
    B                       Carry               B
        32                                          32
             Adder                                       MUX
                                ALU control
                                           4
                           A
                               32
                                     ALU

                                                    Result
                                           32
                           B
                               32                                       5A-11
                                    ALU
        Concluding Remarks
• Make sure you understand the abstractions !!
• Sometimes it is easy to think you do, when you
  don’t




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-12
Step 2b: Datapath Components
Storage elements:
• Register:
   – Similar to the D Flip Flop, except
       • N-bit input and output
       • Write Enable input
           – negated (0): Data Out will not change
           – asserted (1): Data Out will become Data In

                                            Write Enable


                                           Data In         Data Out
                                              N             N


                                                     Clk              5A-13
    Storage Element: Register File
                                                                     RW RA RB
                                                    Write Enable
•    Consists of 32 registers:                                       5      5    5
      – Appendix B.8
                                                                                     busA
      – Two 32-bit output busses:
        busA and busB                                 busW           32-bit             32
      – One 32-bit input bus: busW                        32         Registers
•    Register is selected by:                              Clk                       busB

      – RA selects the register to put on busA                                          32
        (data)
      – RB selects the register to put on busB
        (data)
      – RW selects the register to be written
        via busW (data) when Write Enable is 1
•    Clock input (CLK)
      – The CLK input is a factor ONLY during
        write operation
      – During read, behaves as a combinational
        circuit



          Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)            5A-14
  Storage Element: Memory
• Memory (idealized)                             Write Enable        Address
   – Appendix B.8
   – One input bus: Data In
                                               Data In                   DataOut
   – One output bus: Data Out
                                                 32                          32
• Word is selected by:                            Clk
   – Address selects the word to
     put on Data Out
   – Write Enable = 1: address selects the memory
     word to be written via the Data In bus
• Clock input (CLK)
   – The CLK input is a factor ONLY during write operation
   – During read operation, behaves as a combinational logic block:
       • Address valid => Data Out valid after access time
       • No need for read control

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)         5A-15
  Step 3a: Datapath Assembly
• Instruction fetch unit: common operations
   – Fetch the instruction: mem[PC]
   – Update the program counter:
       • Sequential code: PC <- PC + 4
       • Branch and Jump: PC <- “Something else”




                                                    Add


                                               4


                       Read
                PC     address


                                      Instruction
                                                          Fig. 5.5
                        Instruction
                          memory
                                                                     5A-16
         Step 3b: Add and Subtract
        • R[rd] <- R[rs] op R[rt]                              Ex: add         rd, rs, rt
              – Ra, Rb, Rw come from inst.’s rs, rt, and rd fields
              – ALU and RegWrite: control logic after decode
               31            26             21            16          11            6               0
                      op               rs            rt          rd        shamt           funct
                      6 bits          5 bits        5 bits       5 bits    5 bits          6 bits
Two read ports and
one write port
                                                                           4     ALU operation (funct)
                        rs        Read
                                  register 1
                                                       R ead
                        rt                            data 1
                                  Read
                                                                                    Zero
        Instruction               register 2
                                         Registers                         ALU     ALU
                        rd        W rite                                         result
                                  register
                                                       R ead
                                                      data 2
                                  W rite
                                  data
                                                                                                    Fig. 5.7
                                                 RegW rite
                                                                                                               5A-17
       Step 3c: Store/Load Operations
    • R[rt]<-Mem[R[rs]+SignExt[imm16]] Ex: lw rt,rs,imm16
              31              26               21              16        11                        0
                        op                rs         rt                  immediate
                        6 bits        5 bits        5 bits          rd        16 bits

                   rs                                               4
                                                                    3    ALU operation
                             Read
                             register 1                                                                 MemWrite
                                                 Read
                   rt        Read
                                                data 1
Instruction                  register 2                                   Zero
                                    Registers                       ALU ALU
                   rt        Write                                     result            Address
                                                                                                            Read
                             register                                                                       data
                                                 Read
                             Write              data 2
                                                                                                        Data
                             data
                                                                                                       memory
                             RegWrite                                                    Write
                                                                                         data
                                          16              32
                                                 Sign                                                   MemRead
                                                extend

                                                                                                   Fig. 5.8
                                                                                                                   5A-18
                           Datapath for Memory and
                           R-type (b+c), also for addi
              Read                                        ALU operation
              register 1                              4
                               Read                                                 MemWrite
                              data 1
              Read                                                                         MemtoReg
              register 2                                   Zero
Instruction                             ALUSrc
                     Registers Read                   ALU ALU                      Read
              Write                          0                        Address                  1
                              data 2                     result                     data       M
              register                       M
                                              u                                                 u
                                              x                                                 x
              Write                          1                                                 0
              data                                                                 Data
                                                                      Write       memory
               RegWrite                                               data

                      16               32                                           MemRead
                            Sign
                           extend




                                                                              Fig. 5.10

                Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)            5A-19
Step 3d: Branch Operations
• beq    rs, rt, imm16

   mem[PC]                              Fetch inst. from memory

   Equal <- R[rs] == R[rt]              Calculate branch condition

   if (COND == 0)                Calculate next inst. address
        PC <- PC + 4 + ( SignExt(imm16) x 4 )
   else
        PC <- PC + 4

          31       26         21         16                               0
               op         rs         rt               immediate
               6 bits    5 bits     5 bits              16 bits
        Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)       5A-20
Datapath for Branch Operations
• beq            rs, rt, imm16
                      PC + 4 from instruction datapath


                                                           Add Sum        Branch target
                             Only routing
                                                   Shift
                                                  left 2

                                                               ALU operation
                    Read                                   4
                                                           3
   Instruction      register 1
                                        Read
                                       data 1
                    Read
                    register 2                                            To branch
                           Registers                       ALU Zero
                    Write                                                 control logic
                    register
                                        Read
                                       data 2
                    Write
                    data
                      RegWrite

                            16              32                                  Fig. 5.9
                                  Sign
                                 extend
                                                                                           5A-21
                          Outline
• Designing a processor
• Building the datapath
• A single-cycle implementation
• Control for the single-cycle CPU
   – Control of CPU operations
   – ALU controller
   – Main controller




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-22
            A Single Cycle Datapath
                                                                                                         PCSrc

                                                                                                           1
                 Add                                                                                       M
                                                                                                           u
                                                                                                           x
      4                                                                                          ALU       0
                                                                                           Add result
                                                          RegWrite              Shift
                                                                               left 2

                          Instruction [25– 21]      Read
     Read                                           register 1    Read                                    MemWrite
PC                                                               data 1
     address              Instruction [20– 16]      Read                                                                 MemtoReg
                                                                               ALUSrc
           Instruction                              register 2                                 Zero
                                               1                  Read                     ALU ALU
               [31– 0]                              Write       data 2          1                                 Read
                                               M                                              result    Address             1
                                               u    register                    M                                 data
          Instruction     Instruction [15– 11] x                                u                                           M
            memory                                  Write                       x                                           u
                                               0    data     Registers                                                      x
                                                                                0
                                                                                                        Write    Data       0
                                           RegDst                                                       data    memory
                          Instruction [15– 0]               16    Sign    32
                                                                 extend           ALU                     MemRead
                                                                                 control
                                                    Instruction [5– 0]
 Fig. 5.15                                                                       ALUOp




                   Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                                   5A-23
                      Data Flow during add                                                 Fig. 5.11

                                                                                     PCSrc

                                                                                             M
                     Add                                                                     u
                                                                                             x
            4                                                          Add ALU
                                                                          result
                                                               Shift
                                                              left 2
                                             Registers
                                                                       4   ALU operation
100..0100




                                     Read                              3                          MemWrite
            Read                     register 1               ALUSrc
PC                                                Read
            address                  Read       data 1                                                     MemtoReg
                                     register 2                            Zero
                    Instruction                                        ALU ALU
                                     Write       Read                                Address        Read
                                     register                   M        result                     data
                                                data 2          u                                             M
                Instruction                                                                                   u
                  memory             Write                      x                                 Data        x
                                     data                                                        memory
                                                                                     Write
                                    RegWrite                                         data
                                           16            32
                                                 Sign
• Clocking                                      extend                              MemRead




                      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                     5A-24
      Clocking Methodology
• Define when signals are read and written
• Assume edge-triggered (synchronous design):
   – Values in storage (state) elements updated only on a clock edge
     => clock edge should arrive only after input signals stable
   – Any combinational circuit must have inputs from and outputs to
     storage elements
   – Clock cycle: time for signals to propagate from one storage
     element, through combinational circuit, to reach the second
     storage element
   – A register can be read, its value propagated through some
     combinational circuit, new value is written back to the same
     register, all in same cycle => no feedback within a single cycle

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-25
                               Register-Register Timing
Clk
                             Clk-to-Q
PC     Old Value          New Value
                                            Instruction Memory Access Time
Rs, Rt, Rd,
                          Old Value            New Value
Op, Func
                                                           Delay through Control Logic
ALUctr                    Old Value                              New Value


RegWr                     Old Value                              New Value
                                                                        Register File Access Time
busA, B                   Old Value                                             New Value
                                                                                         ALU Delay
busW                      Old Value                                                          New Value



                                Ideal         32
                                                            Rd Rs Rt                                 Register Write
                             Instruction           RegWr                                 ALUctr
                                                           5  5   5                                   Occurs Here
                               Memory
                                                                             busA
                                                           Rw Ra Rb
                     PC




                                           busW                                 32




                                                                                             ALU
                                                           32 32-bit                                      Result
                                             32            Registers                                 32
                                               Clk                           busB
               Clk
                                                                                32
                            The Critical Path
• Register file and ideal memory:
                – During read, behave as combinational logic:
                       • Address valid => Output valid after access time
                                                                 Critical Path (Load Operation) =
                                                                   PC’s Clk-to-Q +
                     Ideal                                         Instruction memory’s Access Time +
                  Instruction                                      Register file’s Access Time +
                    Memory             Instruction
                                                                   ALU to Perform a 32-bit Add +
                                  Rd     Rs    Rt    Imm           Data Memory Access Time +
                                   5      5      5     16          Setup Time for Register File Write +
    Instruction                                                    Clock Skew
      Address
                                                     A                          Data
                                      Rw Ra     Rb                       32    Address
 Next Address




                             32                      32                                        Ideal



                                                                   ALU
                                        32 32-bit                                              Data
                   PC




                                        Registers                             Data In         Memory
                                                     B


                                Clk                                                     Clk
                                                            32
                 Clk
                     Worst Case Timing (Load)
Clk
                         Clk-to-Q
PC     Old Value       New Value
                                    Instruction Memoey Access Time
Rs, Rt, Rd,           Old Value          New Value
Op, Func
                                                  Delay through Control Logic
ALUctr                Old Value                          New Value

ExtOp                 Old Value                         New Value

ALUSrc                Old Value                         New Value

MemtoReg              Old Value                         New Value         Register
                                                                         Write Occurs
RegWr                 Old Value                         New Value
                                                             Register File Access Time
busA                   Old Value                                       New Value
                   Delay through Extender & Mux
busB                   Old Value                                      New Value
                                                                       ALU Delay
Address                Old Value                                                   New Value
                                           Data Memory Access Time
busW                   Old Value                                                         New
                           Outline
•   Designing a processor
•   Building the datapath
•   A single-cycle implementation
•   Control for the single-cycle CPU
    – Control of CPU operations
    – ALU controller
    – Main controller




       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-29
                          Control
• To select the operations to perform
   – ALU, read/write, etc
• To control the flow of data
   – Multiplexor inputs




      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-30
Step 4: Control Points and Signals
                Instruction<31:0>
  Inst.




                   <21:25>

                             <21:25>

                                        <16:20>

                                                  <11:15>

                                                             <0:15>
 Memory
    Addr
             Op Funct Rt               Rs Rd                Imm16


                                       Control
  PCsrc       RegDst     ALUSrc      MemWr                            MemtoReg   Equal
           RegWr     MemRd    ALUctr




                                       Datapath

     Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)               5A-31
    Designing Main Control
• Some observations:
  – opcode (Op[5-0]) is always in bits 31-26
  – two registers to be read are always in rs (bits 25-21)
    and rt (bits 20-16) (for R-type, beq, sw)
  – base register for lw and sw is always in rs (25-21)
  – 16-bit offset for beq, lw, sw is always in 15-0
  – destination register is in one of two positions:
     • lw: in bits 20-16 (rt)
     • R-type: in bits 15-11 (rd)
     => need a multiplex to select the address for written register


     Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-32
     Datapath with Mux and Control
                                                                                                          PCSrc

                                                                                                            1
               Add                                                                                          M
                                                                                                            u
                                                                                                            x
     4                                                                                          ALU         0
                                                                                          Add result
                                                         RegWrite              Shift
                                                                              left 2

                         Instruction [25– 21]      Read
     Read                                          register 1    Read                                      MemWrite
PC                                                              data 1
     address             Instruction [20– 16]      Read                                                                   MemtoReg
                                                                              ALUSrc
           Instruction                             register 2                                 Zero
                                              1                  Read                     ALU ALU
               [31– 0]                             Write       data 2          1                                   Read
                                              M                                              result      Address             1
                                              u    register                    M                                   data
         Instruction     Instruction [15– 11] x                                u                                             M
           memory                                  Write                       x                                             u
                                              0    data     Registers                                                        x
                                                                               0
                                                                                                         Write    Data       0
                                          RegDst                                                         data    memory
                         Instruction [15– 0]               16    Sign    32
                                                                extend           ALU                       MemRead
                                                                                control
                                                   Instruction [5– 0]
             Control point                                                      ALUOp



                                                                                                      Fig. 5.15

                  Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                                         5A-33
       Datapath with Control Unit
                                                                                                                                       0
                                                                                                                                       M
                                                                                                                                       u
                                                                                                                                       x
                                                                                                                        ALU
                                                                                                                  Add result           1
                  Add                                                                                  Shift                               PCSrc
                                                                     RegDst                           left 2
        4                                                            Branch
                                                                     MemRead
                                    Instruction [31 26]              MemtoReg
                                                          Control
                                                                     ALUOp
                                                                     MemWrite
                                                                     ALUSrc
                                                                     RegWrite

                                    Instruction [25 21]               Read
  PC    Read                                                          register 1
        address                                                                        Read
                                    Instruction [20 16]                               data 1
                                                                      Read
                                                                      register 2                                      Zero
                      Instruction                         0                  Registers Read                       ALU ALU
                          [31– 0]                                                                      0                                           Read
                                                          M           Write           data 2                         result    Address                    1
        Instruction                                        u          register                         M                                           data
                                                                                                        u                                                 M
          memory                    Instruction [15 11]    x                                                                                              u
                                                          1           Write                             x                                    Data
                                                                      data                                                                                x
                                                                                                       1                                    memory        0
                                                                                                                               Write
                                                                                                                               data
                                                                                   16            32
                                    Instruction [15 0]                                   Sign
                                                                                        extend           ALU
                                                                                                        control
Fig. 5.17                                                           Instruction [5 0]




                      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                                                                5A-34
Operation of Datapath: add
       31          26        21         16           11            6            0
            op          rs         rt           rd        shamt        funct
            6 bits      5 bits    5 bits       5 bits     5 bits       6 bits

• add rd, rs, rt
   mem[PC]                                 1. Fetch the instruction
   PC+4                                       from memory

   R[rs], R[rt]                            2. Instruction decode
                                              and read operands

   R[rs] + R[rt]                           3. Execute the actual operation

   R[rd] <- ALU                            4. Write back to target register
   PC <- PC+4



        Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)             5A-35
Instruction Fetch at Start of add
                                                                                                                                                   Fig. 5.19
      1. instruction <- mem[PC]; PC + 4
                                                                                                                                           0
                                                                                                                                           M
                                                                                                                                           u
                                                                                                                                           x
                                                                                                                    Add     ALU            1
                                                                                                                          result
                  Add                                                                                    Shift
                                                                      RegDst                            left 2
        4                                                             Branch
                                                                      MemRead
                                    Instruction [31– 26]              MemtoReg
                                                           Control    ALUOp
                                                                      MemWrite
                                                                      ALUSrc
                                                                      RegWrite

                                    Instruction [25– 21]               Read
        Read                                                           register 1
 PC     address                                                                         Read
                                    Instruction [20– 16]               Read            data 1
                                                                       register 2                                       Zero
                      Instruction                          0                  Registers Read
                          [31– 0]                                                                                   ALU ALU
                                                           M           Write           data 2            0                         Address         Read
                                                                                                                       result                             1
        Instruction                                        u           register                          M                                         data
                                                                                                          u                                               M
          memory                                           x                                                                                               u
                                    Instruction [15– 11]               Write                              x
                                                           1                                                                                    Data       x
                                                                       data                              1                                     memory     0
                                                                                                                                   Write
                                                                                                                                   data
                                                                                    16             32
                                    Instruction [15– 0]                                    Sign
                                                                                          extend           ALU
                                                                                                          control

                                                                     Instruction [5– 0]
      Instruction Decode of add
                                                                                                                                                  Fig. 5.19
     2. Fetch the two operands and decode instruction:
                                                                                                                                          0
                                                                                                                                          M
                                                                                                                                          u
                                                                                                                                          x
                                                                                                                   Add     ALU            1
                                                                                                                         result
                 Add                                                                                    Shift
                                                                     RegDst                            left 2
       4                                                             Branch
                                                                     MemRead
                                   Instruction [31– 26]              MemtoReg
                                                          Control    ALUOp
                                                                     MemWrite
                                                                     ALUSrc
                                                                     RegWrite

                                   Instruction [25– 21]               Read
       Read                                                           register 1
PC     address                                                                         Read
                                   Instruction [20– 16]               Read            data 1
                                                                      register 2                                       Zero
                     Instruction                          0                  Registers Read
                         [31– 0]                                                                                   ALU ALU
                                                          M           Write           data 2            0                         Address         Read
                                                                                                                      result                             1
       Instruction                                        u           register                          M                                         data
                                                                                                         u                                               M
         memory                                           x                                                                                               u
                                   Instruction [15– 11]               Write                              x
                                                          1                                                                                    Data       x
                                                                      data                              1                                     memory     0
                                                                                                                                  Write
                                                                                                                                  data
                                                                                   16             32
                                   Instruction [15– 0]                                    Sign
                                                                                         extend           ALU
                                                                                                         control

                                                                    Instruction [5– 0]
       ALU Operation during add
                                                                                                                                                Fig. 5.19
     3. R[rs] + R[rt]
                                                                                                                                           0
                                                                                                                                           M
                                                                                                                                           u
                                                                                                                                           x
                                                                                                                    Add     ALU            1
                                                                                                                          result
                  Add                                                                                    Shift
                                                                      RegDst                            left 2
        4                                                             Branch
                                                                      MemRead
                                    Instruction [31– 26]              MemtoReg
                                                           Control    ALUOp
                                                                      MemWrite
                                                                      ALUSrc
                                                                      RegWrite

                                    Instruction [25– 21]               Read
       Read                                                            register 1
PC     address                                                                          Read
                                    Instruction [20– 16]               Read            data 1
                                                                       register 2                                       Zero
                      Instruction                          0                  Registers Read
                          [31– 0]                                                                                   ALU ALU
                                                           M           Write           data 2            0                         Address         Read
                                                                                                                       result                             1
        Instruction                                        u           register                          M                                         data
                                                                                                          u                                               M
          memory                                           x                                                                                               u
                                    Instruction [15– 11]               Write                              x
                                                           1                                                                                    Data       x
                                                                       data                              1                                     memory     0
                                                                                                                                   Write
                                                                                                                                   data
                                                                                    16             32
                                    Instruction [15– 0]                                    Sign
                                                                                          extend           ALU
                                                                                                          control

                                                                     Instruction [5– 0]
Write Back at the End of add
                                                                                                                                               Fig. 5.19
     4. R[rd] <- ALU;                         PC <- PC + 4
                                                                                                                                           0
                                                                                                                                           M
                                                                                                                                           u
                                                                                                                                           x
                                                                                                                    Add     ALU            1
                                                                                                                          result
                  Add                                                                                    Shift
                                                                      RegDst                            left 2
        4                                                             Branch
                                                                      MemRead
                                    Instruction [31– 26]              MemtoReg
                                                           Control    ALUOp
                                                                      MemWrite
                                                                      ALUSrc
                                                                      RegWrite

                                    Instruction [25– 21]               Read
       Read                                                            register 1
PC     address                                                                          Read
                                    Instruction [20– 16]               Read            data 1
                                                                       register 2                                       Zero
                      Instruction                          0                  Registers Read
                          [31– 0]                                                                                   ALU ALU
                                                           M           Write           data 2            0                         Address         Read
                                                                                                                       result                              1
        Instruction                                        u           register                          M                                         data
                                                                                                          u                                                M
          memory                                           x                                                                                                u
                                    Instruction [15– 11]               Write                              x
                                                           1                                                                                    Data        x
                                                                       data                              1                                     memory      0
                                                                                                                                   Write
                                                                                                                                   data
                                                                                    16             32
                                    Instruction [15– 0]                                    Sign
                                                                                          extend           ALU
                                                                                                          control

                                                                     Instruction [5– 0]
      Datapath Operation for lw
                                                                                                                                              Fig. 5.20
     • R[rt] <- Memory {R[rs] + SignExt[imm16]}
                                                                                                                                          0
                                                                                                                                          M
                                                                                                                                          u
                                                                                                                                          x
                                                                                                                   Add     ALU            1
                                                                                                                         result
                 Add                                                                                    Shift
                                                                     RegDst                            left 2
       4                                                             Branch
                                                                     MemRead
                                   Instruction [31– 26]              MemtoReg
                                                          Control    ALUOp
                                                                     MemWrite
                                                                     ALUSrc
                                                                     RegWrite

                                   Instruction [25– 21]               Read
       Read                                                           register 1
PC     address                                                                         Read
                                   Instruction [20– 16]               Read            data 1
                                                                      register 2                                       Zero
                     Instruction                          0                  Registers Read
                         [31– 0]                                                                                   ALU ALU
                                                          M           Write           data 2            0                         Address         Read
                                                                                                                      result                             1
       Instruction                                        u           register                          M                                         data
                                                                                                         u                                               M
         memory                                           x                                                                                               u
                                   Instruction [15– 11]               Write                              x
                                                          1                                                                                    Data       x
                                                                      data                              1                                     memory     0
                                                                                                                                  Write
                                                                                                                                  data
                                                                                   16             32
                                   Instruction [15– 0]                                    Sign
                                                                                         extend           ALU
                                                                                                         control

                                                                    Instruction [5– 0]
       Datapath Operation for beq
                                                                                                                                               Fig. 5.21
     if (R[rs]-R[rt]==0) then Zero<-1 else Zero<-0
     if (Zero==1) then PC=PC+4+signExt[imm16]*4; else PC = PC + 4
                                                                                                                                          0
                                                                                                                                          M
                                                                                                                                          u
                                                                                                                                          x
                                                                                                                   Add     ALU            1
                                                                                                                         result
                 Add                                                                                    Shift
                                                                     RegDst                            left 2
       4                                                             Branch
                                                                     MemRead
                                   Instruction [31– 26]              MemtoReg
                                                          Control    ALUOp
                                                                     MemWrite
                                                                     ALUSrc
                                                                     RegWrite

                                   Instruction [25– 21]               Read
       Read                                                           register 1
PC     address                                                                         Read
                                   Instruction [20– 16]               Read            data 1
                                                                      register 2                                       Zero
                     Instruction                          0                  Registers Read
                         [31– 0]                                                                                   ALU ALU
                                                          M           Write           data 2            0                         Address         Read
                                                                                                                      result                             1
       Instruction                                        u           register                          M                                         data
                                                                                                         u                                               M
         memory                                           x                                                                                               u
                                   Instruction [15– 11]               Write                              x
                                                          1                                                                                    Data       x
                                                                      data                              1                                     memory     0
                                                                                                                                  Write
                                                                                                                                  data
                                                                                   16             32
                                   Instruction [15– 0]                                    Sign
                                                                                         extend           ALU
                                                                                                         control

                                                                    Instruction [5– 0]
       Concluding Remarks (1/2)
   • Control Signals              (Fig. 5.16)
inst    Register Transfer
ADD     R[rd] <- R[rs] + R[rt];                        PC <- PC + 4
   ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, PCsrc = “+4”
SUB     R[rd] <- R[rs] - R[rt];                        PC <- PC + 4
   ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, PCsrc = “+4”
LOAD    R[rt] <- MEM[ R[rs] + sign_ext(Imm16)]; PC <- PC + 4
   ALUsrc = Im, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, PCsrc=“+4”
STORE   MEM[ R[rs] + sign_ext(Imm16)] <- R[rs];PC <- PC + 4
   ALUsrc = Im, ALUctr = “add”, MemWr, PCsrc = “+4”
BEQ     if (R[rs]==R[rt]) then PC<-PC+sign_ext(Imm16)] || 00 else PC<-PC+4
   PCsrc = Branch address, ALUctr = “sub”

          Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-42
              Concluding Remarks (2/2)
•   RegDst:
     –   0=>rt;
     –   1=>rd                                                                                                                                                      0

•   RegWrite:                                                                                                                                                       M
                                                                                                                                                                    u
                                                                                                                                                                    x
     –   1=>write dest. reg.                                                                                                                         ALU
                                                                                                                                               Add result           1


•   ALUsrc:
                                               Add                                                                                  Shift                               PCSrc
                                                                                                  RegDst                           left 2
                                     4                                                            Branch
     –   0=>regB;                                                                                 MemRead

     –   1=>immed
                                                                 Instruction [31 26]              MemtoReg
                                                                                       Control
                                                                                                  ALUOp


•   PCsrc:
                                                                                                  MemWrite
                                                                                                  ALUSrc
                                                                                                  RegWrite
     –   0=>PC<-PC+4;                                            Instruction [25 21]               Read
     –   1=>PC<-branch addr.   PC    Read                                                          register 1
                                     address                                                                        Read
                                                                 Instruction [20 16]                               data 1
                                                                                                   Read

•   MemRead:                                                                                       register 2                                      Zero
                                                   Instruction                         0                  Registers Read                       ALU ALU
                                                       [31– 0]                                                                      0                                           Read
                                                                                       M           Write           data 2                         result    Address                    1
                                                                                                                                                                                data
     –   1=>read memory
                                     Instruction                                        u          register                         M
                                                                                                                                     u                                                 M
                                       memory                    Instruction [15 11]    x                                                                                               u
                                                                                       1           Write                             x                                    Data          x
•   MemWrite:
                                                                                                   data                             1                                    memory        0
                                                                                                                                                            Write
                                                                                                                                                            data
     –   1=>write memory                                         Instruction [15 0]
                                                                                                                16
                                                                                                                      Sign
                                                                                                                              32


•   MemtoReg:
                                                                                                                     extend           ALU
                                                                                                                                     control


     –   0=>write reg. from ALU;                                                                 Instruction [5 0]


     –   1=>write reg. from memory



                    Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                                                                                     5A-43
                           Outline
•   Designing a processor
•   Building the datapath
•   A single-cycle implementation
•   Control for the single-cycle CPU
    – Control of CPU operations
    – ALU controller
    – Main controller




       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-44
 Our Plan for the Controller
                                   7  func
              Op code                   6            ALU      ALUctr
                         Main
                                                    Control




                                                                                      ALU
                6       Control     ALUop                        3
                                                    (Local)
                                        2
         31        26        21          16         11           6              0
R-type        op        rs         rt          rd        shamt          funct


• ALUop is 2-bit wide to represent:
    – “I-type” requiring the ALU to perform:
          • (00) add for load/store and (01) sub for beq
    – “R-type” (10), need to reference func field
                              R-type            lw        sw          beq           jump
    ALUop (Symbolic)          “R-type”          Add       Add        Subtract        xxx
       ALUop<1:0>              10               00        00           01            xxx

          Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)            5A-45
    Step 5a: Implement ALU Control
•   Recall: ALU design in Chapter 3 and func
            ALUctr       ALU Operation           funct<5:0>   Instruction Operation
              0000           AND                   10 0000       add
              0001           OR                    10 0010       subtract
              0010           add                   10 0100       and
              0110           sub                   10 0101       or
              0111      set-on-less-than           10 1010       set-on-less-than
      ALUop                     func                     ALU                ALUctr
                             bit<3>bit<2>bit<1> bit<0> Operation bit<3>
    bit<1> bit<0> bit<5>bit<4>                                         bit<2> bit<1>   bit<0>
lw     0      0      x     x   x     x    x      x       Add        0     0    1        0
sw     0      0      x     x   x     x    x      x       Add        0     0     1       0
beq    0      1      x     x   x     x    x      x     Subtract     0     1     1       0
R      1      0      1     0   0     0    0      0       Add        0     0     1       0
R      1      0      1     0   0     0    1      0     Subtract     0     1     1       0
R      1      0      1     0   0     1    0      0       And        0     0     0       0
R      1      0      1     0   0     1    0      1        Or        0     0     0       1
R      1      0      1     0   1     0    1      0     Set on <     0     1     1       1

          Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)             5A-46
      Logic Equation for ALUctr
   ALUop                    func                                               ALUctr
bit<1> bit<0> bit<5>     bit<3>bit<2>bit<1>bit<0>
                    bit<4>                                                bit<2> bit<1> bit<0>
                                                                     bit<3>
   0      0      x     x   x     x    x     x                           0    0    1      0
  x       1        x     x    x      x     x      x                     0       1   1      0

  1       x        x     x    0      0     0      0                     0       0   1      0
  1       x        x     x    0      0     1      0                     0       1   1      0
  1       x        x     x    0      1     0      0                     0       0   0      0
  1       x        x     x    0      1     0      1                     0       0   0      1
  1       x        x     x    1      0     1      0                     0       1   1      1



                                         Fig. 5.13


              Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)           5A-47
Logic Equation for ALUctr2
    ALUop                         func
bit<1> bit<0> bit<5>bit<4> bit<3> bit<2> bit<1> bit<0>            ALUctr<2>
   x      1      x     x      x      x      x      x                 1
   1      x      x     x      0      0      1      0                 1
   1      x      x     x      1      0      1      0                 1

          Fig. 5.13                      This makes func<3> a don’t care



ALUctr2 = ALUop0
  + ALUop1‧func2’‧func1‧func0’



     Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)          5A-48
Logic Equation for ALUctr1
     ALUop                          func
bit<1> bit<0>     bit<5> bit<4> bit<3> bit<2> bit<1>        bit<0>       ALUctr<1>
   0       0         x      x      x      x      x             x            1
   x       1         x      x      x      x      x             x            1
   1       x         x      x      0      0      0             0            1
   1       x         x      x      0      0      1             0            1
   1       x         x      x      1      0      1             0            1

                                             don’t care
           Fig. 5.13

ALUctr1 = ALUop1’
  + ALUop1‧func2’‧func0’


       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)        5A-49
Logic Equation for ALUctr0
     ALUop                          func
bit<1> bit<0>       bit<5> bit<4> bit<3> bit<2> bit<1> bit<0>           ALUctr<0>
   1      x            x      x      0      1      0      1                 1
   1      x            x      x      1      0      1      0                 1


          Fig. 5.13
ALUctr0 = ALUop1
 ‧func3’‧func2‧func1’‧func0
 + ALUop1’‧func3
 ‧func2’‧func1‧func0’

• See Fig. 5.13 for complete truth table
      Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)         5A-50
The Resultant ALU Control Block




   Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-51
                             Outline
•   Designing a processor
•   Building the datapath
•   A single-cycle implementation
•   Control for the single-cycle CPU
    –   Control of CPU operations
    –   ALU controller
    –   Main controller




         Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-52
Step 5b: Implement Main Control
Logic equation for each control signal:

Branch:          if (OP == BEQ) then 1 else 0
ALUsrc :         if (OP == 0 (R-type)) then regB else immed
ALUop:           if (OP == 0 (R-type)) then funct
                          elseif (OP == BEQ) then “sub”
                          else “add”
MemWr:           (OP == SW)
MemtoReg:        (OP == LW)
RegWr:           if ((OP == SW) || (OP == BEQ))
                          then 0 else 1
RegDst:          if (OP == LW) then 0 else 1

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-53
  Truth Table of Control Signals
     See         func 10 0000 10 0010           We Don’t Care :-)
Appendix A         op 00 0000 00 0000   10 0011    10 1011   00 0100
                       add      sub       lw         sw        beq
         RegDst         1        1         0          x         x
         ALUSrc         0        0         1          1         0
         MemtoReg       0        0         1          x         x
         RegWrite       1        1         1          0         0
         MemRead        0        0         1          0         0
                                                                        Fig. 5.22
         MemWrite       0        0         0          1         0
         Branch         0        0         0          0         1
         ALUop1         1        1         0          0         0
         ALUop0         0        0         0          0        1
                       RegDst
                                               func
                       ALUSrc                               ALU        ALUctr
   Op code    Main                               6
     6       Control
                            :                              Control        4
                       ALUop                               (Local)
                           2
   Truth Table for RegWrite
     Op code             00 0000         10 0011 10 1011 00 0100
                         R-type            lw     sw      beq
   RegWrite                 1               1       0      0
RegWrite = R-type + lw
   = op5’‧op4’‧op3’‧op2’‧op1’‧op0’ (R-type)
   + op5‧op4’‧op3’‧op2’‧op1‧ op0 (lw)
            .
        op<5> .         .
                    op<5> .         .
                                op<5> .            .
                                               op<5> .             .
                                                               op<5> .
                  <0>         <0>           <0>          <0>             op<0>




       R-type           lw          sw            beq      jump                  RegWrite


         Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)            5A-55
PLA Implementing Main Control
  Inputs
   Op5
   Op4
   Op3
   Op2
   Op1
   Op0



                                Outputs
     R-format   Iw   sw   beq              Fig. C.2.5
                                RegDst

                                ALUSrc
                                MemtoReg
                                RegWrite
                                MemRead
                                MemWrite
                                Branch
                                ALUOp1

                                ALUOpO
                                                        5A-56
Putting it Altogether (+ jump instruction)
                                                                                                                                                    Fig. 5.24

                                  Instruction [25– 0]         Shift         Jump address [31– 0]
                                                             left 2
                                                        26            28                                                                            0            1

                                              PC+4 [31– 28]                                                                                         M            M
                                                                                                                                                    u            u
                                                                                                                                                    x            x
                                                                                                                                     ALU
                                                                                                                               Add result           1            0
                Add                                                                                                 Shift
                                                                                 RegDst
                                                                                 Jump                              left 2
      4                                                                          Branch
                                                                                 MemRead
                                        Instruction [31– 26]
                                                                      Control    MemtoReg
                                                                                 ALUOp
                                                                                 MemWrite
                                                                                 ALUSrc
                                                                                 RegWrite

                                        Instruction [25– 21]                      Read
      Read                                                                        register 1
 PC   address                                                                                      Read
                                        Instruction [20– 16]                                      data 1
                                                                                  Read
                                                                                  register 2                                       Zero
                    Instruction                                       0                  Registers Read                        ALU ALU
                        [31– 0]                                                                                     0                                        Read
                                                                      M           Write           data 2                          result    Address                    1
      Instruction                                                      u          register                          M                                        data
                                                                                                                     u                                                 M
        memory                          Instruction [15– 11]           x                                                                                                u
                                                                      1           Write                              x                                   Data
                                                                                  data                                                                                  x
                                                                                                                    1                                   memory         0
                                                                                                                                            Write
                                                                                                                                            data
                                                                                               16             32
                                        Instruction [15– 0]                                           Sign
                                                                                                     extend           ALU
                                                                                                                     control

                                                                                Instruction [5– 0]




                    Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)                                                                                  5A-57
                     Worst Case Timing (Load)
Clk
                         Clk-to-Q
PC     Old Value       New Value
                                    Instruction Memoey Access Time
Rs, Rt, Rd,           Old Value          New Value
Op, Func
                                                  Delay through Control Logic
ALUctr                Old Value                          New Value

ExtOp                 Old Value                         New Value

ALUSrc                Old Value                         New Value

MemtoReg              Old Value                         New Value          Register
                                                                          Write Occurs
RegWr                 Old Value                         New Value
                                                             Register File Access Time
busA                   Old Value                                       New Value
                   Delay through Extender & Mux
busB                   Old Value                                      New Value
                                                                       ALU Delay
Address                Old Value                                                   New Value
                                           Data Memory Access Time
busW                   Old Value                                                         New
    Drawback of Single-Cycle Design
•   Long cycle time:
     –   Cycle time must be long enough for the load instruction:
           PC’s Clock -to-Q +
           Instruction Memory Access Time +
           Register File Access Time +
           ALU Delay (address calculation) +
           Data Memory Access Time +
           Register File Setup Time +
           Clock Skew

•   Fixed clock cycle time
     –   Cycle time for load is much longer than needed for all other instructions
         (Significant penalty, Worst case design !!)
•   Variable clock cycle time?
     –   Hard to implement
     –   Asynchronous design style?


          Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)            5A-59
                         Summary
• Single cycle datapath => CPI=1, Clock cycle time long
• 5 steps to design a processor:
   1. Analyze ISA => datapath requirements
   2. Select set of datapath components
   3. Assemble datapath meeting the requirements
   4. Analyze implementation of each instruction to determine
      setting of control points
   5. Assemble the control logic
• MIPS makes control easier
   – Instructions same size
   – Source registers always in same place
   – Immediates same size, location
   – Operations always on registers/immediates

       Lecture05A - simple implementation (cwliu@twins.ee.nctu.edu.tw)   5A-60

				
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