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                          OAK BALLROOM                 FIR BALLROOM                 PINE BALLROOM                 CEDAR BALLROOM          SIERRA BALLROOM   BAYSHORE FOYER
                                                                                                                                                            Educational Session
                            Ed Session 1 -                                                                                                                      Registration
                                                       Ed Session 2 -               Ed Session 3-High-                                                       7:00 am - 2:00pm
                       Integrated Phase-Locked
 8:00 am - 5:00 pm                                   Advanced RF Design        Performance and Low-Power
                         Systems-Optimization                                                                                                                Technical Session
                                                         Techniques                Digital Circuit Design
                              and Trends                                                                                                                        Registration
                                                                                                                                                             2:00 pm - 5:00 pm

 7:30 am - 5:00 pm
 8:00 am - 9:30 am      1. Keynote Presentation                                                                                                              Technical Session
                       2. Advances in Analog &                                                                                                                 Registration
                                                                                                               5 Measurement Techniques
10:00 am - 12:00 pm      Digital Programmable          3.RF Techniques          4. Delta-Sigma Converters
                                                                                                                 for High Speed Signals
                      6. Power Optimized RF and     7. Wireless Transmitter                                       9. Advanced Analog                         7:30 am - 5:00 pm       Exhibits
 1:30 pm - 5:15 pm                                                                  8.D/A Converters                                                                                  Open
                             Wireline SoCs              Building Blocks                                          Verification Technique
 5:15 pm - 6:00 pm                                                                  Author Interviews –Gateway Foyer                                                              3:30 – 8:00 pm
 5:00 pm - 7:00 pm                                                                                                                                                                Poster Session
 5:30 pm - 7:00 pm

 7:30 am – 5:00 pm
                                                  11. Emerging Technologies:
                                                   Materials and Structures    12. Nyquist Analog-to-Digital      13. Signal and Data                        Technical Session
8:00 am - 12:00 pm     10. Advanced Memories
                                                    14. Design for Test and            Converters                     Processing                               Registration
12:00 pm – 1:50 pm                                                                                                                         CICC Luncheon     7:30 am - 5:00 pm
                       15. SoC/SiP 3-D Power/                                                                      18. Productivity
 2:00 pm – 3:45 pm    Signal Transport & MEMS/     16. Eye-Opening Circuits      17. Analog Techniques         Enhancement and Design
                        Sensors Management.                                                                         Optimization
                                                                                                                                                                                  3:30 - 7:30 pm
                          19. Panel: Can the                                                                                                                                         Exhibits
                                                  20. Fabless to Designless-
                        Analog/RF Designer/
 4:00 pm – 5:30 pm                                   How Do We Manage
                      Enterpreneur Make Money                                                                                                                                         Open
                                                  Globalization Challenges?
                        in a Fabless Startup?                                                                                                                                     3:30 - 7:30 pm
 5:30 pm - 6:00 pm                                                                  Author Interviews – Gateway Foyer
 5:30 pm - 7:30 pm                                                                                                                                                                 Happy Hour

 7:30 am - 3:00 pm
                                                                                                                                                             Technical Session
                                                                                23. Advanced Technology                                                         Registration
8:00 am - 12:00 pm       21. Custom Circuits            22. Oscillators             Developments and              24. Modeling for RF                        7:30 am - 3:00 pm
                                                                                 Fabrication Challenges

                                                    26. Clocking and Data
 1:30 pm – 5:15 pm       25. PLLs and DLLs                                       27. Wireless Receivers          28. High Speed Analog
 4:45 pm - 5:30 pm                                                                  Author Interviews – Gateway Foyer
 5:30 pm – 8:00 pm                                                               CDNLive!, San Jose Convention Center
                    2006 STEERING COMMITTEE

Henry Chang, Designer’s Guide           Larry Starr, Intel Corporation
Consulting                              Trudy Stetzler, Texas Instruments
Phil Diodato, Agere Systems             Larry Wissel, IBM
Ann Rincon, AMI Semiconductors

                 2006 ORGANIZING COMMITTEE

General Chair                           Panel Chair
Henry Chang, Designer’s Guide           Ranjit Gharpurey, Univ. of Texas
                                        Publicity Chair
Conference Chair                        Jeanne Trinko Mechler, IBM
Larry Wissel, IBM
                                        Sponsorship Chair
Technical Program Chair                 Rakesh Patel, Altera Corporation
Ann Rincon, AMI Semiconductors
                                        Best Paper Awards
Educational Sessions Chair              Steve Wilton, Univ. British Columbia
Larry Nagel, Omega Enterprises
Exhibits Chair                          Trudy Stetzler, Texas Instruments
Paul Billig, Cavendish Kinetics


                          Analog Circuit Design
Chair:    Jennifer Lloyd, Analog Devices
Rick Carley, Carnegie Mellon Univ. David Nairn, University of Waterloo
Yun Chiu, University of Illinois   Kathleen Philips, Philips Research
Yusuf Haque, Maxim Integrated      Dave Rich, Consultant
Products                           Don Thelen, AMI Semiconductor
Takahiro Miki, Renesas Tech. Corp

              Characterization, Debug, Test and Reliability
Chair:     Gordon Roberts, McGill University
Robert Aitken, ARM                 Kenichi Osada, Hitachi
Hamid Mahmoodi, San Francisco      Jeanne Trinko Mechler, IBM

           Custom Applications and Low-Power Techniques
Chair:    Jamil Kawa, Synopsys
Franco Maloberti, Univ. of Pavia        Kenneth Szajda, LSI Logic
Jackie Snyder, Intel Corporation        Makoto Takamiya, Univ. of Tokyo

                           Embedded Memory
Chair:     Tom Andre, Freescale Semiconductor
Takashi Akioka, Renesas           Kenji Noda, NScore, Inc.
Phil Diodato, Agere Systems       Jean-Christophe Vial, Infineon
Sreedhar Natarajan, Emerging      Technologies
Memory Technologies

                         Emerging Technologies
Chair:    Kris Iniewski, Univ. of Alberta
Sudhir Aggarwal, Adonics              Betty Prince, Memory Strategies
Technology                            International
Mourad El-Gamal, McGill Univ.         Larry Wissel, IBM
Dawn Fitzgerald, JAM Tech.

Chair:     Philippe Jansen, IMEC
Jordan Lai, TSMC                          Larry Starr, Intel Corporation
Rich Liu, Macronix International          David Sunderland, Boeing Satellite
Alvin Loke, Advanced Micro                Systems

                         Programmable Devices
Chair:     Arif Rahman, Xilinx
Steve Wilton, University of British       Arif Rahman, Xilinx

                       Signal and Data Processing
Chair:     Lawrence Clark, Arizona State University
Bryan Ackland, Nobel Device         Ravi Kolagotla, Intel Corporation
Technology                          Ram Krishnamurthy, Intel Corp.
Amine Bermak, Hong Kong Univ.
of Science and Technology

                        Simulation and Modeling
Chair:    Colin McAndrew, Freescale Semiconductor
Yuhua Cheng, Siliconlinx         Larry Nagel, Omega Enterprises
Gennady Gildenblat,              Hidetoshi Onodera, Kyoto Univ.
Pennsylvania. State University   Hong-Ha Vuong, Agere Systems
Rob Jones, IBM

                SoC/SiP-IP Generation and Management
Chair:      Ric Williams, Sun Microsystems
Paul Billig, Cavendish Kinetics      Aurangzeb Khan, Cadence Design
Henry Chang, Designer’s Guide        Rakesh Patel, Altera Corp.

                         Wired Communications
Chair:      Kumar Lakshmikumar, Conexant
Tony Chan Carusone, Univ. of      Eric Naviasky, Cadence Design
Toronto                           Cormac O’Connell, Emerging
Sang-Soo Lee, Pixelplus Semicond Memory Technologies.
Shahriar Mirabbasi, University of Amjad Obeidat, National
British Columbia                  Semiconductor
Un-Ku Moon, Oregon State          Jafar Savoj, Rambus

                             Wireless Designs
Chair:    Francesco Svelto, Univ. of Pavia
Stefan Drude, Philips Semicond.    Earl McCune, Panasonic Wireless
Ranjit Gharpurey, Univ ofTexas     Ali Niknejad, Univ. of California,
Ramesh Harjani, Univ. of Minn.     Berkeley
Payam Heydari, Univ. of California John Rogers, Carleton University
Noboyuki Itoh, Toshiba             Trudy Stetzler, Texas Instruments
Kevin Kornegay, Georgia Inst. of   Cicero Vaucher, Philips Research

Welcome from the CICC Committee

Welcome to CICC 2006, the 28th annual IEEE Custom Integrated Circuits
Conference and leading international conference for integrated circuit
development. We begin the conference with a look at the future of mobile
devices with a keynote entitled “The Evolution of Semiconductor Needs in
Handsets” by Dr. Sanjay Jha of Qualcomm. Our conference luncheon
guest speaker, Dr. Tom Lee from Stanford University, will provide us with a
look at our past with his talk entitled “A Rambling History of the Integrated
Circuit.”   CICC offers attendees a total educational experience with
technical lecture and poster presentations, exhibits, panels, tutorials, and
interesting networking events. We cordially invite you to participate in
CICC 2006 at the DoubleTree Hotel in San Jose, California.

The conference begins on Sunday, September 10
with three educational sessions taught by
practicing experts working at the leading edge of
their fields. The session themes are “Integrated
Phase-Locked Systems-Optimization and Trends”;
“Advanced RF Design Techniques”; and “High-
Performance and Low-Power Digital Circuit

Monday morning Dr. Sanjay Jha of Qualcomm will
discuss his vision of future opportunities in the
wireless space and the technology innovations
required to make next-generation devices a
reality. His keynote presentation, “The Evolution
of Semiconductor Needs in Handsets” will provide           Henry Chang
a stimulating opening for the CICC technical                General Chair

A record number of paper submissions in 2006
allow us to bring you a conference of the highest
technical caliber. This year 194 papers were
selected from 423 submitted and organized into
27 sessions. The topics addressed by these high
quality papers include analog and custom circuits;
wired and wireless communications; low-power
techniques; SoC/SiP-IP devices; simulation and
modeling; signal and data processing; embedded
memories; programmable devices, fabrication,
test and reliability, and emerging technologies.
                                                            Larry Wissel
Highlights include invited and tutorial papers from
                                                          Conference Chair
leading experts from industry and academia.

Our Monday evening Welcome Reception and
Tuesday Happy Hour are professional networking
at its very best! Our exhibits area will include
booths and software demonstrations from
prominent industry suppliers and a lively Poster
Session. The poster session is a unique forum for
in-depth discussions with authors.

Tuesday     afternoon’s   two   spirited   panel
discussions feature experts who are sure to offer
strong opinions on the topic areas: “Can the                Ann Rincon
Analog/RF Designer/Entrepreneur Make Money in             Technical Program
a Fabless Startup?” and “Fabless to Designless -                Chair
How Do We Manage the Challenges of

At the conference luncheon Dr. Tom Lee of Stanford University will trace
the evolution of the IC from its humble origins to today’s gigascale chips in
his talk “From Rocks to Chips: A Rambling History of the Integrated

CICC is co-located with the IEEE Behavior, Modeling, and Simulation
Conference 2006. BMAS will take place September 14 – 15 at the

DoubleTree Hotel, San Jose, California. Visit the BMAS website at for complete conference information.

We extend our thanks to all the authors who spent many hours preparing
their papers and presentations. We also wish to thank the CICC Technical
Program Committee and our dedicated conference staff for all of their hard
work and support. Their diligent efforts keep CICC as the best place to
discover the latest in integrated circuit innovations, to hear the newest
product announcements, and to debate the most effective business
strategies. See you in San Jose.

  Visit our website at

IEEE CICC is sponsored by:

                               The IEEE Solid-     Technically co-sponsored
 The Institute of Electrical
                                State Circuits      by the Electron Devices
 and Electronic Engineers
                                   Society                  Society

Chairperson: Larry Nagel, Omega Enterprises

     Ed. Session 1 – Integrated Phase-Locked Systems –
                  Optimization and Trends
             Oak Ballroom, Sunday, September 10

Organizer: Mourad El-Gamal, McGill University
Co-Organizer: Payam Heydari, University of California, Irvine

8:00 – 9:50
E1-1      Fractional-N PLLs for Frequency Synthesis
          Ian Galton, University of California, San Diego

A brief review of integer-N PLLs will be presented, followed by a
detailed explanation of the additional ideas and issues associated with
the extension to fractional-N PLLs for frequency synthesis. Topics
include a self-contained explanation of the relevant aspects of ΔΣ
modulation; an extension of the well-known integer-N PLL loop design
methodology to fractional-N PLLs; non-ideal effects of particular
concern in fractional-N PLLs such as charge pump nonlinearities and
data-dependent divider delays; and techniques for wideband in-loop
digital modulation of the VCO. Case studies of example circuits and
applications are presented to illustrate the main concepts.

10:10 – 12:00
E1-2     Mixed-Signal Approaches for PLL Design and
         Michael Perrott, Massachusetts Institute of Technology

This talk investigates the use of modern design methods and mixed-
signal implementations of phase-locked loops to efficiently achieve
high performance designs. We begin with a historical overview of
frequency synthesizer architectures which includes integer-N,
fractional-N, and recently introduced "all-digital" architectures. Several
useful PLL CAD tools are then presented which allow efficient design
and simulation of the various synthesizer architectures presented.
With that background in place, we then examine several new mixed-
signal PLL architectures which include a high performance, mixed
analog/digital clock and data recovery circuit, a fractional-N based
DLL circuit, and an optical/electrical phase-locked loop.

1:00 – 2:50
E1-3      Noise Properties of VCOs in PLLs
          Ali Hajimiri, California Institute of Electrical Engineering

In this presentation we will discuss the noise properties of VCOs in a
phase locked looped due to internal and external noise sources. The
cyclostationary noise effects and their impact on the VCO design will
be discussed and we will investigate the effect of correlated noise and
methods of battling it inside PLLs.

3:10 – 5:00
E1-4      Device and Circuit Modeling for Phase-Locked Systems
          Behzad Razavi, University of California, Los Angeles

This presentation studies the behavior of passive devices such as
inductors and varactors and describes device models for accurate
prediction of the performance of oscillators. We also introduce
behavioral and transistor-level circuit modeling techniques for
frequency synthesizers and bang-bang PLLs to reduce the simulation

      Ed. Session 2 – Advanced RF Design Techniques
             Fir Ballroom, Sunday, September 10

Organizer: Kris Iniewski, University of Alberta
Co-Organizer: Kathleen Philips, Philips Research

8:00 – 9:50
E2-1      Circuit Design for Impulse and MB-OFDUM UWB
          Domine Leenaerts, Philips

Since the FCC opened up the spectrum for Ultra Wide Band (UWB)
operation in the 3.1 to 10.6GHz range, several standards have been
proposed to realize moderate and high rate short-range
communication systems. The moderate data rate systems (up to
200Mbps) use impulse transmission concepts. Here, a pulse with
short time duration (hence wide band in frequency) is used to code the
data. Analog correlation techniques with matched filters are deployed
to decode the received signals.

To achieve high data rates up to 480Mbps MB-OFDM UWB divides
the spectrum into QPSK-OFDM modulated sub-bands of 528MHz.
The mandatory mode of operation implements a frequency hopping
scheme in the three lower bands from 3.1GHz to 4.8GHz with a
transmit power below the FCC limit of –41.25dBm/MHz.

Impulse UWB as well as MB-OFDM UWB radios receive low signal
levels. This requires a low-noise receive chain, while the presence of
strong out-of-band interferers in the 2.4 and 5GHz bands and the
need for co-existence with systems operating in these bands mandate
a high linearity and selectivity to achieve robust high-rate data
transmission. While impulse UWB can be a carrier-less system in MB-
OFDM UWB, a frequency-hopping scheme is applied to achieve
efficient and robust communication. This scheme employs hopping
between the carrier frequencies of the lower three bands at 3432MHz,
3960MHz, and 4488MHz, with a period of 312.5ns. The frequency
synthesizer therefore switches between the carrier frequencies within
a maximum transition time of 9ns. The demands on the purity of the
generated carriers are very stringent.

The presentation will briefly discuss the system aspects of impulse-
based and MB-OFDM-based UWB communication and will discuss in
more detail the design aspects of needed circuitry to build up an UWB
radio transceiver. The presentation will also give an overview of UWB
circuits/systems proposed in literature.

10:10 – 12:00
E2-2     CMOS Building Blocks for Emerging RF Technologies
         Kris Iniewski, University of Alberta

The tutorial starts with definition of basic terms in RF and wireless
technologies: RF signal loss and detection limits, Shannon law,
modulation, coding, detection, and multiple user access techniques. It
provides a brief history of cellular telephony starting with Advanced
Mobile Phone System (AMPS) and ending with 3G services like Wide-
Band CDMA (W-CDMA), and discusses evolution of WLAN
technologies from 802.11a/b to 802.11.n. Emerging wireless access
(WiMAX/ 802.16) and medical services for in-vivo (Medical Implant
Communications Service - MICS) and in-vitro (Wireless Medical
Telemetry Service - WMTS) applications are described next.

A major focus of the tutorial is design of CMOS circuits for emerging
wireless technologies. The current R&D activity drives towards two
major application areas: high data rates towards Gb/s, and low-power
per device towards battery-free operation using energy scavenging. In
the first camp of higher data rate technologies, 802.11n, Ultra-Wide
Band/802.15.3 and 60 GHz MM-wave radios are compared. In the
second group, Bluetooth/IEEE 802.15.1 and ZigBee/IEEE 802.15.4,
which are already deployed in the marketplace, are compared against
newcomer UWB pulse radio/802.15.3.

Basic principles of operation, power dissipation levels and hardware
realization challenges in silicon are discussed. Low Noise Amplifiers
(LNA), mixers, filters, power amplifiers and Phase-Locked Loops
(PLLs) are described in a tutorial fashion. Prospects of building
devices that achieve Gb/s data rates, operate at mm-waves, or are
energy self-reliant are investigated from silicon point of view.

1:00 – 2:50
E2-3      Power Amplifier Design Techniques
          Mihai Banu, MHI Consulting

The recent proliferation of wireless applications in an expanding
consumer market has been a catalyst for substantial changes in the
radio technology. Great advances have been possible due to the
introduction of sophisticated solutions based on RFICs, DSPs, and
special mixed-signal ICs, which have successfully addressed the
signal processing needs of low-cost high-performance digital wireless
systems. However, the front end design of such systems, including the
power amplifier (PA), has seen a less dramatic evolution. Partially, this
is due to operation closer to the fundamental physical limits of wireless
transmission where there are less obvious opportunities for
innovation. In addition, conventional class-A or class-AB designs have
provided acceptable solutions for digital wireless systems with
constant envelope modulation, such as GSM.

As wireless systems evolve towards highly efficient bandwidth
utilization and very high data rates as in broad-band CDMA, WiMax,
etc., the use of complex modulation schemes with large peak-to-
average ratio (PAR) signals is mandatory. The conventional PA
design techniques become quite inadequate for such cases, mainly
due to very poor efficiency. This has serious repercussions in mobile
talk time, base station power requirements, etc.

In this lecture, we first review the principles of “power amplification”
from a general power conversion point of view, naturally leading to the
classical PA architectures. Then, we discuss system-type methods for
increasing the power efficiency, such as those based on the Doherty
principle, the drain modulation principle, or signal decomposition. The
advantages and deficiencies of these techniques will be discussed in

the context of modern IC implementations. In addition, we will present
a new optimum class-AB biasing scheme for fully integrated PA

3:10 – 5:00
E2-4      Technology-Aware ESD-Reliable RF CMOS Circuit
          Dimitri Linten, IMEC/Vrije Universiteit Brussels

Scaling of CMOS technology introduces reliability concerns for the
final product which must be resolved before the products go to the
market. For example, as the gate oxide thickness of the transistors
decreases with scaling, its breakdown voltage (BVox) also decreases.
The thinner gate oxide makes scaled technologies very susceptible to
Electro Static Discharge (ESD) failures.

Protecting the final product against ESD induced failures is a
challenging task, especially for RF applications. Products are even
being marketed without any ESD protection. Unlike in digital circuits,
implementing a suitable on-chip ESD protection for RF CMOS
applications requires simultaneously addressing the challenges posed
by design and technology limitations. For instance, a low-noise
amplifier (LNA) is one of the critical building blocks needed in any RF
front-end. It is connected to the outside world through an antenna or
an off-chip receive filter. Hence, it can easily be exposed to ESD
events. The challenge of implementing an ESD protection on the RF
input of the LNA is that it should not degrade the RF performance of
the LNA itself.

This lecture will review the key issues involved in designing ESD
reliable RF circuits in sub-90nm CMOS technologies and the impact of
technology options on ESD-reliable design. After an overview of ESD
test and standards, basic concepts of ESD protection devices will be
discussed. Even with good individual ESD components, a successful
full-chip ESD solution is neither automatically obtained, nor it is
straight-forward. An overview of commonly-used ESD protection
strategies will be presented and evaluated with on typical front-end
circuit, such as an LNA. Finally, an outlook will be provided towards
ESD-reliable design in the 45nm CMOS technology node.

  Ed. Session 3 – High-Performance and Low-Power Digital
                        Circuit Design
            Pine Ballroom, Sunday, September 10

Organizer: Amine Bermak, Hong Kong University of Science and
Co-Organizer: Lawrence Clark, Arizona State University

8:00 – 9:50
E3-1      Low-Power and Low-Voltage Circuit Technologies for
          Energy-Efficient DSP Design
          Ram Krishnamurthy, Intel Corporation

This tutorial examines some of the most prominent barriers to
designing energy-efficient DSP circuits in the sub-45nm CMOS
technology regime and outlines new paradigm shifts necessary in
next-generation DSP architectures. Emerging trends in wireless and

embedded          DSP       industry    including      special-purpose
multimedia/communication accelerators, co-processor arrays, and
reconfigurable DSP engines and their associated power-performance
trade-offs are reviewed. Energy-efficient arithmetic and logic circuit
techniques, static/dynamic supply scaling, low-voltage and ultra low-
voltage circuit techniques, and multi-supply/multi-threshold design for
switching and leakage energy reduction are described. Special
purpose hardware accelerators and data-path building blocks for
enabling high GOPS/Watt on specialized DSP tasks are presented.
Many chip design examples and their results/trade-offs will be
discussed as part of this tutorial.

10:10 – 12:00
E3-2     Clockless Circuits as Silent Digital Companions for
         Analog and RF
         Ad Peeters, Handshake Solutions

In clockless circuits, the centralized clock of synchronous design is
replaced by distributed handshake signaling, leading to circuits that
are active only when and where needed. Compared to synchronous
circuits, clockless circuits demonstrate a saving in energy
consumption, have lower current peaks, and greatly reduced
electromagnetic emission. These characteristics make clockless
circuit an ideal companion for analog and RF circuits when integrated
on the same die, in the same package, or in a product. Two major
roadblocks in clockless circuit technology have been the absence of
an integrated design flow and the lack of a satisfactory design-for-test
solution. The tutorial will focus on an approach that hides all the
clockless implementation details from the designers, thereby making
the potential benefits of clockless circuits available to non-specialists.
This approach is based on so-called handshake circuits, and is
supported by a set of tools that automatically handle all timing
assumptions and implementation aspects throughout the complete
design flow, from high level design entry down to layout. It includes a
design-for-test solution based on synchronous scan test. The tutorial
will address how this technology is implemented, which benefits this
brings, and how these benefits have been exploited in real products.

1:00 – 2:50
E3-3      Ultra Low Power/Voltage Design
          Jan Rabaey, University of California at Berkeley

Power concerns have been at the forefront for the last decade, yet
were always considered a second-order concern with respect to other
design metrics. Today however, few will dispute that CMOS has
entered the "power-limited scaling regime", with power dissipation
becoming the limiting factor on what can be integrated on a chip and
how fast it can run. Many approaches have been proposed to address
the concerns regarding both active and standby power. Yet none of
these provides a persistent answer enabling technology scaling to go
on in the foreseeable future. Fortunately, a number of researchers are
currently engaging in ultra-low power design (ULP), providing a
glimpse on potential innovative solutions as well as clear
showstoppers. In this talk, we will first present a perspective on power
roadmaps and challenges. We will present some of the solutions
currently being considered in the ULP community, and discuss their
pros and cons. As low-voltage memory is also a formidable challenge,
a substantial fraction of the presentation will focus on that topic. The
talk will conclude with some long-term perspectives.

3:10 – 5:00
E3-4      Variability, A Barrier to Further CMOS Scaling?
          Marcel J.M. Pelgrom, Philips

Circuit operation greatly depends on the ability to control and
reproduce transistor and process parameters, such as oxide
thickness, dielectric constants, doping levels, width and length.
Variation in processing was in the past countered by defining process
corners: boundaries in parameter variation that accounted for
remaining process tolerances. With the improved control over
processing, this batch-to-batch variation is largely under control.

However, now a new class of phenomena has appeared: intra-die
variability. In conventional ICs, analog circuits with a differential
operation (e.g. analog-to-digital converters) were already affected by
this parameter spread. The remaining variation between otherwise
identical components is generally described by “mismatch”
parameters. Next to this also mechanical and electrical stress, local
operating condition variations such as voltage and temperature and
interference (supply and substrate noise, cross-talk, etc.) are of major
importance to optimize circuit performance.

For a long period digital designers did not consider this intra-die
variability. However due to scaling, the margins in digital designs are
reduced. Also, the number of atoms involved in the local definition of
electrical parameters is reduced, thereby increasing the local
variability to a level where even the classical full-swing digital noise
margins are affected. While analog designers have the option to
spend area to implement correction circuits, digital designers have to
cope with these effects differently.

The tutorial will focus on mechanisms causing intra-die variations,
which originate from physical, electrical, thermal and interference
effects. Especially, the effects of jitter, mismatch and substrate noise
in digital circuits will be considered.

CICC once again combines its outstanding technical program with a
variety of exhibitors. Exhibits will include displays and demonstrations
by semiconductor manufacturers, software tool suppliers, design
service houses, and leading electronics industry publications. The
Exhibit Hall will be the site for Monday's Welcome Reception and
Tuesday evening's Happy Hour.

Donner Pass Ballroom
Monday, September 11
3:30 pm - 8:00 pm – Exhibits Open
5:30 pm - 8:00 pm Welcome Reception

Tuesday, September 20
3:30 pm - 7:30 pm – Exhibits Open
5:30 pm - 7:30 pm Happy Hour

   Monday, September 11 – Wednesday, September 13

              Session 1 – Keynote Presentation
          Oak Ballroom, Monday Morning, September 11

8:00 am       Welcome/Opening Remarks
              Awards Presentations
                  Best Invited Paper
                  A Digital Clock and Data Recovery Architecture for
                  Multi-Gigabit/s Binary Links, J. Sonntag and J. Stonick,
                  Synopsys, Inc., Hillsboro, OR

                  Best Regular Paper
                  An 8Mb 1T1C Ferroelectric Memory with Zero
                  Cancellation and Micro-Granularity Redundancy, J.
                  Eliason, S. Mandan*, H. McAdams*, G. Fox, T. Moise*,
                  C. Lin, K. Schwartz, J. Gallia*, E. Jabillo, B. Craus and
                  S. Summerfelt*, Ramtron International Corp., Colorado
                  Springs, CO, *Texas Instruments Inc., Dallas, TX
                  Best Student Paper

                  A Precision CMOS Amplifier using Floating-Gates for
                  Offset Cancellation, V. Srinivasan, G.J. Serrano, J.
                  Gray, and P. Hasler, Georgia Institute of Technology,
                  Atlanta, GA

              Keynote Speaker Introduction
              Henry Chang, General Chair

              The Evolution of Semiconductor Needs in Handsets
              Dr. Sanjay K. Jha, Executive Vice President of
              QUALCOMM Incorporated and President of
              QUALCOMM CDMA Technologies

Looking to the future of mobile devices, there
will be key applications that exponentially drive
the growth of this platform even beyond the
dramatic growth expected over the next few
years. There are many opportunities in the
wireless space, and as a leader of this
industry, QUALCOMM CDMA Technologies
(QCT) has a unique vision into what the future
holds. Technology coming to market today is
often called "3G," so what will 4G look like?
What types of groundbreaking services will be
possible, and how will the semiconductors
powering these next-generation devices need to evolve in order to
power the new functionality in a still-attractive form-factor? Dr. Sanjay
K. Jha, president of QCT, will explore the changing landscape of this
industry and explain the technology innovations necessary to bring
these visions of the future to reality.

              Session 2 – Advances in Analog and
                 Digital Programmable Devices
           Oak Ballroom, Monday Morning, September 11

        Chair: Steve Wilton            Co-Chair: Arif Rahman

Programmable devices provide a low-cost, low-risk path to
complex analog, digital, and mixed-signal implementations. This
session highlights circuit and architectural techniques that make
these devices possible.

10:00 am      Introduction

10:05 am      Low-Voltage Universal Cell (LVUC): A Compact
2.1           Analog/Digital Logic Block for Mixed Signal FPGAs,
              L. Kalyani-Garimella, A.Garimella, J. Ramirez-Angulo,
              R. Carvajal,     A. Lopez-Martin, New Mexico State
              University, Las Cruces, NM

10:30 am      A Large-Scale Reconfigurable Analog Signal
2.2           Processor (RASP) IC, C. Twigg, P. Hasler, Georgia
              Institute of Technology, Atlanta, GA

10:55 am      Determination of Power Gating Granularity for FPGA
2.3           Fabric, A. Rahman, S. Das, T. Tuan, and S.
              Trimberger, Xilinx Research Laboratories, San Jose, CA

11:20 am      Reconfigurable Asynchronous Logic (INVITED
2.4           PAPER), R. Manohar, Cornell University, Ithaca, NY

                    Session 3 – RF Techniques
           Fir Ballroom, Monday Morning, September 11

           Chair: John Rogers          Co-Chair: Ali Niknejad

This session explores advanced circuits techniques that address
timely issues such as working at extremely high frequencies and
at very low voltage. New topologies for LANs, oscillators, and
dividers will be presented.

10:00 am      Introduction

10:05 am      A 50-GHz Phase-Locked Loop in 130-nm CMOS, C.
3.1           Cao, Y. Ding and K. O, University of Florida,
              Gainesville, FL

10:30 am      Common Gate Transformer Feedback LNA in a High
3.2           IIP3 Current Mode RF CMOS Front-End, A. Liscidini,
              C. Ghezzi, E. Depaoli*, G. Albasini*, I. Bietti* and R.
              Castello, Universita degli Studi di Pavia, Pavia, Italy,
              *STMicroelectronics, Pavia, Italy

10:55 am      Passive & Active Control of Regenerative Standing
3.3           & Soliton Waves (INVITED PAPER), W. Andress, D.
              Ricketts, X. Li and D. Ham, Harvard University,
              Cambridge, MA

11:45 am      A    0.9-V    Double-Balanced    Quadrature-Input
3.4           Quadrature-Output Frequency Divider, H. Zheng and
              H. Luong, The Hong Kong University of Science and
              Technology, Hong Kong

               Session 4 – Delta-Sigma Converters
           Pine Ballroom, Monday Morning, September 11

      Chair: Kathleen Philips         Co-Chair: Don Thelen

The papers in this session discuss innovative circuits and
architectures advancing the performance of Delta-Sigma A/D

10:00 am      Introduction

10:05 am      Incremental Delta-Sigma Structures for DC
4.1           Measurement: an Overview (INVITED PAPER), J.
              Markus, P. Deval*, V. Quiquempoix*, J. Silva** and G.
              Temes**, University of Technology and Economics,
              budapest, Hungary, *Microchip Technology, Inc.,
              Chandler, AZ, **Oregon State University, Chandler, AZ

10:55 am      A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using
4.2           Pseudo-Differential Split-Path Cascode Amplifiers,
              Z. Cao, T. Song and S. Yan, The University of Texas at
              Austin, Austin, TX

11:20 am      A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ
4.3           ADC with a Triple Sampling Technique, Y.
              Kanazawa, Y. Fujimoto, P. Lo Ré and M. Miyamoto,
              Sharp Corporation, Nara, Japan

11:45 am      A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with
4.4           a Hybrid Active-Passive Loop Filter, T. Song, Z. Cao
              and S. Yan, The University of Texas at Austin, Austin,

           Session 5 – Measurement Techniques
                    for High Speed Signals
        Cedar Ballroom, Monday Morning, September 11

   Chair: Jeanne Trinko-Mechler         Co-Chair: Robert Aitken

On-chip signal digitization and capture at 70-GHz is presented in
the first paper. Next is offered a jitter and link characterization
tutorial which addresses standards such as PCI Express, Fibre
Channel, and Giga Bit Ethernet. A novel bus probing technique
based on electromagnetic couplers is presented in the third
paper. The session closes with an innovative circuit design which
allows a two order improvement in characterization accuracy of
the frequency response of on-chip continuous-time filters.

10:00 am      Introduction

10:05 am    A 70-GHz Effective Sampling Rate On-Chip
5.1         Oscilloscope with Time-Domain Digitization, M. Safi-
            Harb and G. Roberts, McGill University, Montreal,

10:30 am    Jitter And Signaling Test For High-Speed Links
5.2         (INVITED PAPER), M. Li, Wavecrest Corporation, San
            Jose, CA

11:20 am    A 8 Gb/s Electromagnetic Coupler Transceiver, T.
5.3         Hinck, J. Critchlow, T. Wig, J. Benham and L. Tate, Intel
            Corporation, Hudson, MA

11:45 am    A Technique for Accurate Frequency Response
5.4         Measurement of Integrated Continuous-Time Filters,
            S. Pavan and T. Laxminidhi, Indian Institute of
            Technology, Madras, India

    Session 6 – Power Optimized RF and Wireline SoCs
      Oak Ballroom, Monday Afternoon, September 11

     Chair: Aurangzeb Khan           Co-Chair: Rakesh Patel

The first four papers present software-assisted GSM radio RF
processing, 802.11 WLAN integration, multiprocessing and
integrated power management for wireless products. The next
four papers present SoCs with 6.375 Gb/s SerDes I/Os, 22.5 Gb/s
cross-current and a 10 Gb/s framer. A human-body network
processor with less than 30uW power, and a 15 dB SNR
substrate noise reduction for wireline networks.

1:30 pm     Introduction

1:35 pm     Software Assisted Digital RF Processor for Single-
6.1         Chip GSM Radio in 90 nm CMOS, R. Staszewski, T.
            Jung, B. Staszewski, K. Muhammad, D. Leipold, T.
            Murphy, S. Sabin, J. Wallberg, S. Larson, M. Entezari,
            J. Fresquez, S. Dondershine and S. Syed, Texas
            Instruments, Dallas, TX

2:00 pm     A Highly Integrated Power Management IC for
6.2         Advanced Mobile Applications, C. Shi, B. Walker, E.
            Zeisel, B. Hu and G. McAllister, Qualcomm Inc., San
            Diego, CA

2:25 pm     A Dual-Band Triple-Mode SoC for 802.11a/b/g
6.3         Embedded WLAN in 90nm CMOS, A. Shirvani, D.
            Cheung, R. Tsang, S. Jamal, T. Cho, X. Jin and Y.
            Song, Marvell Semiconductor, Santa Clara, CA

2:50 pm     Design and Implementation of a Reconfigurable
6.4         Heterogeneous Multiprocessor SoC, M. Bocchi, M.
            De Dominicis, C. Mucci, A. Deledda, F. Campi*, A. Lodi,
            M. Toma* and R. Guerrieri, University of Bologna,
            Bologna, Italy, *STMicroelectronics, Brianza, Italy

3:15 pm     BREAK

3:35 pm     Embedded Mixed-Signal IP Development Method-
6.5         ology in 90nm CMOS SerDes FPGAs, R. Patel and W.
            Bereza*, Altera Corp., San Jose, CA, *Kanata, Canada

4:00 pm     Integrated 155M-10Gbps Framer with 22.5Gbps
6.6         Low/High    Order    Cross     Connect     SoC,     K.
            Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. Kalari,
            J. Zhi, E. Ruetz, M. Gray, B. Reynov and A. Iqbal,
            Crimson Microsystems, Inc. Sunnyvale, CA

4:25 pm     Comparison and Impact of Substrate Noise
6.7         Generated by Clocked and Clockless Digital
            Circuitry, J. Le, C. Hanken, M. Held, M. Hagedorn, K.
            Mayaram and T. Fiez, Oregon State University,
            Corvallis, OR

4:50 pm     A Multi-Nodes Human Body Communication Sensor
6.8         Network Control Processor, S. Choi, S-J. Song, K.
            Sohn, H. Kim, J. Kim, N. Cho, J-H. Woo, J. Yoo and H-
            J. Yoo, KAIST, Daejeon, Korea

      Session 7 – Wireless Transmitter Building Blocks
        Fir Ballroom, Monday Afternoon, September 11

    Chair: Cicero Vaucher           Co-Chair: Payam Heydari

The session starts with an invited paper on low-power design
challenges, followed by advances in wireless transmitter building
blocks, including direct modulators, a wide-band VCO, and high-
efficiency PA techniques.

1:30 pm     Introduction

1:35 pm     Challenges in Designing Low-Power CMOS Wireless
7.1         Systems-on-a-Chip (INVITED PAPER), D. Su, Atheros
            Communications, Inc., Santa Clara, CA

2:25 pm     A 2.4GHz Direct Modulated 0.18µm CMOS IEEE
7.2         802.15.4 Compliant Transmitter for ZigBee, S. Beyer,
            R. Jaehne, W. Kluge, D. Eggert, Atmel, Dresden,

2:50 pm     A Wideband ΔΣ Digital-RF Modulator With Self-
7.3         Tuned RF Bandpass Reconstruction Filter, A. Jerng
            and C. Sodini, Massachusetts Institute of Technology,
            Cambridge, MA

3:15 pm     BREAK

3:35 pm     Quad Band Digitally Controlled Oscillator for
7.4         WCDMA Transmitter in 90nm CMOS, S. Akhtar, M.
            Ipek, J. Lin, R. Staszewski and P. Litmanen, Texas
            Instruments, Inc., Dallas, TX

4:00 pm     Low-Power CMOS IEEE 802.11a/g Signal Separator
7.5         for Outphasing Transmitter, L. Panseri, L. Romanò, S.
            Levantino, C. Samori and A. Lacaita, Politecnico di
            Milano, Milan, Italy

4:25 pm       A Novel DAC Based Switching Power Amplifier for
7.6           Polar Transmitter, A. Shameli, A. Safarian, A.
              Rofougaran*, M. Rofougaran* and F. De Flaviis,
              University of California, Irvine, CA, *Broadcom
              Corporation, Irvine, CA

4:50 pm       A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power
7.7           Amplifier with Efficiency Enhancement, G. Liu, T-J.
              Liu and A. Niknejad, University of California, Berkeley,

                    Session 8 – D/A Converters
          Pine Ballroom, Monday Afternoon, September 11

     Chair: Yun Chiu              Co-Chair: L. Richard Carley

This session covers DACs from an oversampled one with >100dB
DR to a 90nm CMOS one clocked at 1GHz, and addresses
proximity effects in sub-100nm CMOS.

1:30 pm       Introduction

1:35 pm       A 4mW per-Channel 101dB-DR Stereo Audio DAC
8.1           with Transformed Quantization Structure, Y-H. Lee,
              M-Y. Choi, S-B. You, W-S. Yeum, H-J. Park and J-W.
              Kim, Samsung Electronics, Co., Ltd., Gyeonggi-Do,

2:00 pm       Design of a Binary-Weighted Resistor DAC Using
8.2           Tunable Linearized Floating-Gate CMOS Resistors,
              E. Ozalevli, H. Dinc, H-J. Lo and P. Hasler, Georgia
              Institute of Technology, Atlanta, GA

2:25 pm       Low Power Approaches To High Speed CMOS
8.3           Current Steering DACs (INVITED PAPER), D. Mercer,
              Analog Devices Inc., Wilmington, MA

2:50 pm       An Area Optimized 2.5-V 10-b 200-MS/s 200-uA
8.4           CMOS DAC, B. Nejati and L. Larson*, Sequoia
              Communications, San Diego, CA, *University of
              California San Diego, La Jolla, CA

3:15 pm       BREAK

3:35 pm       A 10-bit 1GSample/s DAC in 90nm CMOS for
8.5           Embedded Applications, J. Cao, H. Lin, Y. Xiang, C.
              Kao and K. Dyer*, KT Micro, Inc., Rancho Santa
              Margarita, CA, *Keyeye Communications, Sacremento,

4:00 pm       Implications of Proximity Effects for Analog Design
8.6           (INVITED PAPER), P. Drennan, M. Kniffin and D.
              Locascio, Freescale Semiconductor, Tempe, AZ

      Session 9 – Advanced Analog Verification Technique
        Cedar Ballroom, Monday Afternoon, September 11

         Chair: Larry Nagel       Co-Chair: Hong Ha Vuong

This session addresses new modeling and circuit verification
techniques that are required for the design of increasingly
complex, sophisticated, and mainly analog portions of VLSI
integrated circuits.

1:30 pm       Introduction

1:35 pm       Verification of Complex Analog Integrated Circuits
9.1           (INVITED PAPER), K. Kundert and H. Chang,
              Designer's Guide Consulting, Inc., Sunnyvale, CA

2:25 pm       On-the-Fly Fidelity Assessment for Trajectory-
9.2           Based Circuit Macromodels, S. Tiwary and R.
              Rutenbar, Carnegie Mellon University, Pittsburgh, PA

2:50 pm       Predictive Modeling of the NBTI Effect for Reliable
9.3           Design, S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao
              and S. Vrudhula, Arizona State University, Tempe, AZ

3:15 pm       BREAK

3:35 pm       Modeling, Design, and Verification for the Analog
9.4           Front-end of a MEMS-based Parallel Scanning-probe
              Storage Device, C. Hagleitner, T. Bonaccio*, H.
              Rothuizen, D. Wiesmann, J. Lienemann, J. Korvink**, G.
              Cherubini and E. Eleftheriou, IBM Zurich Research Lab,
              Ruschlikon, Switzerland, *IBM Systems & Technology
              Group, Burlington, VT, **University of Freiburg,
              Freiburg, Germany

4:00 pm       Modeling Op Amp Nonlinearity in Switched-
9.5           Capacitor Sigma-Delta Modulators, K. Abdelfattah
              and B. Razavi, University of California, Los Angeles, CA

4:25 pm       Rapid Simulation of Current Steering Digital-to-
9.6           Analog      Converters    using Verilog-A,     M.
              Shanmugasundaram and S. Pavan, Indian Institute of
              technology, Madras, India

                          Poster Session
      Cascade/Sierra Ballroom, Monday Evening, September 11
                         5:00 pm – 7:00 pm

P.1           A Phase-Domain Continuous-Time 2nd-Order ΔΣ
              Frequency Digitizer, M. Sharifkhani and M. Sachdev,
              University of Waterloo, Waterloo, Canada

P.2           A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with
              Digital Background Calibration, Z-M. Lee, C-Y. Wang
              and J-T. Wu, National Chiao-Tung University, Taiwan,

P.3    A Low 1/f Noise CMOS Low-Dropout Regulator with
       Current-Mode Feedback Buffer Amplifier, W. Oh, B.
       Bakkaloglu, B. Aravind* and S. K. Hoon*, Arizona
       State University, Tempe, AZ, *Texas Instruments,
       Dallas, TX

P.4    10-b 100-MS/s Two-Channel Time-Interleaved
       Pipelined ADC, K. El-Sankary and M. Sawan,
       University of Montreal, Montreal, Canada

P.5    A 20 GS/sec Analog-to-Digital Sigma-Delta
       Modulator in SiGe HBT Technology, X. Li, W.-M.
       Kuo, Y. Lu and J. Cressler, Georgia Institute of
       Technology, Atlanta, GA

P.6    A 300 C, 110-dB Sigma-Delta Modulator with
       Programmable Gain in Bulk CMOS, X.Yu and S.
       Garverick,    Case Western Reserve University,
       Cleveland, OH

P.7    A 0.18µm CMOS 1000 Frames/sec, 138dB Dynamic
       Range Readout Circuit for 3D-IC IR Focal Plane
       Arrays, S. Kavusi, K. Ghosh, K. Fife and A. El Gamal,
       Stanford University, Stanford, CA

P.8    ViPro: Focal-Plane Spatially-Oversampling CMOS
       Image Compression Sensor, A. Olyaei and R. Genov,
       University of Toronto, Toronto, Canada

P.9    Prediction and Characterization of Frequency
       Dependent MOS Switch Linearity and the Design
       Implications, T. Brown, M. Hakkarainen* and T. Fiez,
       Oregon State University, Corvallis, OR, *Maxim
       Integrated Products, West Palm Beach, FL

P.10   1.56 GHz On-chip Resonant Clocking in 130nm
       CMOS, M. Hansson, B. Mesgarzadeh and A.
       Alvandpour, Linkoping University, Linkoping, Sweden

P.11   Low-Ripple CMOS Switched-Capacitor Power
       Converter       With     Closed-Loop Interleaving
       Regulation, M. Somasundaram and D. Ma, The
       University of Arizona, Tuscon, AZ

P.12   A Low Power ASK Clock and Data Recovery Circuit
       for Wireless Implantable Electronics, H. Yu and R.
       Bashirullah, University of Florida, Gainesville, FL

P.13   An Efficient Adaptive Digital DC-DC Converter with
       Dual Loop Controls for Fast Dynamic Voltage
       Scaling, J. Song, G. Yoon and C. Kim, Korea
       University, Seoul, Korea

P.14   A Floating-Gate Based Low-Power Capacitive
       Sensing Interface Circuit, S.-Y. Peng, M. Qureshi, A.
       Basu, P. Hasler and L. Degertekin, Georgia Institute of
       Technology, Atlanta, GA

P.15   PulseNet -- A Parallel Flash Sampler and Digital
       Processor IC for Optical SETI, A. Howard, G-Y. Wei,
       W. Dally* and P. Horowitz, Harvard University,
       Cambridge, MA, *Stanford University, Stanford, CA

P.16   A 32Gb/s On-chip Bus with Driver Pre-eEmphasis
       Signaling, L. Zhang, J. Wilson, R. Bashirullah*, L. Luo,
       J. Xu and P. Franzon, North Carolina State University,
       Raleigh, NC, *University of Florida, Gainesville, FL

P.17   An Integrated 90V Switch Array for Medical
       Ultrasound Applications, Y-M. Li, R. Wodnicki* N.
       Chandra* and N. Rao*, Intersil, Irvine, CA, *GE Global
       Research, Niskayun, NY

P.18   Towards a Wearable Electronic Nose Chip, K-T.
       Tang and R. Goodman*, National Tsing Hua University,
       Taiwan, ROC, *InfinID Technologies Inc.

P.19   A 1V 420uW 32-Channel Cortical Signal Interface, E.
       Lee, E. Matei, A. Lam and T. Li, Alfred Mann
       Foundation, Santa Clarita, CA

P.20   A 3D Multi-Aperture Image Sensor Architecture, K.
       Fife, A. El Gamal and H.-S. P. Wong, Stanford
       University, Stanford, CA

P.21   GHz Serial Passive Clock Distribution in VLSI Using
       Bidirectional Signaling, V. Prodanov and M. Banu,
       MHI Consulting, NJ

P.22   A Driving Scheme for AMOLED Displays Based on
       Current Feedback, S. Ashtiani         and A. Nathan,
       University of Waterloo, Waterloo, Canada

P.23   Efficient Far-Field Radio Frequency Power
       Conversion System for Passively Powered Sensor
       Networks, T. Le, K. Mayaram and T. Fiez, Oregon
       State University, Corvallis, OR

P.24   Match Line Sense Amplifiers with Positive Feedback
       for Low-Power Content Addressable Memories, N.
       Mohan, W. Fung, D. Wright and M. Sachdev, University
       of Waterloo, Ontario, Canada

P.25   A Soft-Error Tolerant Content-Addressable Memory
       (CAM) Using An Error-Correcting-Match Scheme, K.
       Pagiamtzis, N. Azizi and F. Najm, University of Toronto,
       Toronto, Canada

P.26   180nm 4Mb High Speed High Reliability Embedded
       SONOS Flash Memory, L. Pan, D. Wu, G. Yang, L.
       Sun, H. Pang and J. Zhu, Tsinghua University, Beijing,

P.27   A Low-Power Routing Archictecture Optimized for
       Deep Sub-Micron FPGAs, L. Ciccarelli, D. Loparco*,
       M. Innocenti*, A. Lodi*, C. Mucci* and P. Rolandi,
       STMicroelectronics, Brianza, Italy, *University of
       Bologna, Bologna, Italy

P.28   A 0.13 µm Low-Power Race-Free Programmable
       Logic Array, G. Samson and L. Clark, Arizona State
       University, Tempe, AZ

P.29   An Energy Scalable Computational Array for Sensor
       Signal Processing, L. Guo, M. Scott and R.
       Amirtharajah, University of California, Davis, CA

P.30   Nonlinear Soft-Output Signal Detector Design and
       Implementation for MIMO Communication Systems
       with High Spectral Efficiency, S. Chen, F. Sun and T.
       Zhang, Rensselaer Polytechnic Institute, Troy, NY

P.31   VLSI Design of High-Rate Quasi-Cyclic LDPC Codes
       for Magnetic Recording Channel, H. Zhong, T. Zhang
       and E. Haratsch*, Rensselaer Polytechnic Institute,
       *Agere Systems, Allentown, PA

P.32   A CMOS Image Sensor with Combined Adaptive-
       Quantization and QTD-Based On-Chip Compression
       Processor, S. Chen, A. Bermak, Y. Wang and D.
       Martinez*, Hong Kong University of Science and
       Technology, Hong Kong, *LORIA-CNRS, Vandoeuvre-
       Les-Nancy, France

P.33   Considerations for Accurate Behavioral Modeling of
       High-Speed SC ΣΔ Modulators, G. Suarez and M.
       Jimenez, University of Puerto Rico, Mayaguez, Puerto

P.34   Width Quantization Aware FinFET Circuit Design, J.
       Gu, J. Keane, S. Sapatnekar and C. Kim, University of
       Minnesota, Minneapolis, MN

P.35   Concurrent Design of Delta-Sigma Modulator Using
       Behavioral Modeling and Simulation with the
       Verilog-A, T. Yamamoto, T. Suzuki and H. Asai,
       Shizuoka University, Hamamatsu-shi, Japan

P.36   IO Clock Network Skew & Performance Analysis: A
       Pentium-D Case Study, V. Bhargava, N. Haider and N.
       Sarpotdar, Intel Corporation, Santa Clara, CA

P.37   Nonlinear Phase-Macromodel-Based Simulation/
       Design of PLLs with Superharmonically Locked
       Dividers, S. Srivastava, X. Lai and J. Roychowdhury,
       University of Minnesota, Minneapolis, MN

P.38   The Backward-Traversing Relaxation Algorithm for
       Circuit Simulation, C-J. Chen, T-N. Yang and J-D.
       Sun, Chinese Culture University, Taiwan, ROC

P.39   Yield and Cost Modeling for 3D Chip Stack
       Technologies, P. Mercier, S. Singh, K. Iniewski, B.
       Moore and P. O'Shea, University of Alberta, Edmonton,

P.40   On-Chip Transient Detection Circuit for System-
       Level ESD Protection in CMOS ICs, M-D. Ker, C-C.
       Yen and P-C. Shih, National Chiao-Tung University,
       Taiwan, ROC

P.41   CMOS Mixed-Signal Circuit Process Variation
       Sensitivity Characterization for Yield Improvement,
       D. Kim, C. Cho, J. Kim, J-O. Plouchart, R. Trzcinski and
       D.    Ahlgren, IBM Semiconductor Research and
       Development Center, Hopewell Junction, NY

P.42   In Situ Evaluation Method for On-Chip Inductors
       Using Oscillator Response, M. Motoyoshi and M.
       Fujishima, The University of Tokyo, Tokyo, Japan

P.43   A Quadrature Demodulator for WCDMA Receiver
       Using Common-Base Input Stage with Robustness
       to Transmitter Leakage, T. Mitomo, O. Watanabe, R.
       Fujimoto* and S. Kawaguchi*, Toshiba Corporation,
       Kawasaki, Japan, *Toshiba Corporation, Yokohama,

P.44   A 3.8-5.5-GHz Multi-Band CMOS Frequency
       Synthesizer for WPAN/WLAN Applications, J. Y. Lee,
       K. Kim, J. Kwon, S-C. Lee, J. Kim, S-H. Lee, ETRI,

P.45   Inductor- and Transformer-based Integrated RF
       Oscillators: A Comparative Study, H. Krishnaswamy
       and H. Hashemi, University of Southern California, Los
       Angeles, CA

P.46   An 8-mW, ESD-protected, CMOS LNA for Ultra-
       Wideband Applications, K. Bhatia, S. Hyvonen and E.
       Rosenbaum, University of Illinois at Urbana-Champaign,
       Urbana, IL

P.47   X/Ku Band CMOS LNA Design Techniques, B. Afshar
       and A. Niknejad, University of California, Berkeley, CA

P.48   A 60GHz Phased Array in CMOS, S. Alalusi* and R.
       Brodersen, University of California, Berkeley, CA, *HRL
       Laboratories, Malibu, CA

P.49   A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in
       90nm CMOS Technology, C. Lee, L-C. Cho and S-L.
       Liu, National Taiwan University, Tiapei, Taiwan

P.50   A Multi-Standard Low Power 1.5-3.125Gb/s Serial
       Transceiver in 90nm CMOS, D. Yokoyama-Martin, K.
       Krishna, J. Stonick, A. Caffee, E. Kolet Gamble, C.
       Jones, J. McNeal, J. Parker, R. Segelken, J. Sonntag*,
       K. Umino, J. Upton, D. Weinlader and S. Wolfer,
       Synopsys, Inc., *Silicon Laboratories

P.51   FEXT Crosstalk Cancellation for High-Speed Serial
       Link Design, K.-J. Sham, M. Ahmadi, S.
       Bommalingaiahnapallya, G. Talbot* and R. Harjani,
       University of Minnesota, Minneapolis, MN, *AMD Boston
       Design Center, Boxborough, MA

P.52           A Low-Jitter Added SSCG with Seamless Phase
               Selection and Fast AFC for 3rd Generation Serial-
               ATA, J. Shin, I. Seo, J.Y. Kim, S.-H. Yang, C. Kim, J.
               Pak, H. Kim, M. Kwak and G.B. Hong, Samsung
               Electronics, Kiheung, Korea

P.53           A 5Gb/s Transmitter with Reflection Cancellation for
               Backplane Transceivers, R. Yuen, M. van Ierssel, A.
               Sheikholeslami, W.     Walker* and H. Tamura**,
               University of Toronto, Toronto, Canada, *Fujitsu
               Laboratories of America, **Fujitsu Laboratories, Ltd.,
               Kawasaki, Japan

P.54           Phase Mismatch Detection and Compensation for
               PLL/DLL Based Multi-Phase Clock Generator, A.
               Tan and G-Y. Wei, Harvard University, Cambridge, MA

                Session 10 – Advanced Memories
           Oak Ballroom, Tuesday Morning, September 12

       Chair: Phil Diodato        Co-Chair: Jean-Christophe Vial

Next generation DRAM technology and FIN-FET SRAMs are
presented. Exhaustive SER analysis and low cost test methods
are described. CAM design techniques are highlighted.

8:00 am        Introduction

8:05 am        Device Technology for Embedded DRAM Utilizing
10.1           Stacked MIM (Metal-Insulator-Metal) (INVITED
               PAPER) Capacitor, Y.     Yamagata, H. Shirai, H.
               Sugimura, S. Arai, T. Wake, K. Inoue, T. Sakoh, M.
               Sakao, and T. Tanigawa, NEC Electronics Corporation,
               Kanagawa, Japan

8:55 am                       2
               A Scalable ET RAM (SETRAM) with Verify Control
10.2           for SoC Platform Memory IP on SOI, K. Arimoto, F.
               Morishita, I. Hayashi, T. Tanizaki, T. Ipposhi, and K.
               Dosaka, Renesas Technology Corporation, Hyogo,

9:20 am        Optimization Of Surface Orientation For High-
10.3           Performance, Low-Power And Robust FinFET
               SRAM, S. Gangwal, S. Mukhopadhyay, and K. Roy,
               Purdue University, West Lafayette, IN

9:45 am        BREAK

10:00 am       Spreading Diversity in Multi-Cell Neutron-Induced
10.4           Upsets with Device Scaling (INVITED PAPER), E.
               Ibe, S. Chung*, S. Wen*, H. Yamaguchi, Y. Yahagi, H.
               Kameyama**, S. Yamamoto***, and T. Akioka**, Hitachi,
               Ltd., Kanagawa, Japan, *Cisco Systems, Inc., San Jose,
               CA, **Renesas Technology Corp., Tokyo, Japan,
               ***Renesas Technology Corp., Hyogo, Japan

10:50 am     Low Cost Test of High Bandwidth Embedded
10.5         Memories (INVITED PAPER), K. Gorman, D. Anand,
             G. Pomichter and W. Corbin, IBM Systems and
             Technology Group, Essex Junction, VT

11:15 am     High-Temperature, High Reliability EEPROM Design
10.6         For Automotive Applications, J. Walsh and G. Scott,
             AMI Semiconductor, Pocatello, ID

11:40 am     Self-Referenced Sense Amplifier for Across-Chip-
10.7         Variation Immune Sensing in High-Performance
             Content Addressable Memories, I. Arsovski and R.
             Wistort, IBM Silicon Solutions, Essex Junction, VT

              Session 11 – Emerging Technologies:
                      Materials and Structures
           Fir Ballroom, Tuesday Morning, September 12

      Chair: Dawn Fitzgerald    Co-Chair: Mourad El-Gamal

This session focuses on emerging materials and structures
including microfluid platforms for DNA detection, antennas used
for communications on chip, carbon nanotubes forming an
innovative memory and MEMS structures integrated for leakage

8:00 am      Introduction

8:05 am      Integrated MEMS Switches for Leakage Control of
11.1         Battery Operated Systems, A. Raychowdhury, J. Kim,
             D. Peroulis and K. Roy, Purdue University, West
             Lafayette, IN

8:30 am      CNT Based Mechanical Devices for ULSI Memory
11.2         (INVITED PAPER), J. Jang, S. Cha, Y. Choi, D. Kang*,
             T. Butler, D. Hasko, J. Kim** and G. Amaratunga,
             University   of     Cambridge,     Cambridge,   UK,
             *Sungkyunkwan University, Suwon, Korea, Samsung
             Advanced Institute of Technology, Yongin, Korea

8:55 am      Nucleic Acid Extraction, Amplification, and
11.3         Detection on Si-based Microfluidic Platforms
             (INVITED PAPER), L. Yobas, H-M. Ji, W-C. Hui, Y.
             Chen, T-M. Lim*, C-K. Heng* and D-L. Kwong, Insitute
             of Microelectronics, Singapore, *National University of
             Singapore, Singapore

9:20 am      Silicon Integrated Circuits Incorporating Antennas
11.4         (INVITED PAPER), K. O, K. Kim, B. Floyd, J. Mehta, H.
             Yoon, C-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li,
             N. Trichy, J. Caserta, W. Bomstad, J. Branch and D-J.
             Yang, University of Florida, Gainesville, FL

9:45 am      BREAK

     Session 12 – Nyquist Analog-to-Digital Converters
       Pine Ballroom, Tuesday Morning, September 12

          Chair: David Nairn        Co-Chair: Takahiro Miki

Nyquist analog-to-digital converters continue to push the
accuracy, speed and low-power boundaries by exploiting circuit
techniques and newer processing technologies.

8:00 am       Introduction

8:05 am       Frequency-Based Measurement of Mismatches
12.1          Between Small Capacitors, A. Verma and B. Razavi,
              University of California, Los Angeles, CA

8:30 am       A Calibration-Free 14b 70MS/s 3.3mm2 235mW
12.2          0.13µm CMOS Pipeline ADC with High-Matching 3-D
              Symmetric Capacitors, Y-J. Cho, K-H. Lee, H-C. Choi,
              S-H. Lee, K-H. Moon* and J-W. Kim*, Sogang
              University, Seoul, Korea, *Samsung Electronics Co.,
              Ltd., Gyeonggi-Do, Korea

8:55 am       A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS, S. Park,
12.3          Y. Palaskas*, A. Ravi*, R. Bishop* and M. Flynn,
              University of Michigan, Ann Arbor, MI, *Intel Corporatio,
              Hillsboro, OR

9:20 am       A 30-GS/sec Track and Hold Amplifier in 0.13-µm
12.4          CMOS Technology, S. Shahramian, S. Voinigescu and
              A. Chan Carusone, University of Toronto, Toronto,

9:45 am       BREAK

10:00 am      A 10b 25MS/s 4.8mW 0.13µm CMOS ADC for Digital
12.5          Multimedia Broadcasting Applications, Y-J. Cho, D-
              H. Sa, Y-W. Kim, K-H. Lee, H-C. Choi, S-H. Lee, Y-D.
              Jeon*, S-C. Lee* and J-K. Kwon*, Sogang University,
              Seoul, Korea, *ETRI, Daejeon, Korea

10:25 am      A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined
12.6          A/D Converters, T. Ueno, T. Ito, D. Kurose, T. Yamaji
              and T. Itakura, Toshiba Corporation, Kawasaki, Japan

10:50 am      Low-Power Design of Pipeline A/D Converters
12.7          (INVITED PAPER), S. Kawahito, Shizuoka University,
              Hamamatsu, Japan

11:40 am      A 1.8-V 22-mW 10-bit 30-MS/s Subsampling
12.8          Pipelined CMOS ADC, J. Li, X. Zeng, L. Xie, J. Chen,
              J. Zhang and Y. Guo*, Fudan University, Shanghai,
              China, *Shanghai MicroScience Integrated Circuits Co.,
              Ltd., Shanghai, China

            Session 13 – Signal and Data Processing
          Cedar Ballroom, Tuesday Morning, September 12

Chair: Bryan Ackland            Co-Chair: Ravi Kolagotla

Mobile computing and communications are primary market drivers
for today’s integrated circuit technology. Papers describe novel
techniques for providing improved communications and
application signal processing capability while maintaining low
power consumption.

8:00 am       Introduction

8:05 am       Digital Signal Processing for RF at 45-nm CMOS and
13.1          Beyond (INVITED PAPER), B. Staszewski, K.
              Muhammad and D. Leipold, Texas Instruments, Dallas,

8:55 am       Delta-Sigma Modulation in Direct Digital Frequency
13.2          Synthesis, D. Yang, W. Ni*, F. Dai, Y. Shi* and R..
              Jaeger, Auburn University, Auburn, AL, *Chinese
              Academy of Sciences, China

9:20 am       OFDM Modulator With Digital IF and On-Chip D/A-
13.3          Converter, J. Lindeberg, O. Väänänen,           J.
              Pirkkalaniemi, M. Kosunen and K. Halonen, Helsinki
              University of Technology, Espoo, Finland

9:45 am       BREAK

10:00 am      Neuromorphic       Vision    Systems  for    Mobile
13.4          Applications (INVITED PAPER), R. Etienne-
              Cummings, S. Mehta, R. Philipp and V. Gruev*, Johns
              Hopkins University, Baltimore, MD, *University of
              Pennsylvania, Philadelphia, PA

10:25 am      A Low-Power Unified Arithmetic Unit for
13.5          Programmable Handheld 3-D Graphics Systems, B-
              G. Nam, H Kim and H-J. Yoo, KAIST, Daejon, Korea

10:50 am      A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor
13.6          with Advanced NLMS Receiver and Receive
              Diversity for Mobile Terminals, C. Thomas, M. Cooke,
              O. Ridler, K. Van Den Beld, D. Yip, U. Sontowski, A.
              Kind, G. Zhou, Y-C. Li, L. Ung, R. Banna, B. Widdup, T.
              Prokop, M. Bickerstaff, G. Woodward, R. Srikantiah*, K.
              Gupta*, R. Reddy*, S. Arvapalli*, R. Bidnur*, P. Avss*,
              R. Lang, C. Nicol, Agere Systems, North Ryde,
              Australia, *Agere Systems, Bangalore, India

11:15am       A GFLOPS Vector-DSP for Broadband Wireless
13.7          Applications, E. Matus, H. Seidel, T. Limberg, P.
              Robelly and G. Fettweis, Dresden University of
              Technology, Dresden, Germany

           Session 14 – Design for Test and Reliability
           Fir Ballroom, Tuesday Morning, September 12

     Chair: Hamid Mahmoodi            Co-Chair: Kenichi Osada

Architecting reliability is the focus of the first two invited papers,
followed by a paper on capturing supply noise, another on at-
speed structural test, concluding with a paper on improving EM-
robustness in inductors.

9:55 am       Introduction

10:00 am      SRAMs in Scaled Technologies Under Process
14.1          Variations: Failure Mechanisms, Test and Variation
              Tolerant Design (INVITED PAPER), S. Mukho-
              padhyay, A. Agarwal, Q. Chen and K. Roy, Purdue
              University, West Lafayette, IN

10:25 am      The UltraSPARC T1 Processor: CMT Reliability
14.2          (INVITED PAPER), A. Leon, B. Langley and J. Shin,
              Sun Microsystems Inc., Sunnyvale, CA

10:50 am      A Time-Slicing Ring Oscillator for Capturing
14.3          Instantaneous Delay Degradation and Power Supply
              Voltage Drop, T. Sato, Y. Matsumoto, K. Hirakimoto, M.
              Komoda and J. Mano, Renesas Technology
              Corporation, Tokyo, Japan

11:15 am      Design For At-Speed Structural Test And
14.4          Performance Verification Of High-Performance
              ASICs, V. Iyengar, M. Johnson, T. Anemikos, G.
              Grise, M. Taylor, R. Farmer, F. Woytowich and B.
              Bassett, IBM Microelectronics, Essex Junction, VT

11:40 am      Robust Inductor Design for RF Circuits, Y-L. Lu, Y-H.
14.5          Lee, W. McMahon and T-C. Fung, Intel Corporation,
              Santa Clara, CA

                           CICC Luncheon
              Sierra Ballroom, Tuesday, September 12
                           12:00 – 1:30 pm

12:00 pm      Seating for Lunch

12:35 pm      Welcome and Introduction of Speaker
              Larry Wissel, Conference Chair

12:40 pm      Luncheon Presentation: From Rocks to Chips: A
              Rambling History of the Integrated Circuit, Professor
              Tom Lee, Stanford University, Stanford, CA

Electrical engineers are not good historians. For example, few know
anything about Ohm except that he created some law (which we
routinely violate). Similarly, few IC designers know that the PN
junction was a discovery (aided by a pair of well-trained noses), not an
invention; or that the first diodes -- made out of rocks dug out of the
ground -- were described in 1874.

Rather than the truncated, linearized
history presented in universities, this
talk will trace the evolution of the IC
from its humble, sporadic origins, to
today's gigascale chips. The talk will
conclude with speculations about the
future of the integrated circuit, now that
we are allegedly approaching the post-
Moore's law era.

Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical
engineering from MIT in 1983, 1985, and 1990, respectively. He has
worked at Analog Devices, Rambus, and AMD before joining the
Electrical Engineering faculty at Stanford University. His Stanford
research focus has been on gigahertz-speed wireline and wireless
integrated circuits built in conventional silicon technologies,
particularly CMOS. He has received Best Paper awards at ISSCC
(twice) and CICC, and is a Packard Foundation Fellowship recipient.
He is an IEEE Distinguished Lecturer of both the Solid-State Circuits
and Microwave Societies. He holds 35 U.S. patents and has authored
six books on RF circuit design, and has also co-founded Matrix

1:20 pm       Introduction of the Technical Program Chair for
              CICC 2007, Larry Wissel, Conference Chair

      Session 15 – SoC/SiP 3-D Power/Signal Transport
             And MEMS/Sensors Management
       Oak Ballroom, Tuesday Afternoon, September 12

          Chair: Paul Billig         Co-Chair: Ric Williams

Novel techniques for SoC/SiP are presented which include
wireless power transmission and high density through die vias for
SiP, a photo diode interface for automotive, and a high voltage
generator for MEMS.

2:00 pm       Introduction

2:05 pm       Chip-to-Chip      Inductive        Wireless    Power
15.1          Transmission System for SiP Applications, K.
              Onizuka, H. Kawaguchi*, M. Takamiya, T. Kuroda** and
              T. Sakurai, University of Tokyo, Tokyo, Japan, *Kobe
              Univ., Kobe, Japan, **Keio Univ., Yokohama, Japan

2:30 pm       Balanced Low Noise High Dynamic Photodiode
15.2          Interface for Automotive, I. Koudar, AMIS Mixed
              Signal Design Center, Brno, Czech Republic

2:55 pm       On-chip Digitally Tunable High Voltage Generator
15.3          for Electrostatic Control of Micromechanical
              Devices, L. Aaltonen, M. Saukoski and K. Halonen,
              Helsinki University of Technology, Finland

3:20 pm       Die Stacking Technology for Terabit Chip-to-Chip
15.4          Communications, A. Rahman, J. Trezza*, B. New, and
              S. Trimberger, Xilinz Research Lab, San Jose, CA,
              *Cublic Wafer, Inc., Merrimack, NH

3:45 pm       BREAK

               Session 16 – Eye-Opening Circuits
          Fir Ballroom, Tuesday Afternoon, September 12

    Chair:Tony Chan Carusone              Co-Chair: Jafar Savoj

This session focuses on CMOS wireline transceiver building
blocks. A tutorial on transmit equalization and two novel clock
and data recovery architectures are described.

2:00 pm       Introduction

2:05 pm       Wireline Equalization Using Pulse-Width Modulation
16.1          (INVITED PAPER), J. Schrader, E. Klumperink, J.
              Visschers* and B. Nauta, University of Twente,
              Enschede, The Netherlands, *NIKHEF, Amsterdam, The

2:55 pm       A 10Gbps Burst-Mode CDR Circuit in 0.18µm CMOS,
16.2          C-F. Liang, S-C. Hwu and S-I. Liu, National Taiwan
              University, Taipei, Taiwan, ROC

3:20 pm     A 1.6Gbps Digital Clock and Data Recovery Circuit,
16.3        P. Hanumolu, M. Kim, G-Y. Wei* and U-K. Moon,
            Oregon State University, Corvallis, OR, *Harvard
            University, Cambridge, MA

3:45 pm     BREAK

              Session 17 – Analog Techniques
       Pine Ballroom, Tuesday Afternoon, September 12

      Chair: Don Thelen         Co-Chair: Kathleen Philips

Speed isn’t everything!      This session covers circuits with
challenges in other dimensions including voltage references,
voltage regulators and high voltage circuits.

2:00 pm     Introduction

2:05 pm     A Sub-1V Low-Noise Bandgap Voltage Reference, K.
17.1        Sanborn, D. Ma and V. Ivanov*, University of Arizona,
            Tucson, AZ, *Texas Instruments, Inc., Tucson, AZ

2:30 pm     A Compact Programmable CMOS Reference With
17.2        40µV Accuracy, V. Srinivasan, G. Serrano, C. Twigg
            and P. Hasler, Georgia Institute of Technology, Atlanta,

2:55 pm     A Transient-Enhanced 20µA-Quiescent 200mA-Load
17.3        Low-Dropout Regulator With Buffer Impedance
            Attenuation, M. Al-Shyoukh, R. Perez and H. Lee*,
            Texas Instruments Inc., Dallas, TX, *University of Texas
            at Dallas, Richardson, TX

3:20 pm     Compact Outside-Rail Circuit Structure By Single-
17.4        Cascode Two-Transistor Topology, A. Tamtrakarn, H.
            Ishikuro*, K. Ishida** and T. Sakurai, University of
            Tokyo, Tokyo, Japan, Keio University, Yokohama,
            Japan, Tokyo Institute of Technology, Yokohama, Japan

3:45 pm     BREAK

         Session 18 – Productivity Enhancement
                  and Design Optimization
      Cedar Ballroom, Tuesday Afternoon, September 12

    Chair: Gennady Gildenblat           Co-Chair: Rob Jones

This session presents the most important advances in compact
models, simulation algorithms, and web-based design
methodologies for productivity improvement and design

2:00 pm     Introduction

2:05 pm        Enhancing Productivity by Continuously Improving
18.1           Standard Compact Models (INVITED PAPER), J.
               Watts, IBM Mocroelectronics, Essex Junction, VT

2:55 pm        A Web Tool for Interactive Exploration of Analog
18.2           Design Tradeoffs, C. Recker, B. Braswell, P. Drennan
               and C. McAndrew, Freescale Semiconductor, Tempe,

3:20 pm        Circuit    Optimization     Using     Scale     Based
18.3           Sensitivities, B. Agrawal, F. Liu* and S. Nassif*, IBM
               EDA, Fishkill, NY, *IBM Austin Research Lab., Austin,

3:45 pm        BREAK

            Session 19 – Afternoon Panel Discussion
          Oak Ballroom, Tuesday Afternoon, September 12
                        4:00 PM – 5:30 PM

          Can the Analog/RF Designer/Enterpreneur Make
                   Money in a Fabless Startup?

Organizer: Henry Chang, Designer’s Guide Consulting
           Ramesh Harjani, University of Minnesota

Moderator: Henry Chang, VP, Designer’s Guide Consulting


Dado Banatao                              Sam Sheng
Managing Partner                          CTO/VP Engineering
Tallwood Venture Capital                  Telegent Systems

Aaron Cheatham                            Hemant Thapar
Principal                                 CEO
Mobius Venture Capital                    Link A Media Devices Corp.

Brian Fitzgerald                          Masoud Zargari
Executive Consultant                      Director
UTEK-EKMS Consulting &                    Atheros Communications
Serial Entrepreneur

It has been half a decade since the dot com boom. The memory of $500M
IC startup acquisitions grows faint.        There have been few IPOs.
Acquisitions in the $100M range are not uncommon. More common are
stories of quiet acquisitions of startups overwhelmed by competition,
usually ones engaged in building standards based consumer ICs. There
are few indicators that suggest that the climate for IC startups is changing.
Given this backdrop, this panel explores whether or not the analog/RF
designer/entrepreneur should start a new fabless IC company. Will the
founders be adequately rewarded? Will the employees be adequately
rewarded? Can the investors make money? We have invited venture
capitalists and founders of past and present startups to participate in this
panel. Though not as common, there are alternate approaches to funding
beyond venture capital. We have also invited a founder of a startup who
pursued alternate means. Please join us at this panel to learn the answers
to these questions. If you are interested in starting an IC company, bring
your questions!

            Session 20 – Afternoon Panel Discussion
          Fir Ballroom, Tuesday Afternoon, September 12
                         4:00 PM – 5:30 PM

             Fabless to Designless – How Do We Manage
                      Globalization Challenges?

Organizers: Yuhua Cheng, Siliconlinx Inc
            Sudhir Aggarwal, Adonics Technology

Moderator: Sudhir Aggarwal, Adonics Technology


Rob Aitken                                 Bob Payne
ARM Fellow                                 CTO
ARM                                        LSI Logic

Paul Bromley                               Shih-Wei Sun
Director Of corporate Strategic            Senior VP, Central R&D
Planning                                   UMC
                                           Woodward Yang
Mojy Chian                                 Professor
VP, Technology Development                 Harvard University
Altera Corporation

Rapidly increasing chip-design complexity and cost are forcing IC
companies to adopt more external IP and consider outsourcing to countries
with much lower labor cost. Will this bring us another new “designless”
business model in semiconductor industry? This brings up a lot of issues to
consider from business to technical:
     1.     Is this the only way to go and what can we do about it?
     2.     How do we look at this possible global business model in
            semiconductor industry?
     3.     What will the IC industry look like in 5 years?
     4.     What’s the role of the government during this period? How will
            the government and industry support the research programs
            need to advance technology with the outsourcing?
     5.     What types of jobs should stay on-shore both from political and
            business points of view?
     6.     How do we successfully manage trans-continental teams in
            several regions such as India, China, US and Taiwan,
            especially for a circuit that requires a lot of experience-intensive
            analog/RF designs?

This panel consisting of experts and senior managers from the industry will
discuss the IC design outsourcing issues, analyze the trend of advance and
globalization in the IC design industry, and explore the evolution of new
business models in the semiconductor industry.

                Session 21 – Custom Circuits
       Oak Ballroom, Wednesday Morning, September 13

     Chair: Ken Szajda         Co-Chair: Jacqueline Snyder

The session covers a number of applications ranging from current
and voltage effective generation to custom circuits used in optical
sensor systems, MEMS and implantable biomedical micro-

8:00 am      Introduction

8:05 am      A 4-Channel High-Precision Constant Current
21.1         Control ASIC for Automotive Transmission
             Applications, W. Horn, M. Graefling, G. Gross, M.
             Steiner, J. Treiber, R. Dickman, and K. Reis, Infineon
             Technologies Austria AG, Austria

8:30 am      Dithering Skip Modulator with a Width Controller for
21.2         Ultra-wide-load High-Efficiency DC-DC Converters,
             H-W. Huang, H-H. Ho*, C-C. Chien*, K-H. Chen*, G-K.
             Ma** and S-Y. Kuo, National Taiwan University, Taipei,
             Taiwan, *National Chiao Tung University, Hsinchu,
             Taiwan, **ITRI, Hsinchu, Taiwan

8:55 am      Per-Pixel Floating-Point ADCs with Electronic
21.3         Shutters for a High Dynamic Range, High Frame
             Rate Infrared Focal Plane Array, S-M. Lee, H. Park
             and B. Wooley, Stanford University, Stanford, CA

9:20 am      Smart CMOS Charge Transfer Readout Circuit for
21.4         Time Delay and Integration Arrays, C.B. Kim, B-H.
             Kim, Y.S. Lee, H. Jung and H.C. Lee, KAIST, Daejeon,

9:45 am      BREAK

10:00 am     A 104dB SNDR Transimpedance-based CMOS ASIC
21.5         for Tuning Fork Microgyroscopes, A. Sharma, F.
             Zaman and F. Ayazi, Georgia Institute of Technology,
             Atlanta, GA

10:25 am     Fully-Integrated CMOS Power Regulator for
21.6         Telemetry-Powered         Implantable      Biomedical
             Microsystems, A. Sodagar, K. Wise, K. Najafi and M.
             Ghovanloo, University of Michigan, Ann Arbor, MI

                      Session 22 – Oscillators
          Fir Ballroom, Wednesday Morning, September 13

   Chair: Amjad Obeidat           Co-Chair: Cormac O’Connell

This session presents advances in high-speed, widely-tunable
voltage-controlled oscillators and analysis of mutual pulling
between oscillators.

8:00 am       Introduction

8:05 am       A Varactor-Less 10GHz CMOS LC-VCO for Optical
22.1          Communications Transceiver SOCs Using Caged
              Inductors (INVITED PAPER), A. Maxim, Maxim Inc.,
              Austin, TX

8:55 am       An Ultra Compact Differentially Tuned 6GHz CMOS
22.2          LC VCO with Dynamic Common-Mode Feedback., B.
              Soltanian, H. Ainspan*, W. Rhee*, D. Friedman* and P.
              Kinget, Columbia University, New York, NY, *IBM T.J.
              Watson Research Center, Yorktown Heights, NY

9:20 am       Mutual Injection Pulling Between Oscillators, B.
22.3          Razavi, University of California, Los Angeles, CA

9:45 am       BREAK

     Session 23 – Advanced Technology Developments
                 and Fabrication Challenges
      Pine Ballroom, Wednesday Morning, September 13

     Chair: Alvin Loke          Co-Chair: David Sunderland

This session of Invited papers covers CMOS scaling, advanced
structures and packaging for high-performance digital and RF
applications, as well as competing technologies that overcome
present-day limitations of conventional CMOS.

8:00 am       Introduction

8:05 am       Technologies for (sub-) 45nm Analog/RF CMOS -
23.1          Circuit Design Opportunities and Challenges
              (INVITED PAPER), S. Decoutere, P. Wambacq, V.
              Subramanian, J. Borremans and A. Mercha, IMEC,
              Leuven, Belgium

8:55 am       Recent Advances in III-V Electronics (INVITED
23.2          PAPER), Y-K. Chen, Y. Baeyens, N. Weimann, J. Lee,
              J. Weiner, V. Houtsma and Y. Yang, Lucent
              Technologies, Murray Hill, NJ

9:45 am       BREAK

10:00 am   Electrical Characteristic Fluctuations in Sub-45nm
23.3       CMOS Devices (INVITED PAPER), F-L. Yang, J-R.
           Hwang and Y. Li*, TSMC, Taiwan, ROC, *National
           Chiao Tung University, Taiwan, ROC

10:25 am   SiGe BiCMOS Trends - Today and Tomorrow
23.4       (INVITED PAPER), J. Dunn, D. Harame, A. Joseph, S.
           St. Onge, N. Feilchenfeld, L. Lanzerotti, B. Orner, E.
           Gebreselasie, J. Johnson, D. Coolbaugh*, R. Rassel
           and M. Khater**, IBM, Essex Junction, VT, *Hopewell
           Junction, NY, **Yorktown Heights, NY

11:15 am   Advances and Challenges in Flip-Chip Packaging
23.5       (INVITED PAPER), R. Mahajan, D. Mallik, R. Sankman,
           K. Radhakrishnan, C. Chiu and J. He, Intel Corporation,
           Chandler, AZ

               Session 24 – Modeling for RF
     Cedar Ballroom, Wednesday Morning, September 13

     Chair: Colin McAndrew         Co-Chair: Yuhua Cheng

This session presents developments in modeling of noise,
inductors and gate resistance in advanced RF processes, and
new research in injection-locked oscillators.

8:00 am    Introduction

8:05 am    Compact modeling of noise in CMOS (INVITED
24.1       PAPER), A. Scholten, R. van Langevelde, L. Tiemeijer
           and D. Klaassen, Philips Research Europe, Eindhoven,
           The Netherlands

8:55 am    A Scalable Model Methodology for Octagonal
24.2       Differential and Single-Ended Inductors, V. Blaschke
           and J. Victory, Jazz Semiconductor, Newport Beach CA

9:20 am    Measurement of Inductive Coupling Effect on
24.3       Timing in 90nm Global Interconnects, Y. Ogasahara,
           M. Hashimoto and T. Onoye, Osaka University, Suita,

9:45 am    BREAK

10:00 am   A Novel Monitoring Method of RF Characteristics
24.4       Variations for Sub-0.1µm MOSFETs with Precise
           Gate-resistance Model, A. Tanabe, K. Hijioka and Y.
           Hayashi, NEC Corporation, Kanagawa, Japan

10:25 am   Sizing Ground Taps to Minimize Substrate Noise
24.5       Coupling in RF LNAs, A. Sundaresan, T. Fiez and K.
           Mayaram, Oregon State University, Corvallis, OR

10:50 am   First-Harmonic Injection-Locked Ring Oscillators, B.
24.6       Mesgarzadeh and A. Alvandpour, Linkoping University,
           Linkoping, Sweden

11:15 am      Analysis of Oscillators Locked by Large Injection
24.7          Signals: Generalized           Adler's Equation and
              Geometrical Interpretation, A. Mirzaei, M. Heidari and
              A. Abidi, University of California, Los Angeles, CA

11:40 am      Rigorous Analytical/Graphical Injection Locking
24.8          Analysis    of   Two-Port   Negative   Resistance
              Oscillators, T. Mei and J. Roychowdhury, University
              Minnesota, Twin Cities, MN

                    Session 25 – PLLs and DLLs
          Fir Ballroom, Wednesday Morning, September 13

   Chair: Eric Naviasky            Co-Chair: Shahriar Mirabbasi

This session covers advances in the design of low noise/spurious
PLLs and DLLs for frequency generation and clock recovery.

9:55 am       Introduction

10:00 am      A Digital PLL with 5-Phase Digital PFD for Low
25.1          Long-Term Jitter Clock Recovery, TY. Oh, S-H. Yi, S-
              H Yang, B-C. Lim and K-T. Hong, LG Electronics,
              Seoul, Korea

10:25 am      Adaptive-Bandwidth Mixing PLL/DLL Based Multi-
25.2          Phase Clock Generator for Optimal Jitter
              Performance, A.Tan and G-Y. Wei, Harvard University,
              Cambridge, MA

10:50 am      A Low Jitter Multi-Phase PLL with Capacitive
25.3          Coupling, J.Y. Park and M. Flynn, University of
              Michigan, Ann Arbor, MI

11:15 am      A 150MHz-400MHz DLL-Based Programmable Clock
25.4          Multiplier with -70dBc Reference Spur in 0.18µm
              CMOS, P. Maulik and D. Mercer, Analog Devices,
              Wilmington, MA

11:40 am      An Anti-Harmonic Locking, DLL Frequency
25.5          Multiplier with Low Phase Noise and Reduced Spur,
              Q. Du, J. Zhuang and T. Kwasniewski, Carleton
              University, Ottawa, Canada

         Session 26 – Clocking and Data Recovery
      Oak Ballroom, Wednesday Afternoon, September 13

     Chair: Makoto Takamiya           Co-Chair: Jackie Snyder

This session presents novel GHz clock distribution techniques,
low power oscillators, and AC coupled interconnects.

1:30 pm       Introduction

1:35 pm     Integrated VCO Design for MICS Transceivers, A.
26.1        Tekin, M. Yuce* and W. Liu, University of California at
            Santa Cruz, Santa Cruz, CA, *The University of
            Newcastle, Callaghan, Australia

2:00 pm     A 0.8V 1.52MHz MSVC Relaxation Oscillator with
26.2        Inverted Mirror Feedback Reference for UHF RFID,
            R. Barnett and J. Liu*, Texas Instruments, Dallas, TX,
            *University of Texas at Dallas, Richardson, TX

2:25 pm     A 36Gb/s ACCI Multi-Channel Bus using a Fully
26.3        Differential Pulse Receiver, L. Luo*, J. Wilson, S.
            Mick, J. Xu, L. Zhang, E. Erickson and P. Franzon,
            North Carolina State University, Raleigh, NC, *Rambus,
            Inc., Chapel Hill, NC

2:50 pm     900MHz to 1.2GHz Two-Phase Resonant Clock
26.4        Network with Programmable Driver and Loading, J-
            Y. Chueh, V. Sathe and M. Papaefthymiou, University of
            Michigan, Ann Arbor, MI

3:15 pm     BREAK

3:35 pm     Clock Generation and Distribution Using Traveling-
26.5        Wave Oscillators with Reflection and Regeneration,
            R. Wang, C-K. Koh, B. Jung and W. Chappell, Purdue
            University, West Lafayette, IN

4:00 pm     Injection-Locked Clocking: A New GHz Clock
26.6        Distribution Scheme, L. Zhang, B. Ciftcioglu, M.
            Huang and H. Wu, University of Rochester, Rochester,

                Session 27 – Wireless Receivers
       Fir Ballroom, Wednesday Afternoon, September 13

    Chair: Stefan Drude             Co-Chair: Ranjit Gharpurey

In this session implementations for advanced radio receivers that
address the challenges of modern communication systems will be

1:30 pm     Introduction

1:35 pm     Digital RF Processor Techniques for Single-Chip
27.1        Radios (INVITED PAPER), B. Staszewski, K.
            Muhammad and D. Leipold, Texas Instruments, Dallas,

2:25 pm     A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator
27.2        for Multi-Band Direct-Conversion Receivers, N.
            Poobuapheun, W-H. Chen, Z. Boos* and A. Niknejad,
            University of California, Berkeley, CA, *Infineon
            Technologies, Munich, Germany

2:50 pm     A 1.5-V CMOS Receiver Front-End for 9-Band MB-
27.3        OFDM UWB System, S. Lou, H. Zheng and H. Luong,
            The Hong Kong University of Science and Technology,
            Hong Kong

3:15 pm     BREAK

3:35 pm     A Distributed RF Front-End for UWB Receivers, A.
27.4        Safarian, L. Zhou and P. Heydari, University of
            California, Irvine, CA

4:00 pm     A Fully-Integrated 0.11µm CMOS Digital Low-IF
27.5        DVB-S2 Satellite TV Dual Tuner SOC, A. Maxim, R.
            Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M.
            Chennam, T. Nutt and D. Trager, Silicon Inc., Nashua,

               Session 28 – High Speed Analog
      Pine Ballroom, Wednesday Afternoon, September 13

          Chair: Yusuf Haque         Co-Chair: David Rich

This session presents advances in on chip noise suppression,
improvements on filter tuning and linearity, temperature sensing
techniques, dc and ac amplifier performance and low noise

1:30 pm     Introduction

1:35 pm     Active On-Die Suppression of Power Supply Noise,
28.1        G. Keskin, X. Li and L. Pileggi, Carnegie Mellon
            University, Pittsburgh, PA

2:00 pm     A Fully Integrated DC/DC Converter for Tunable RF
28.2        filters, M. Bouhamame, J. Tourret, L. Lococo, S.
            Toutain* and O. Pasquier*, Philips Semiconductors,
            Caen, France, *Institut de Recherche en Electronique et
            Electrotechnique de Nantes Atlantique

2:25 pm     A Time Domain Mixed-Mode Temperature Sensor
28.3        with Digital Set-Point Programming, P. Chen, C-C.
            Chen, T-K. Chen and S-W. Chen, National Taiwan
            University of Science and Technology, Taipei, Taiwan

2:50 pm     A Unity-Gain Buffer with Reduced Offset and Gain
28.4        Error, G. Xing, S. Lewis* and T. Viswanathan**,
            Marvell Semiconductor, *University of California, Davis,
            CA, **University of Texas, Dallas, TX

3:15 pm     BREAK

3:35 pm     A 19-GHz Broadband Amplifier Using a gm-Boosted
28.5        Cascode in 0.18-um CMOS, M. Hossain and A. Chan
            Carusone, University of Toronto, Ottawa, Canada

4:00 pm     A 0.6V Highly Linear Switched-R-MOSFET-C Filter,
28.6        P. Kurahashi, P. Hanumolu, G. Temes and U-K. Moon,
            Oregon State, Corvallis, OR

4:25 pm     Fast Automatic Tuning of Channel Selection Filters
28.7        Based on Phase Delay Calibration, K. Kagoshima, S.
            Kawama, S. Toyoyama and K. Iizuka, Sharp
            Corporation, Nara, Japan

4:50 pm    A Low Phase Noise 100MHz Silicon BAW Reference
28.8       Oscillator, K. Sundaresan, G. Ho, S. Pourkamali and F.
           Ayazi, Georgia Institute of Technology, Atlanta, GA

 Session 29 – Modeling and EDA Challenges in Nano-CMOS
    Cedar Ballroom, Wednesday Afternoon, September 13

  Chair: Yuhua Cheng            Co-Chair: Hidetoshi Onodera

This session discusses and reviews modeling and EPA
challenges in nano-scale CMOS technologies. The impact of
variabilities on device and circuit performances will also be

1:30 pm    Introduction

1:35 pm    EDA Challenges in Nano-scale Technology (INVITED
29.1       PAPER), J. Kawa, C. Chiang and R. Camposano,
           Synopsys, Inc., Mountain View, CA

2:25 pm    Statistical and Corner Modeling of Interconnect
29.2       Resistance    and   Capacitance, N.   Lu,  IBM
           Semiconductor Research and Development Center,
           Essex Junction, VT

2:50 pm    Experimental Verification of Simulation Based Yield
29.3       Optimization for Power-On Reset Cells, G. Rappitsch,
           O. Eisenberger, B. Obermeier*, A. Ripp* and M.
           Pronath*, austriamicrosystems AG, Unterpremstatten,
           Austria, *MunEDA GmbH, Munich, Germany

3:15 pm    BREAK

3:35 pm    Measurement Results of Delay Degradation Due To
29.4       Power Supply Noise Well Correlated With Full-Chip
           Simulation, Y. Ogasahara, T. Enami, M. Hashimoto, T.
           Sato* and T. Onoye, Osaka University, Suita, Japan,
           *Tokyo Institute of Technology, Yokohama, Japan

4:00 pm    Delay Variation Analysis in Consideration of
29.5       Dynamic Power Supply Noise Waveform, M.
           Fukazawa and M. Nagata, Kobe University, Kobe,

4:25 pm    Crosstalk Reduction with Nonlinear Transmission
29.6       Lines for High-Speed VLSI System, J. Kim, W. Ni and
           E. Kan, Cornell University, Ithaca, NY

LOCATION         DoubleTree Hotel
                 2050 Gateway Place
                 San Jose, CA 95110
                 (408) 453-4000

Payment of the Technical Session registration fee entitles the
registrant to entrance to all Monday-Wednesday Technical Sessions,
the Exhibit Hall, Welcome Reception, Tuesday Happy Hour,
Wednesday CDNLive! Technology Demo Night and to one copy of the
Conference Proceedings and CD ROM. Single-day registration
(Monday, Tuesday, Wednesday) entitles the registrant to that day's
events and one copy of the Conference Proceedings and CD ROM.
Technical session registration does not include entrance to the
Sunday Educational Sessions.

Payment of the Sunday Educational Sessions registration fee entitles
the registrant to entrance to the Sunday Educational Sessions, lunch
on Sunday, and one copy of the Educational Sessions Workbook.
Educational Session registration does not include entrance to the
Monday-Wednesday Technical Sessions, the Exhibits or a copy of the
Conference Proceedings and CD ROM.

How to Register

Online Registration
To register online for the Technical Sessions and/or Sunday
Educational Sessions go to the CICC website at
Click on Registration.

Registration by Mail or Fax
To register by fax or mail fill out the registration form in the center of
this booklet and fax or mail the form and payment.

Mail the form to:
            CICC Conference
            16220 S. Frederick Avenue
            Suite 312
            Gaithersburg, MD 20877


Fax the form to: 301-527-0994

Don’t register online and by mail or fax –it will result in double

   Online and mail/fax registration forms MUST be received by
                         Monday, August 28
       After that date please register onsite at the conference.

Make checks payable to CICC 2006 in US dollars on a US bank. We
also accept VISA and MasterCard only. CICC is not able to accept
American Express charges. Requests for cancellations must be
received by September 1, 2006 to qualify for a refund.       All
cancellations will be charged a $25.00 processing fee.

Questions on Your Registration
If you have questions on your registration please contact:
By email:
By phone: 301-527-0900 x 101
By fax: 301-527-0994

Onsite Registration and Advance Registration Badge Pick-Up
The Registration Center, located in the Bayshore Foyer, will be open
as follows:

Registration for Sunday Educational Sessions Only
          Sunday, Sept. 10         7:00 am - 2:00 pm
Registration for Technical Sessions
    Sunday, Sept. 10          2:00 pm - 5:00 pm
    Monday, Sept. 11          7:30 am - 5:00 pm
    Tuesday, Sept. 12         7:30 am - 5:00 pm
    Wednesday, Sept. 13       7:30 am - 3:00 pm

The DoubleTree Hotel is located at 2050 Gateway Place, San Jose,
California. The hotel has an outdoor swimming pool and exercise
facilities. Parking at the Hotel is $2/hour, maximum $10/day. The
hotel has a complimentary shuttle from San Jose Airport. The hotel is
only 1 mile from the San Jose Airport.

The room rate is $125 for a single or double room. All rooms must be
guaranteed with a credit card. To make a hotel reservation call the
hotel at (408) 453-4000 or go to the CICC website ,
click on Hotel Reservations, then complete the form.

The cut-off date for the CICC rate is August 18, 2006. To qualify for
the CICC rate you MUST make your hotel reservation by the cut-off
date. Make certain you tell reservations you are with IEEE CICC.

You will receive a reservation confirmation directly from the hotel. It is
the responsibility of each participant to make changes or cancellations
directly with the hotel no later than 24 hours prior to scheduled arrival.
No refunds will be given by the hotel for changes or cancellations with
less than 24 hours notification.

On Sunday, Sept. 10, the CICC sponsors three Educational Sessions.
These Sessions are:
  1. Integrated Phase-Locked Systems-Optimization and Trends
  2. Advanced RF Design Techniques
  3. High-Performance and Low-Power Digital Circuit Design

To register, complete the Advance Registration Form for receipt by
August 28.

Welcome Reception - Monday Evening, Sept. 11, 5:30 pm - 8:00 pm
Donner Pass Ballroom
The CICC social event this year is the Welcome Reception sponsored
by the CICC 2006 Exhibits Committee, held in the Exhibit Hall. All
conference attendees are cordially invited! Enjoy the evening by
browsing around the exhibit area, talking with the exhibitors' staff,
seeing old friends and meeting new ones.

Happy Hour – Tuesday Evening, Sept. 12, 5:30 pm – 7:30 pm
Donner Pass Ballroom
Join the CICC for a Tuesday night Happy Hour for a final visit to the
Exhibits and Posters. Thank you Cadence Design Systems for
sponsoring the Happy Hour this year.

Tuesday, Sept. 11, 12:15 pm - 1:30 pm
Sierra Ballroom

The CICC Luncheon features an address titled “From Rocks to Chips:
A Rambling History of the Integrated Circuit” by Professor Tom Lee of
Stanford University. Luncheon is not included in the registration fee.

Luncheon tickets are available through Advance Registration or onsite
at a cost of $32 per ticket. See page 27 for a description of the

The proceedings contains papers on each presentation. Technical
Session registrants will receive one copy of the Proceedings.
Additional copies will be available at the conference registration desk,
IEEE member: $80, Non-member: $90. After the conference, order
the Proceedings through: Single Copy Sales, IEEE Service Center,
445 Hoes Lane, Box 1331, Piscataway, NJ, 08855-1331, Customer
Service Department (toll free): 800-678-4333. The IEEE catalogue
number is 06CH37753

Approximately six weeks after the conference, technical session
registrants will be mailed the conference CD ROM which includes
copies of the papers and presentation slides. CICC gratefully
acknowledges Philips Semiconductors’ sponsorship of this CD ROM.

Additional copies of the CD ROM can be ordered onsite at the
conference registration desk, IEEE member: $80, Non-member: $90.
CD ROMs are not for sale by IEEE after the conference.

There will be author interviews each day of the conference
immediately following the afternoon sessions in Gateway Foyer. This
additional forum provides an opportunity for relaxed discussions with
your colleagues outside the strict time constrains of the regular

CICC acknowledges the generous support of our conference sponsors
    Philips Research for the CD ROM
    AMI for the T-Shirts
    Cadence Design Systems for the Tuesday Happy Hour
    Texas Instruments for the Internet Café
    Intel for the AV Sponsorship
    Altera for the AV Sponsorship
    GE Global Research for the Best Paper Award Sponsorship
    DigiSensory Technologies for the Demo Sponsorship

The DoubleTree Hotel is approximately 1 mile from San Jose Airport.
There is a complementary hotel shuttle from San Jose Airport to the
hotel that runs from 6:00 am to midnight. Call the hotel on the
DoubleTree Courtesy Phone outside the baggage area at San Jose

For passengers flying into San Francisco Airport, the San Jose
Doubletree is approximately 33 miles from the airport. Supershuttle
Service provides shuttle service from the airport to the hotel.
Arrangements can be made at Ground Transportation or by calling
(415) 558-8500 for more information. You can also make reservations
online at The cost is $38.00/one way or
$76.00/round-trip. Taxi service is also available from the airport at an
estimated cost of $75.00.

Visit the San Jose Convention & Visitor’s Bureau website at for a listing of activities and attractions in the San
Jose area. Downtown San Jose, including the Convention Center, is
accessible from the DoubleTree Hotel via Light Rail service. The
“Metro Road” Light Rail stop is two blocks from the hotel and trains
run every 15 minutes and cost $1.75 one way.

Badges are required for admittance to all sessions and the exhibit hall.
Please wear your badge at all times while attending the conference so
that you will not be delayed entry to a session.

    CICC 2006
         Suite 312
    16220 S. Frederick Ave.
    Gaithersburg, MD 20877
    Phone: 301-527-0900 ext. 101, Fax: 301-527-0994
    Home Page:

This year the CICC is co-locating with the IEEE Behavior, Modeling, and
Simulation Conference 2006. BMAS will take place September 14 – 15 at
the DoubleTree Hotel, San Jose, California.

Visit the BMAS website at for complete conference

Cadence CDNLive!
CICC attendees are invited to the Cadence CDNLive! Technology
Night on Wednesday, Sept. 13, from 5:30 pm – 8:00 pm at the San
Jose Convention Center in downtown San Jose. Visit the following
website for a list of the demonstrations scheduled:

        Visit our website at


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