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SILICON GERMANIUM BICMOS TECHNOLOGY Paul Kempf Jazz Semiconductor

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SILICON GERMANIUM BICMOS TECHNOLOGY Paul Kempf Jazz Semiconductor Powered By Docstoc
					                   SILICON GERMANIUM BICMOS TECHNOLOGY
                                         Paul Kempf
                                    Jazz Semiconductor
                                  Newport Beach, CA, USA
                                  paul.kempf@jazzsemi.com

ABSTRACT                                        increased functionality, reduced power and
Integration,   speed      and      power        reduced cost.
improvements achieved using silicon
germanium bipolar transistors have              Increased data density in disk drives is
enabled new types of functionality in           leading to a need for higher data rate and
high-performance integrated circuits.           greater sensitivity pre-amplifiers that require
                                                SiGe BiCMOS. Developing standards, such
INTRODUCTION                                    as Ultra-Wide-Band for wireless data, can
After a discussion of some applications that    exploit the performance offered by SiGe
benefit from the use of SiGe BiCMOS             BiCMOS to meet the 2-11 GHz frequency
technology, this paper describes a              requirements while meeting power and cost
production process with bipolar Ft of 150       targets consistent with a consumer
GHz and Fmax of 170 GHz.                The     application.
modularity of this technology enables cost
and performance trade-offs that make it         HIGH-PERFORMANCE
suitable for different market segments.         TECHNOLOGY
Leveraging the same manufacturing               Multiple      generations     of   BiCMOS
infrastructure and tools that are used for      technology demonstrate rapid advances in
mainstream CMOS technology makes it             bipolar performance (see Figure 1 and Table
possible to provide the predictable             1). A production 0.18 m SiGe BiCMOS
performance and high yield that is expected     technology (SiGe120) with Ft=150 GHz and
in silicon manufacturing.                       Fmax=170 GHz begins with collector
                                                formation using a buried layer and substrate
APPLICATIONS FOR SIGE BICMOS                    epi. Utilizing both shallow and deep trench
SiGe bipolar transistors can now match or       isolation, a self-aligned SiGe NPN is formed
exceed the performance of production III-V      after most of the standard dual-gate 0.18 m
technologies. Mainstream acceptance has         CMOS steps. Blanket SiGe epitaxy is
made SiGe BiCMOS cost competitive with          performed in a single-wafer RT-CVD. A
advanced CMOS. Increased RF sub-system          sacrificial emitter post is patterned using
functionality is driving new architectures,     DUV lithography to achieve scaling
like direct conversion radios, which reduce     comparable to CMOS gates. Self-aligned
the dependence on off-chip components           extrinsic base implants enable optimization
while the requirements of next generation       of extrinsic base resistance while
products are more demanding in terms of         maintaining a simple bipolar structure.
noise figure, gain, linearity and power         After removal of the sacrificial emitter and
consumption than the current generation.        pre-clean steps, an in-situ doped poly
                                                emitter is deposited in an RT-CVD reactor
Physical layer products for 10G and 40G         and patterned.
systems have migrated to more highly
integrated SiGe BiCMOS designs that have
                                                                   FETs and deep trench reduces the mask
             200                                                   count and cost. Three different top via and
             175                                                   thick metal modules are available for
             150                                                   optimum usage depending on the cost,
  Ft (GHz)




             125                                                   integration level and inductor performance
             100                                                   requirements. A module with 4 m deep top
              75                                                   via and 6 m thick aluminum (10 m above
              50                                                   the silicon substrate) offers significant
              25                                                   enhancement in inductor performance or
               0                                                   reduction in inductor area for the same level
                0.01           0.1           1             10      of performance.
                       Ic (mA) for Minimum We and Le=1 m
                                                                   A 1 kOhm/sq p-type poly resistor in SiGe90
 Figure 1. Ft versus collector current for                         provides footprint and matching suitable for
 several    generations    of    BiCMOS                            2 to 6GHz RF circuit design. Upgrade of
 technology.                                                       the MIM capacitor to 2.0 fF/um^2, or 4.0
                                                                   fF/um^2 in its stacked topology, reduces
 Table 1. Bipolar transistor specifications for                    capacitor area by using a scaled version of a
 0.18 m technology.                                                nitride dielectric.

                    FT        @JE        Fmax    BVCEO     VCCBO   TECHNOLOGY BEYOND 200GHZ
                   GHz       mA/µm2      GHz       V        V      A 200 GHz BiCMOS process has been
SiGe 120           150         5         170      2.2        7     derived from the production, 150 GHz
SiGe 90             75        2.5        130      3.8       11
                                                                   process technology. A strong reduction in
SiGe 90             35        0.6         60       6        14
                                                                   emitter resistance, coupled with a small re-
                                                                   optimization in the collector dose has been
 The subsequent cobalt silicide formation,
                                                                   used to increase the Ft of the SiGe transistor
 contact etch and oxide CMP are the same as
                                                                   without significantly reducing the base
 the standard CMOS process. The SiGe120
                                                                   width, resulting in a peak Ft of 205 GHz
 process continues with 4 layers of standard
                                                                   with a BVceo of 1.8 V. Improving Fmax
 metalization, thin film metal resistor, and
                                                                   beyond 200 Ghz is accomplished by a
 MIM capacitor plus 2 thick layers of
                                                                   combination of higher Ft and a reduction in
 aluminum (1.5 m and 3.0 m) for
                                                                   parasitic effects. Intrinsic base resistance is
 implementation of transmission lines and
                                                                   reduced by decreasing the emitter width, and
 inductors.
                                                                   parasitic collector-base capacitance is
                                                                   reduced by scaling the base active opening.
 WIRELESS TECHNOLOGY
 Wireless     applications   require    high-
                                                                   MANUFACTURABILITY
 performance bipolar transistors with quality
                                                                   A key to manufacturability of SiGe
 passives and CMOS density suitable for
                                                                   technology is the reuse of high-volume
 moderate levels of mixed-signal and logic
                                                                   CMOS infrastructure.      The maturity of
 integration. This is achieved in SiGe90 by
                                                                   process equipment, the high level of factory
 eliminating SiGe120 process modules that
                                                                   automation for recipe download and wafer
 are not required to meet RF sub-system
                                                                   handling, the yield management discipline
 requirements, while adding RF passives that
                                                                   and the mechanisms for continuous
 enable improved RF performance and
                                                                   improvement make it possible to deliver
 reduced die size. Elimination of the 0.18 m
high quality wafers in complex process                            adds to the SiGe bipolar variability. Control
technologies.        For similar process                          of all of these parameters translates into
complexity, as measured by the number of                          resistances and vertical doping profiles that
critical photomask layers or the number of                        determine the range of bipolar Ft, which is
process steps, the manufacturing cost and                         shown in Figure 5 to be 2.5% 1-sigma for
fab yield is comparable regardless of the
technology specifics. It is the commitment
                                                                                               SiGe120 Ft, Fmax Control
to establishing process modules that are
within the capability of the equipment set                                           240
that makes it possible to deliver SiGe
                                                                                     220
technology that is as repeatable and cost
                                                                                     200




                                                                     Ft,Fmax (GHz)
effective as mainstream CMOS.
                                                                                     180                                  HS Ft
The ability to perform in-line measurement                                           160                                  HS Fmax
of SiGe epi thickness, germanium content                                             140
and boron doping level is required to                                                120
establish typical production control charts.
                                                                                     100
Spectroscopic ellipsometry can be used on                                                  1   11    21    31     41
production wafers to monitor SiGe epi                                                           Sampled Lots
thickness, as shown in Figure 2.
Demonstrated control of 1.64% 1-sigma
variation provides feedback on the epi                            Figure 3. Uniformity of Ft and Fmax
process. Measurement of poly thickness and                        demonstrated by measurements from
in-line sheet resistance closes the loop for                      over 40 production lots (mean Ft=158
day-to-day SiGe manufacturing.                                    GHz with 1-sigma variation of 3.9 GHz or
                             SiGe Epi Control Chart               2.5%).

               500                                                over 40 production lots of a technology with
               480                                     Measured
                                                       (A)
                                                                  mean Ft greater than 150 GHz.
               460
   Thickness




               440                                     LSL
                                                                  Investigation of wafer contour plots of Ft for
               420                                                a 200 GHz technology demonstrates similar
               400                                     USL        control with 1-sigma variation of 1.85%
               380                                                over a 200mm wafer.
               360
                              13
                                   19
                                        25

                                             31
                                                  37
                     1
                         7




                              Lot Num ber                         CONCLUSION
                                                                  SiGe BiCMOS technology addresses a
                                                                  number of different market segments. A
Figure 2. SiGe epi thickness uniformity                           state-of-the-art example provides a variety
demonstrated by measurements on over                              of features while maintaining the benefits of
40 production lots (1-sigma thickness                             manufacturing silicon-based technology.
variation of 7.2A or 1.64%, measurement
accuracy 7.7A 1-sigma).                                           ACKNOWLEDGEMENTS
                                                                  The author would like to acknowledge the dedicated
                                                                  efforts of the Jazz Semiconductor team.
Process variation related to the emitter
formation, such as emitter pre-clean, in-situ
poly doping and final rapid thermal anneal,

				
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posted:8/2/2011
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