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					    System-Level Living Roadmap

         GSRC Annual Symposium
         September 28 & 29, 2006

Faculty: Kahng, Markov, Orshansky, Sylvester
              System-Level Living Roadmap
• Only cost-effective technology innovations reach production
     – What are relevant bounds, and how do they evolve?
     – What are quantified benefits from available technology options?
     – Beyond-ITRS: what are system implementation roadblocks?

• System-level design optimization and scaling
     – What are the relevant models and metrics for system scaling?

• Early analysis tools
     – Map technology concerns (power, variability, speed, area, …) to
       system concerns (total cost, availability, …)

• Roadmaps
     – Connect applications to design and process technologies
        well-calibrated cost and resource tradeoffs

September 28, 2006                   GSRC Annual Symposium
                                                                         2
            Roadmap of Parametric Yield Estimation and
            Optimization: TUNES
                                                            Variability Data
    Technology / Circuit Data




   Fmax Variability


                                Statistical Clock Skew            SER Macromodeling




September 28, 2006                        GSRC Annual Symposium
                                                                                      3
                       Roadmap of Parametric Yield Estimation and Optimization:
                       Block-Level Probabilistic Power-Delay Exploration
• Variability greatly impacts leakage
  power and parametric yield
    – Exponential dependency on process

•   Package often sets power limits
    – Cooling costs grow rapidly for higher power



                                                Power w/    Cooling/Power Limit
                                                Leakage
     Number of Parts




                                Leakage
                        Power




                                   Switching
                                                                           Minimum Ship
                                   Power                                   Frequency




                                                 Design Spread                  Slow
                       Fast                                    Max Ship Freq
                                Max Ship Freq
                                                               (With Leakage)
                                (No Leakage)
September 28, 2006                                     GSRC Annual Symposium
                                                                                          4
                                   Roadmap of Parametric Yield Estimation and Optimization:
                                   Block-Level Probabilistic Power-Delay Exploration
• How much parametric yield loss can be                                                                                                                          Statistical Optimization
  recovered?                                                                                                                                                     Deterministic Optimization
• DAC-05 Best Paper: Robust LP, second-order




                                                                                                                      Frequency
  conic programming for sizing / dual Vth
            – Efficient, large-scale parametric yield
              maximization
• Designer chooses sweet spot in power-delay
  space, trades timing yield for power yield, etc.
            – E.g., 5% timing yield loss  25% less power                                                                         0              200            400           600
                                                               Timing yield = 99.9%                                                                 Static Power ( μW )
                      900
                                                               Timing yield = 95%
                      850                                      Timing yield = 84%                        900
                                                                                                                                                 Deterministic optimization
                      800                                                                                                                        Statistical: inter and intra-chip variation
   99.9% Power (W)




                                                                                                         850
                                                                                                                                                 Statistical: all intra-chip variation
                                                                                      Total Power (W)   800
                      750

                      700                                                                                750

                                                                                                         700
                      650
                                                                                                         650
                      600
                                                                                                         600
                      550
                                                                                                               0.60               0.61   0.62     0.63   0.64   0.66   0.67
                            0.53   0.56   0.58   0.60   0.62    0.64   0.67                                                                     Delay (ns)
                                            Delay (ns)
 September 28, 2006                                                                                 GSRC Annual Symposium
                                                                                                                                                                                               5
         Roadmap of Reliability: Impact of Dynamic
         Reliability Management
• TDDB, EM, thermal cycling, NBTI with dynamic stress inputs
• PID + threshold control solution
• DRM voltage control
   – Boosts/throttles maximum assignable voltage
   – +25% peak performance with typical workload/temperature
        • +12-15% peak performance  workloads
        • +10-12% peak performance  temperature
• Future directions                            1.8

                                               1.6

   – Parametric performance           VDD
                                               1.4
                                               1.2
                                                                             “Boost”


     degradations vs. hard failures              1

                                               0.8
   – Sensor architecture and                   0.6
                                                      0        2         4             6       8   10          12
                                            In a DRM System, the maximum voltage can be
     placement                              “boosted” to allow periods of higher peak
                                            performance while maintaining a margin below
                                                    x 10  -9
                                                                                                              x 10
                                                                                                                     4


                                                  3


   – ElastIC: A system-level
                                            the budgeted damage curve.
                                                2.5

                                                                       Lifetime Budget Curve
     adaptive architecture            Damage
                                                 2

                                                1.5
                                                                                           DRM Damage Curve
                                                 1

                                                0.5
                                                                                           DVS Damage Curve
                                                 0

September 28, 2006                      GSRC Annual Symposium
                                                      0        2         4
                                                                                   Time
                                                                                       6       8   10          12
                                                                                                               x 10 4
                                                                                                                  6
            Roadmap of Reliability: Efficient Soft Error
            Analysis and Optimization in Combinational Logic
• Proposed algorithm considers injection, propagation, and merging of
  SET descriptors (capturing correlation between transient waveforms and
  rate distribution function) in STA-like fashion
    – Waveform models based on Weibull, 1-time characterization cost
• Highly efficient: runtime linear with #gates (25K gates in 0.2sec)
• Accurate: ~15% error in FIT
•   vs. Monte-Carlo SPICE
                                                           Q0  {Q1, Q2, …, Qm}
• Used in SER optimization

• Gate sizing + flip-flop             R1




                                                                                          Voltage (V)
  assignment shows 28X                          Rate Function       Transient Injection
                            Rate R




                                                                                                               Qm
  SER reduction with no                    R2
                                                                                                          Q1
  delay penalty and 5%                                     Rm
  area overhead
                                                                                                        Time (ps)
    – Runtime: 1 min
                                     Q1 Q2      Charge Q    Qm


      for 5K gates                                                SET Descriptor
                                                                      (d0,d1)
                                                                     Vector b
                                                                     Vector R
                                                                                          Waveform Parameters
September 28, 2006                                     GSRC Annual Symposium
                                                                                                                    7
        Roadmap of Reliability: Bottom-Up Reliability
        Prediction
• System-level analysis requires: • Pulse Generation:
    – Precise gate electrical                    – Library: Output Waveform =
      properties                                   f(Collected Charge)
    – Logical structure of the circuit
    – System-level timing behavior                                                  Vth
    –  Electrical, logical, and timing                       Y               0   PW
      window masking                       A=0                     CL
• Cell library characterization
• Intractability (#P) of logical           B=1
  masking                                                                          Library
    – Pioneered use of decision
      diagrams in this context               •   Pulse Propagation:
    – DATE-05 Best Paper award                   – Library: Output Waveform =
• Three new static SER analysis                    f(Input Waveform)
  tools
                                                        Y               Vth        Library

                      Vth
                            0   PWin
                                       A               CL
                                       B=1
 September 28, 2006                        GSRC Annual Symposium
                                                                                             8
           Roadmap of Reliability: Fast Analysis of Soft Error
           Susceptibility (FASER) for Cell-Based Designs
•    Fast analytical modeling and
    computational technique for logic SER                                                 0.02




                                                                      Error Probability
    analysis for cell level designs                                                                                                             SPICE
                                                                                                                                                FASER
    – Excellent accuracy compared to                                                      0.01
      SPICE
    – Best Paper Award, ISQED 2006                                                            0
                                                                                                      C1       C2       C3    C4      C5         C6       C7
                                                                                                                        Benchmark Circuit


                                                                             0.6
                                                                                                           With Logic Masking
                                                                                                           Without Logic Masking
                                                                             0.5




                                            Soft Error Rates (a.u.)
                                                                             0.4


                                                                             0.3


                                                                             0.2


                                                                             0.1


                                                                                          0
                                                                                                  1        2        3        4        5     6         7

                                                                                                                        Logic Depth



September 28, 2006                     GSRC Annual Symposium
                                                                                                                                                               9
            Roadmap of Reliability: System Susceptibility to
            Soft Errors: Memory Modeling
•   Memory arrays much more sensitive                                                      Inverter 1
                                                                                                        Iseu
    to single event upsets                                               V1                      V2


•   Developed first analytical model for
    predicting SER noise margins under                          C                                              C



    dynamic disturbances (single event
    upsets)                                                                   Inverter 2




                                              0.8
                                                                                       Analyitcal


                                              0.6                                      SPICE

                                    In (mA)                                            Bounds
                                              0.4



                                              0.2       I snm


                                               0
                                                    0               20                           40                60
                                                                              Tcrit (ps)

September 28, 2006                       GSRC Annual Symposium
                                                                                                                        10
            Roadmap of Reliability: Synthesis for Reliability
            and Probabilistic Testing

• Optimize reliability using          New project with
  recent competitive                  Air Force Research Lab
  synthesis frameworks                • Evaluating 4 GSRC
     – Allow or veto logic              reliability evaluators
       transformations                  and two more
     – Using ABC from Berkeley            – Figure out which work !

• Probabilistic test                 • Use in estimation
     – Take deterministic patterns • Use in synthesis
                                       and optimization
     – Compute multiplicities
       using a reliability evaluator • Use in circuit test



September 28, 2006              GSRC Annual Symposium
                                                                      11
                                      Roadmap of Power and Variability: Energy-Optimal
                                      Gate Sizing for Subthreshold Circuits
   • Subthreshold energy efficiency is limited by leakage
      – Energy optimal supply voltage, Vmin, determined by rise in leakage
      – At Vmin, leakage accounts for ~30% of total energy

                                    E  E dyn  E leak  C  Vdd    Ileak  Vdd  TCLK
                                                               2


 • Increasing gate sizes along critical paths can reduce energy
    – Shorter clock period = shorter leakage time
    – A reduction c499leakage affects the location of c499 ; therefore, Vdd can
                  in                                   Vmin

      Number of Paths




                                                                                         Number of Paths
                        700                                                                                700
                       Before After                       Before   After
       be reduced if leakage is reduced
                        600
                        500
                                                                                                           600
                                                                                                           500
                        400                                                                                400

 • An energy-driven, TILOS-like sizing algorithm yields energy savings of
                        300
                        200
                                                                                                           300
                                                                                                           200

   ~6-15% on ISCAS85 benchmarks
                        100
                         0
                                                                                                           100
                                                                                                            0
                              0.0       0.2     0.4         0.6         0.8       1.0                            0.0       0.2    0.4           0.6      0.8   1.0

                                                      c7552
                                                       c499                                                                             c7552
      Number of Paths




                        700
      Number of Paths




                                                                                        Number of Paths




                        400                                                                                400
                        600                                 Before            After
                                                                     After                                                                            After
                        300
                        500                                                                                300
                                    Before                                                                             Before
                        400
                        200          6% energy                                                             200
                                                                                                                                                               15% energy
                        300
                        200
                        100          reduction                                                             100
                                                                                                                                                                reduction
                        100
                         0                                                                                  0
                              0.0       0.2     0.4         0.6         0.8       1.0                            0.0       0.2    0.4           0.6      0.8   1.0

                                       Delay       c7552
                                               (Normalized        to TCLK)                                                Delay (Normalized to TCLK)
      r of Paths




                        400

    September 28, 2006                                               After                                 GSRC Annual Symposium
         300
                                    Before                                                                                                                                  12
                        200
            Roadmap of Power and Variability: Design Assessment
            under Realistically Available Uncertainty Descriptions
• In practice, detailed process
  characterization data for current and                                                             E [X ] V ar [X ]
  future generations are not available
     – Only partial probabilistic descriptions
       are accessible, e.g., mean and
       variance                                                                                X                           X
     – Timing, power, and parametric yield
       estimates are affected




                                                 C u m u la tiv e P ro b a b ility
                                                                                     1.0
• Probabilistically-enhanced interval                                                0.9
  analysis                                                                           0.8
                                                                                     0.7
   – Use mean, variance, and intervals                                               0.6
     of circuit parameters to estimate                                               0.5
     probabilistic bounds for timing and                                             0.4
                                                                                     0.3
     power                                                                           0.2
   – Probability box: bounds for                                                     0.1
     cumulative distribution function                                                0.0
                                                                                       -0.10       -0.08   -0.06   -0.04   -0.02   0.00
                                                                                                             Vdd (V)

September 28, 2006                        GSRC Annual Symposium
                                                                                                                                     13
         Roadmap of Power and Variability:
         Intra-Gate Biasing
• Exploit edge effects in modern MOSFET devices that lead
  to different Ion/Ioff current densities based on position in
  channel
• Key: lengthen channel near edges to suppress high leakage
  there, reduce Ldrawn in center slightly to compensate
• FREE circuit-level leakage reduction on the order of 5-6%
     – No delay penalty or optimization cost
• An orthogonal knob to all other
  circuit optimization techniques
                                    14
                                               Leakage Improvement vs Width
          Leakage Improvement (%)




                                    12


                                    10


                                    8


                                    6


                                    4


                                    2
                                         200   400      600       800     1000
                                                     Width (nm)
September 28, 2006                                                               GSRC Annual Symposium
                                                                                                         14
              Roadmap of Cost: Low-Volume Implementation
• What can be recovered along cost trajectory of Moore’s Law?
    – OPC, reticle plan, multi-layer reticle strategy, multi-flow production strategy,
      wafer shot map, blading, mask write and inspect, dicing plan, …
       many optimization opportunities
    – Goal: 10X reduction in per-die cost for low volume




 September 28, 2006                        GSRC Annual Symposium
                                                                                         15
             MFMLMP Reticles
• A reticle has multi-layers of multi-projects of multi-flows
• Different printing frames for different wafers
• More design challenges: layer assignment, flow embedding and
  frame floorplan

             Die 1   Die 2
                                  Die 1         Die 2            Die 1        Die 2
             Lay 3   Lay 3
                                  Lay 3         Lay 3            Lay 3        Lay 3
Reticle 1
                                  Die 1                                      Die 2
             Die 1                Lay 2                                      Lay 2
             Lay 2
Frame                             Die 1        Die 2             Die 1       Die 2
                     Die 2        Lay 1        Lay 1             Lay 1       Lay 1
                     Lay 2
                                Die 1          Die 2            Die 1        Die 2
Reticle 2
             Die 1   Die 2         Wafer 1                               Wafer 2
             Lay 1   Lay 1   Example of MFMLMP Reticles: Layer 2 of Die 1
                             and Die 2 cannot share the same reticle
September 28, 2006                     GSRC Annual Symposium
                                                                                      16
                 GSRC On-Line MFMLMPR Designer
•      Flexible: Handles all known practical design constraints
•      Fast: Interactive solver to minimize manufacturing costs
•      Graphical viewing of output
•      Co-developed with, used at Cypress Semiconductor for MFMLMP Reticle design




     Define Parameters               Input Data                  Output
    September 28, 2006                   GSRC Annual Symposium
                                                                                    17
             Roadmap for Physical Implementation QOR
• Delay, Power: large part in interconnect
    – Growing problem with every technology node
    – Spatial embedding becomes more critical
    – Unpleasant surprises at first spatial
      embedding
      (industry: many RTL designs are found
      infeasible)
• Early planning for distances, shapes and
  sizes
    – Manual planning has hit the complexity limit
    – System must co-evolve with its spatial
      embedding
    – Embedded memories, IPs, analog/RF, …
• Vertically-consistent spatial embedding
    – Consistent objectives and optimizations
      through multiple levels of abstraction
    – Smooth transitions between design steps,
      with gradual refinement
    – Support for design optimizations such as
      high-level and RTL synthesis
 September 28, 2006                      GSRC Annual Symposium
                                                                 18
             Vertical Consistency (1)
•   SCAMPI: SCalable Advanced Macro Placement
    Improvements
     – Variety of macro sizes & shapes
     – Look-ahead, macro clustering,
       obstacle evasion
•   Floorist:
    Floorplan Assistant
    (constraint-driven FP repair)




                           red: overlap




                            blue: block
                            movement
                            (no overlap)
September 28, 2006                         GSRC Annual Symposium
                                                                   19
             Vertical Consistency (2)

•   Physically safe logic restructuring
•   Top-down whitespace & buffer area allocation




•   Support for design optimizations
    via selective re-embedding (below)
•   More direct optimization of routed net lengths                (ROOSTER), at
    several design steps




                            Legalize


                            Improve


September 28, 2006                        GSRC Annual Symposium
                                                                              20
             SLLR Theme Posters
•   Parametric Yield Estimation and Optimization
     –   Eric Karl, Dennis Sylvester and David Blaauw: Multi-Mechanism Reliability Modeling and
         Management in Dynamic Microprocessor-Based Systems
     –   Scott Hanson, Dennis Sylvester and David Blaauw: A New Technique For Jointly Optimizing Gate
         Sizing and Supply Voltage in Ultra-Low Energy Circuits
     –   Saumil Shah, Dennis Sylvester, Andrew Kahng and Youngmin Kim: Intra-Gate Channel Length
         Biasing for Transistor-Level Circuit Optimization
•   Roadmap of Reliability
     –   Bin Zhang and Michael Orshansky: Evaluating Reliability of On-Chip SRAM Arrays using Dynamic
         Stability Analysis
     –   Rajeev Rao, Vivek Joshi, David Blaauw and Dennis Sylvester: Efficient Soft Error Rate
         Computation and Circuit Optimization Techniques to Mitigate Soft Errors in Combinational Logic
     –   Wei-Shen Wang and Michael Orshansky: Yield Estimation under Realistic Descriptions of
         Parameter Uncertainty
•   Roadmap of Cost
     –   Andrew Kahng and Xu Xu: A General Framework for Multi-Flow Multi-Layer Multi-Project Reticle
         Design
•   Roadmap of Physical Implementation QOR
     –   Jarrod Roy and Igor Markov: Vertically-Consistent Spatial Embedding of Integrated Circuits and
         Systems
•   Roadmap of Power and Variability
     – Andrew Kahng, Swamy Muddu and Chul-Hong Park: A Scalable Auxiliary Pattern-Based OPC
       Strategy for Better Printability, Timing and Leakage Control
     – Andrew Kahng and Swamy Muddu: Design-Centric Modeling and Optimization of BEOL
       Interconnect Stacks
     – Andrew Kahng, Kambiz Samadi and Puneet Sharma: Study of Floating Fill on Interconnect
       Capacitance
     – Andrew Kahng and Kambiz Samadi: Nanometer Era CMP Fill for Variability Reduction
     – Andrew Kahng and Puneet Sharma: CMP Fill for Reduced STI Variability
     – Andrew Kahng and Swamy Muddu: Predictive Modeling of Systematic Intra-die Variability
     – Andrew Kahng and Rasit Topaloglu: Interconnect Optimization through Design Rule Generation
September 28, 2006                                   GSRC Annual Symposium
                                                                                                          21
             Toward System Scaling Theory
         Traditional Scaling                      Future Scaling
• Driven by min feature size         • Driven by system constraints

• Determinism: size directly      • Non-determinism: size impact
  impacts performance and density   mediated by power density,
                                    redundancy overhead, low yield,
                                    increased comm overhead
                                  • System-level overdesign and
                                    effective transistor density
                                     • Performance is achieved by multi-
• FO4-based performance metric
                                       core architectures running at lower
                                       frequencies
• Transistors are either logic or    • Adaptivity/reliability  many
  memory                               transistors are used to diagnose and
                                       tune
• Cost not discussed (e.g., design   • Power trades off with design time
  TAT, leakage current from Tox      • Impacts of concurrency, spatial
  scaling, …)                          embedding, application domain, …
 September 28, 2006                  GSRC Annual Symposium
                                                                         22
             Future: GSRC Modeling and Metrics SIG

• Enable system design to comprehend impact and feasibility of
  technology options
    – Variability, power, cost
    – Reliability, flexibility, resilience
• Initial focus: uncalibrated, “variational” scaling models
    – Priority: modeling requests from system-level design and GSRC
      sponsors
    – “X% increase in reliability requires Y% increase in power”?
    – “X% (transient + hard) fault coverage can be achieved with < Y% area
      overhead”?
    – How to measure efficiency and yield in the presence of failures?
    – Approximations + Abstractions  “block models” for system optimization
• Future system scaling is dominated by silicon non-idealities
    – Variability and reliability will fundamentally change density, power,
      speed, cost scaling laws
    – Long-term goal: a new system scaling theory
 September 28, 2006                          GSRC Annual Symposium
                                                                              23

				
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