# Viterbi Detector_ Review of Fast Algorithm and Implementation by malj

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```									Viterbi Detector: Review of Fast
Algorithm and Implementation

-Xiaohong Sheng
ECE734 Project
Viterbi Algorithm

Viterbi Algorithm:
The optimum decoding algorithm for convolutional code,
it can also be used for speech and character recognition
which is modeled by hidden Markov models
Receive     01        01        00        11            10
00   1   00    2    00    2 00     2       00    3
01                        00
1/11                                                        11        11    5 11             11
1/01                          11    1         2           4       2             3
01                              11
10               3 11            10
0/00   00    1/00        0/10     11                                     3     00
1/10                                         2        3             2
10                   01                                          Winner!
01        01
1                       3         3
0/01               11
10           10
0/11    10                                                        10    2
Detected: 00 00 00 11 10
Convolutional Code

Convolutional code
Widely used for digital communication
m
Cj             X
l 0
j l   Gl
Cj=[Cj1,Cj2]
Example: C  0,1
+      +

1 1
G0                                         Cj1
C j  X j 2 X j 1 X j 1 0
    G1                      Xj-1    Xj-2

1 1                    Xj
    G2

 X j 2  X j 1  X j X j 2  X j                   State
+         Cj2
Problems on Viterbi Algorithm

Computational complexity increases exponentially
with constraint length (state) of convolutional code
Nonlinear feedback loop in the VA presents a
bottleneck for High speed implementations
 Other issues such as:
Viterbi algorithm is a ML (optimum) algorithm if
Euclidean distance is used. The usually used Hamming
distance in VA is sub-optimum and therefore lose some
performance.
 If Euclidean distance is used, The use of multiplier
increases the decoder complexity significantly
Any Solution?
YES!
Two main solutions
Reduce state
• At least half of the states can be reduced for DPSK sources.
– Exciting! -Yes, Believe?-?, How? And any other problem can be
induced?
Pipeline
Solve the bottleneck of nonlinear feedback?
Others solutions like
Linear distance metric can be used
Select some special convolutional codes
Reduced state solution
DPSK sources
data communication system can be described as
When Xi(t) is oversampled by K, hi(t) lasts a
maximum of d symbol intervals and put all data from N
receivers in a vector, the signals can be modeled as:

Under the assumptions on: a)Si are
orthonormal, b) Noise is Gaussian

Use SVD

Use Mahalanobis
orthogonalization transform
Reduced state solution (Cont.)

 It can be proven that                ry( k )  rsk      Where:

So,
ryk Is affected by input data symbols [St, St-1…St-k-d+1]
So, the optimal detection can be defined by:

It can be achieved by VA to a M^(d+k-1) states, the original Rx optimal
detection achieved by VA has M^(d+k) states. Half of States is reduced
Pipeline Solution

Pipeline
M-Step Trellis+1-Step Trellis

Backward and forward Trellis
Other solutions

Use Linear Distances (For QPSK 8-PSK, 16-
QAM)
Avoid multiplication without losing the VA
decoder performance
Use doubly complementary convolutional
codes
Save 1/3 of real time operations over the VA with
a state grouping and partitioning of the trellis
Other issues I’m thinking...

Can we increase the decoder speed infinitely if we
have infinite hardware? If not, what’s maximum
speed we can achieve?
Is there optimal partitions given the size of the source
need to be decoded so that we can achieve maximum
decoding speed and use minimum hardware
Woo…, Really hard mathematical problem. And
Perhaps no solution
Interested these problems also?
Reference(1)
 [1]. Implementing the Viterbi algorithm, Lou, H.-L. IEEE Signal Processing Magazine ,
Volume: 12 Issue: 5 , Sept. 1995, Page(s): 42 -52
 [2]. A reduced-state Viterbi algorithm for blind sequence estimation of DPSK
sources,Tongtong Li; Zhi Ding Global Telecommunications Conference, 1999.
GLOBECOM '99 , Volume: 4 , 1999 ,Page(s): 2167 -2171 vol.
 [3]. A reduced state Viterbi algorithm for multiuser detection in DS/CDMA systems ,Wang
Zhaocheng; Ge Ning; Yao Yan; Qiang Wang Communication Technology Proceedings,
1996. ICCT'96., 1996 International Conference on , Volume: 2 , 1996 Page(s): 1102 -1105
vol.2
 [4]. Linear distances as branch metrics for viterbi decoding of trellis codes,Hut-Ling Lou
Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE
International Conference on , Volume: 6 ,Page(s): 3267 -3270
 [5]. A constraint-length based modified Viterbi algorithm with adaptive effort Feldmann, C.;
Harris, J.H. Communications, IEEE Transactions on, Volume: 47 Issue: 11 , Nov. 1999
Page(s): 1611 –1614
Reference(2)
 [6]. Complexity reduction of the Viterbi algorithm using doubly complementary
convolutional codes, Haccoun, D.; Caron, M.; Nabli, M. Communications, Computers and
Signal Processing, 1999 IEEE Pacific Rim Conference on , 1999 Page(s): 408 –411
 [7]. High-performance VLSI architecture for the Viterbi algorithm, Boo, M.; Arguello, F.;
Bruguera, J.D.; Doallo, R.; Zapata, E.L. Communications, IEEE Transactions on , Volume:
45 Issue: 2 , Feb. 1997 Page(s): 168 -176
 [8]. Pipelined architectures for the Viterbi algorithm, Boo, M.; Brugera, J.D. TENCON '97.
IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and
Telecommunications., Proceedings of IEEE , Volume: 1 , 1997 Page(s): 239 -242 vol.
 [9]. A high speed Viterbi decoder using path limited PRML method and its application to 1/2
inch HD full bit rate digital VCR, Hara, M.; Yoshinaka, T.; Sugizaki, Y.; Ohura, S.
Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. Page(s): 96 -97
 [10]. Novel Viterbi decoder VLSI implementation and its performance, Kubota, S.; Kato, S.;
Ishitani, T. Communications, IEEE Transactions on, Volume: 41 Issue: 8 , Aug. 1993
Page(s): 1170 –1178
 [11], "A 1-Gb/s, four-state, sliding block Viterbi decoder," P. J. Black, T. H.-Y. Meng, IEEE
J. Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 797-805

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