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7.7 Peak Hold Circuit with Monolithic Transconductance Amplifier

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					7.7   Peak Hold Circuit with Monolithic Transconductance Amplifier
    a
J. G´l, Gy. Hegyesi

    Peak hold circuits play an important role                         two charging diodes (D2,D3), and negative
in most high resolution spectroscopy ADC sys-                         feedback is applied to the amplifier through
tems. They are designed to track an analogue                          the high impedance output buffer (U2). Un-
input pulse, capture the maximum amplitude                            der this condition, the circuit works as an in-
and keep that peak value on a hold capacitor.                         verting amplifier. The rise time of the input
Traditional peak hold circuits use voltage am-                        pulses can be as short as 80 ns. The feedback
plifiers to charge the hold capacitor through a                        circuit brakes immediately after the input goes
nonlinear device (e.g. diode). In order to main-                      through a maximum level and starts decaying.
tain linearity, a feedback loop must encompass                        The circuit then enters hold mode.
the diode - hold capacitor path through an
                                                                          In this mode, the first charging diode (D2)
output buffer. The output impedance of the
                                                                      is reverse biased and the voltage across the
voltage amplifier and the dynamic impedance
                                                                      hold capacitor is held equal to the maximum
of the diode make up the resistance which, to-
                                                                      level. The leakage currents of the components
gether with the capacitor, determines the feed-
                                                                      connected to the hold capacitor cause it to dis-
back loop pole. As the input signal approaches
                                                                      charge. The rate of this discharge is the droop
its maximum value, the diode’s current goes to
                                                                      rate of the circuit. A boot-strap circuit (R5,
zero, increasing its dynamic impedance. That
                                                                      D3) in the input stage of the output buffer am-
introduces a loop stability problem. The neces-
                                                                      plifier, minimizes the droop error which occurs
sary compensation to stabilize the circuit, how-
                                                                      during periods of long peak-hold duration.
ever, will make it useless in high speed appli-
cations. The peak hold circuit that we present                            The hold capacitor could be intentionally
in this report replaces the input voltage ampli-                      discharged by enabling the reset circuit (R6,
fier with a monolithic transconductance ampli-                         HOLD/TRACK Switch) within the circuit. If
fier. A description of the circuit’s operational                       the discharge rate of the hold capacitor is
modes follows.                                                        higher than the decay rate of the input signal,
    During the rise time of a negative input sig-                     the output of the circuit will follow (track) the
nal, the hold capacitor (C1) is charged through                       input even when the signal is decaying.
                   R1                                            R2
         Input
                               U1B

                                        1/gm
                                1




                                                                                R5
                               U1A                    V+                                  V+

                                i                                                              U2
                                               i
                                        1/gm                          D2   D3                           Output
                                                    25k
                                    1
                                                                                R6   C1
                                                           D1
                                IQ ADJ                                                    V-
                          R3
                                               R4
                                                                       HOLD     TRACK

                                                      V-



                                                            78

				
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posted:7/22/2011
language:English
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