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PLD Basics

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					                PLD Basics




September, 00
1
                    Agenda


                Basic Logic Tutorial


                 Gal / Architecture


                CPLD / Architecture


                        ISP


                     Software


                    Packaging




September, 00
2
                Digital Logic Tutorial




September, 00
3
                                   Key Poitns



    • Digital Logic Uses Only Two Values: 1 and 0


    • 1 and 0 usually represent a voltage


    • Example
           – Digital 1 = 5 volts
           – Digital 0 = 0 volts



    OR
           – 1 = ON, 0 = Off
           – 1 = True, 0 = False




September, 00
4
                            Boolean Basics


    • Manipulation of digital values is done by Boolean Algebra




    • Boolean algebra uses primarily AND / OR functions




    • Boolean equation: TRUE OR FALSE = TRUE




    • Programmable logic implements the AND / OR functions in
      hardware




September, 00
5
                                       Basic Gates

    • A gate performs a logic function in hardware


    • Three basic PLD gate types
          – AND gates

          – OR gates

          – Exclusive-OR (XOR) gates



    • Gates can have any number of inputs




September, 00
6
                                  AND Gate Example


    • Output of an AND gate is TRUE only if all inputs are TRUE
           – In a 2 input gate both switches must be on to turn the light on




                OFF                                           ON
                OFF                                           OFF
                               OFF                                             OFF




                OFF                                           ON
                ON                                            ON
                               OFF                                             ON




September, 00
7
                                      Or Gate Example

                      • Output of OR Gate Is TRUE if ANY Input is TRUE
                              – If Either Switch Is ON, The Light Will Trun ON




                OFF                                           ON
                OFF                                           OFF
                                OFF                                              ON




                OFF                                           ON
                ON                                            ON
                                ON                                               ON




September, 00
8
                                 XOR Gate Example

                 • Output of XOR Gate Is TRUE Only of One Input Is TRUE
                           – If Only One Switch Is ON, The Light Will Turn ON




                OFF                                        ON
                OFF                                        OFF
                              OFF                                               ON




                OFF                                        ON
                ON                                         ON
                               ON                                               OFF




September, 00
9
                Basic Gates Summary

                        Truth Table
                             (OFF-0, ON-1)

                      SW1        SW2         Light
                       OFF       OFF         OFF
SW1                    OFF       ON          OFF     Light = SW1 * SW2
                       ON        OFF         OFF
SW2                    ON        ON          ON




                      SW1        SW2         Light
                       OFF       OFF         OFF
SW1                    OFF       ON          ON
                                                     Light = SW1 # SW2
                       ON        OFF         ON
SW2                    ON        ON          ON




                      SW1        SW2         Light
                       OFF       OFF         OFF
     SW1               OFF       ON          ON
                                                     Light = SW1 $ SW2
                       ON        OFF         ON
     SW2               ON        ON          OFF



September, 00
10
                                      PLD Symbols

 • AND Gate Representations

                                           A
           – Traditional Representation    B               D
                                           C



                                           Input Terms
                                               A   B   C
           – PLD Representation

                                                               D




 • PLD Connections

           – Hardwired Connection

           – Programmed Connection

           – No Connection Made

September, 00
11
                         Typical PLD Structure

Input Terms             Product Terms
  A    B    C    D




                                           A
                                           B
                                           C
                                                 Output

                                           B

                                           D




                     Output


 September, 00
 12
                     Registers and Clocks


 • Registers Store a Digital Value
 • Values Move From Input To Output With Clock Transition
 • D = Incoming Data
 • Q = Outgoing Data
 • CLK = Clock Input; Causes Data Movement




                                       CLK   D      Q
                D      Q                0    0      0
                                        0    1      0
                                             1      1
                                        0    0      1
                                             0      0

 CLK

September, 00
13
                       Typical GAL Logic Structure

Input Terms              Product Terms
     A   B   C   ...
                                                          Output Enable


                                  Registered or
                                  Combinatorial

                                                  D   Q




                                             Feedback


September, 00
14
                Basic GAL Structure


                              Macrocell


                              Macrocell


                              Macrocell


                              Macrocell
                                          Gal Macrocell
                              Macrocell


                              Macrocell


                              Macrocell


                              Macrocell


September, 00
15
                           GAL Devices



 • Low density GAL product families: 16/20V8, 18/22V10/26V12,
   20RA10, 20XV10, 6001/6002. Families are organized based on
   architectural layout and a common Output Logic Macro Cell
   (OLMC). Pin counts and array sizes are all that change across a
   family.


 • Lattice GAL devices have Macro Cell counts from 8 to 39 and
   package sizes from 20 pins to 28 pins.


 • All GAL devices have registered or combinatorial options, OE
   control, and selectable output polarity.




September, 00
16
                                         GAL Devices



 • There are also various flavors of each device type.
           –    An L in the product name is a low voltage (3.3V) device.
           –    Zero power devices are either Z or ZD, such as 22LV10ZD.
           –    A VP indicates high drive outputs, such as the 16VP8.
           –    The ispGAL16Z8 was the worlds first ISP PLD.
           –    There is also a Confusion Letter, which roughly indicates the process and
                technology that the device is based on.



 • Appended to each device type are speed, power, package, etc.
           – Device speed grades are by TPD in ns. (HD devices are graded by Fmax in MHz.)
           – Power dissipation (standard, Low, and Quarter), package type (Pdip, Jlcc, Soic),
             and Temp/VCC range are appended to device names such as 16LV8C-5LJI for 5nS,
             low power, PLCC, Industrial.




September, 00
17
                                       PAL Vs. GAL


 • PAL:
           – Programmable Array Logic.
           – Registers, feedback paths, dynamic I/O, and both output polarities are available.
           – There are dozens of different devices each with a fixed architecture. For
             example, a PAL16H2 has 16 inputs and 2 combinatorial outputs each with 8 PTs
             per OR gate. Output polarity is positive.



 • GAL:
           – Generic Array Logic.
           – GALs are a superset of PALs. A few GAL devices cover all PAL architectures and
             hundreds of other possible configurations.
           – GALs add extremely flexible routing and complete reconfigurability.
           – The structure of GAL devices allows them to replace many PALs with various IO,
             input and register counts. Therefore, extra programmable areas known as
             architecture rows are needed for device configuration. There are global
             configuration modes and well as individual MacroCell options.




September, 00
18
                High Density Logic Overview




September, 00
19
                            ispLSI Heritage




 • The ispLSI Architecture Has Its Origins In The GAL Family
 • The Best Features Of The GAL Family Have Been Blended Toghter


           –    GAL16V8:    Output Logic Macrocell (OLMC)
           –    GAL22V10    More Product Terms
           –    GAL20XV10   Exclusive OR Gate (XOR)
           –    GAL20RA10   Asynchronous Clocking
           –    GAL6002:    Input Registers and Product Term Sharing




September, 00
20
                CPLD Structure

                Modified Gal Structure




                Global Routing Pool
                   (Interconnect)




September, 00
21
                               ispLSI Archtiecture

           Key GAL Features



 16V8     22V10 20XV10     20RA10    6002
  Prog. Variable XOR       Asynch Prod. Term
Macrocell Product           Clocks Sharing/
           Term                     Input
          Distribution             Registers




                  ispLSI
                   GLB


                18XVRA4



September, 00
22
                               High Density Structure

 • Simple Lattice definition: High Density (HD) devices are those with
   1000 or more PLD gates and packages exceeding 28 pins. Our HD
   devices are Complex PLDs (CPLDs).
 • HD devices are essentially many identical GAL sized blocks that are
   repeated to form larger devices.
 • There is a portion of the device dedicated to routing signals
   between logic blocks called the Global Routing Pool (GRP)
 • In GAL terms, the basic GLB (1K, 2K families) is a fancy 18V4.
           – The logic in the GLB contains most of the features available in the entire GAL
             family, but on a smaller, more limited scale.
               » PT clocking
               » XOR functions
               » 20 wide OR
               » PT reset
           – Much of the logic is mutually exclusive and gets „burned‟ as other logic is used.
             This is overcome by having many GLBs.




September, 00
23
                              High Density Structure


 • Megablock/Megacell based.
           – A Megablock contains 8 GLBs.
           – Devices in a family are built from whole Megablocks.



 • The Global Routing Pool (GRP) is the only means to get signals
   from one GLB to the next and to get the IO cells to the GLBs.


 • External pins such as CLK pins, RESET, and GOE are globally fed
   to all GLBs.


 • The only other global signals are internally generated clocks and
   OE‟s (differ by family and device).




September, 00
24
                CPLDs and FPGAs




September, 00
25
                           High Density Logic Overview

                     FPGA                             HDPLD or CPLD
                                                             A          B




                                                             C




 •     Field Programmable Gate Arrays             •   High-Density or Complex PLDs
           – Small Logic Building Blocks               – Large Logic Building Blocks
           – Register Intensive                        – PLD-Like Ardchitectures
           – Distributed Interconnect                  – Centralized Interconnect



           – Slow, Unpredictable, Performance          – Fast Predictable Performance
           – Good at “Narrow Gating” Funcitions        – Good at “Wide Gating” Functions
                » Datapath                                  » State Machines
                » Random Logic                              » Coutners



FPGAs and CPLDs Can Compliment One Another In the Same Design!

September, 00
26
                                 Major PLD Suppliers



                     FPGAs                                   CPLDs

        Company         Family       Technology   Company     Family   Technology
            Altera       10K           SRAM        Lattice     1K          E2
                          8K           SRAM                    2K          E2
                          6K                                   3K          E2
                        Apex           SRAM                    5K          E2
            Xilinx      XC2K           SRAM                    6K          E2
                        XC3K           SRAM                    8K          E2
                        XC4K           SRAM                   GDX          E2
                     XCS (Spartan)     SRAM                   GAL          E2
                        Virtex         SRAM                   GDS          E2
                                                              Mach         E2
                                                   Altera      7K          E2
                                                               9K          E2
                                                   Xilinx     9500         E2




September, 00
27
                     Technology Comparisons



 Feature                     E2CMOS   Flash   SRAM         Antifuse
 Reprogrammability            Yes      Yes     Yes           NO
 In-System Programmable       Yes      Yes     Yes           NO
                                              (Volatile)

 Program Time                 Fast     Med.    Fast          Slow
 Erase Time           Fast    Slow     Fast    N/A (OTP)
 Testability                  Full     Full    Full          Limited
 External Hardware            No       No      EPROM         Pgmr
 Other                                         Start up
                                               Delay




September, 00
28
                The GDX




September, 00
29
                              Multiplexer

                                             (1)
                                     IN A
                                                                   Output
 • Commonly called a MUX                    (0)
                                     IN B


 • An electronic selectable
   switch
                                            Control (1 or 0)

 • Simplest Form: 2 inputs, 1
   output, and 1 control


 • GDX(V) Building blocks: 4




                                            Mux
                                                        Register
   inputs, 1 output, 2 control




September, 00
30
                        ispGDX/V Functional Diagram




• Simmilar to CPLD                                                          I/O Cell Bank D

          – Centralized Routing Pool                                                           ISP
                                                                                              Control


              » Consistent timing
          – Non Volatile
          – Registers available on output




                                               I/O Cell Bank A




                                                                                                        I/O Cell Bank A
          – Small ammounts of logic possible                                    Global
                                                                                Routing
                                                                                  Pool
                                                                                 (GRP)




• Specialized Functionality                                      Boundary
                                                                   Scan
                                                                  Control


          – Dynamic routing of signals                                      I/O Cell Bank B

          – No dedicated logic




September, 00
31
                 BFW in Crosspoint Switch Application

         System-level                        Logical                     CPLD
        Representation                    Representation             Implementation
     (2 X 2) x 1 bit Switch                                           Sel1 Sel0   B   A
                                            A
                                                       C
                                            B
                                                                                              A to C
                                                                Pt    X     0     X       A            P
         1                                                                                             T
                      1                         Sel0                                          B to C       C
     A                           C                                    X     1     B       X            S
                                                                                                       A
         1            1
     B                           D          A                         0     X     X       A   A to D   P
                                                       D                                               T
                                            B                                                              D
                                                                      1     X     B       X   B to D   S
                                                                                                       A

                                                Sel1
                                                               • One PT Per Input Port
                                                           • One Macrocell Per Output Port
             GDX/V Implementation
                  A                      • One Mux Input Per Input Port
                                     C
                  B                          • 4 Input Ports Max. Per GDX
                                             • 16 Input Ports Max. Per GDXV
                          Sel0
                                         • One I/O Cell Per Output



September, 00
32
                         Telecom Aplications (PDP)

                                  Input Registers
                1
                     Channel 1
                     Channel 2                      4:1
                     Channel 3                      MUX
                     Channel 4


                5
                     Channel 5
                     Channel 6                      4:1
                     Channel 7                      MUX
                     Channel 8                                  Register

                                                          4:1
                                                                Bypass     1…16

                9                                         MUX
                     Channel 9
                     Channel 10                     4:1
                     Channel 11                     MUX
                     Channel 12



                     Channel 13
                     Channel 14                     4:1
                16   Channel 15                     MUX
                     Channel 16




 • Multiplex 16 Slow-Speed Channels Into A Single High-Speed
   Channel
 • 1 Level in GDXV


September, 00
33
                        Crosspoint Switching Application

Backplane Controller
                                            • 8000/V
                  • GDX/V        Control
                                            • 5000V        Functions Performed:
                                            • 2000E/VE
                                                           • Cross Connect Data
     Backplane                                               From One Source To
                                                             Another
                                                           • Perform Arbitration
                Line Line     Line         Line     Line   • Generate Switching
                Card Card     Card         Card     Card     Control

                                       • 8000/V
                                       • 5000V
Switch Controller            Control   • 2000E/VE
                                                                    Mem

                   • GDX/V
                                                                            ASIC
                                                             CPU
                                                                            ASSP


                                                                     BUS
                  Line Line        Line      Line
                                                                      I/F
                  Card Card        Card      Card

September, 00
34
                In-System-Programmable
                         (ISP)




September, 00
35
                             Historical Programming


     Originally all programming had to be done in a separate piece
                              of hardware


 • One Time Programmable (OTP)
           – Antifuse technology
           – Not erasable

 • Erasable PLDs (EPLDs)
           – UV light used to erase device
           – Expensive packaging

 • Electrically Erasable PLDs
           – Could be erased by programming equipment
           – Had to be removed from circuit for both programming and erasing
           – Uses High (~12v) voltages to program




September, 00
36
                             In-System-Programming



 • ISP PLDs

           – Programming and erasing done through a wire interface to the part
               » Programming voltages generated “on chip”

           – Part can be soldered to the board
               » No need to handle parts
               » More delicate (smaller) packaging can be used

           – Field upgrades are possible

           – Multiple / different devices can be programmed at once




September, 00
37
                           Two ISP programming algorithms


     • Lattice ISP
                – Invented by Lattice
                – Five wire interface
                – Three state state-machine



                   –SDO
                     –SDI          –5-wire Lattice ISP
                       –MODE       –Programming
                        –SCLK      –Interface
                          –ispEN




                                                         –ispGAL   –ispGDS   –ispLSI
                                   –ispLSI                –22V10      –22     –2032
                                   –1032E




September, 00
38
                                          ISP Functionality


 • JTAG / Boundary Scan
           – Pseudo standard across vendors
           – Four wire interface
           – 16 state state-machine




                    –TDO      –4-wire ispJTAG
                     –TDI     –Programming
                       –TMS
                         –TCK –Interface




                                                          –VCC

                                           –BSCAN/ispEN


                                                                                   –ispEN
                                                                 –Non-Lattice
                                        –ispLSI                   –BSCAN        –ispLSI
                                        –3256A                     –Device      –2032V




September, 00
39
                                         Mixed Programming

 • Mixed Programming
           – JTAG and Lattice ISP are incompatable if used is the same chain (in series)
           – Parallel sharing of signals is possible



                  –TDO/SDO         –5-wire Lattice ISP and
                    –TDI/SDI       –ispJTAG Mixed
                     –TMS/MODE
                       –TCK/SCLK   –Programming
                          –ispEN   –Interface




                               –ispLSI                          –ispLSI              –ispLSI
                                –2032                           –1032E                –2128




                                                         –VCC

                                          –BSCAN/ispEN



                                                                                               –ispEN
                                                                      –Non-Lattice
                                     –ispLSI                                             –ispLSI
                                                                        –BSCAN
                                     –3256A                             –Device          –2032V




September, 00
40
                ISP Innovator
                     and
                Market Leader




September, 00
41
                                     Industry Shaping Innovations



                                                                        Lattice
                                                                   introduces Cell
                                  Lattice
                                                                   Based PLD with
                                introduces
                                                                       Memory
                               the ISP GAL



                                                          ispLSI
                                                           1000
                        1986                                                                1996           1999



                1985                                       1992                                     1997




                                             Lattice invents
                                                                                                                  TODAY
                                             the ISP CPLD                                                  Lattice Invents
                   Lattice invents
                      the GAL                                                  Lattice Introduces           the ISP PAC
                    Architecture;                                               the ISP Generic            Programmable
                     introduces                                                Digital Crosspoint              Analog
                      E2CMOS




September, 00
42
                Historical Market Overview

 • Circa 1985   Lattice           GAL22V10

 • Circa 1990   Xilinx            3042

 • Circa 1993   Altera            7032, 7128

 • Circa 1996   Altera/Xilinx     10K/4000

 • Circa 1998   Lattice BFW       2KVE, 5KV, 8KV




September, 00
43
                    Company Background




 • Lattice is the Inventor of In-System-Programmable PLDs

 • The PLD Performance Leader

 • World‟s Largest Supplier of ISP PLDs

 • Fastest Growing CPLD Supplier

 • Broadest Line Supplier




September, 00
44
                Lattice Device Packages




September, 00
45
                Space-Saving Packages With ISP Devices




                       Plastic BGA    Plastic QFP
                           TQFP      SuperBGA SSOP

                  ISP Enables the Use Of Space-Saving
                        TQFP & BGA Packages!
September, 00
46
                                          Lattice Packaging Roadmap
                                             QFP
                                             (.50-.80mm)



                                    3.5

                                    3.0
                (mm)


                                    2.5
                Package Thickness




                                    2.0

                                    1.5

                                    1.0                    TQFP
                                                           (.40-.80mm)


                                    0.5
                                                                                              (.xxmm) = Lead Pitch




                                             1992          1994          1996   1998   2000     2002


                                                                         YEAR



September, 00
47
                Software Basics




September, 00
48
                                Start To Finish


        Concept



                  Design Entry
                  Schematic or HDL




                                     Design Synthesis
                                 3rd Party Tools or Lattice




                                                          Place and Rout
                                                              Lattice Fitter




                                                                               Download to Part



September, 00
49
                                 Design Entry Methods


     Schematic
                a                     • Schematic is used to capture structural
                b
                                        models using IC vendor-supplied logical
                                        gates and other macro functions
                                      • Used for designing PLDs, CPLDs, FPGAs, and
                                        ASIC




     HDL
                                      • HDL (Behavioral) models differ from
     ..
     process
                                        structural models in that there is no one-to-
     begin                              one correspondence between expressions
           carry <= (a and b);          and logic gates
           sum <= (a xor b);
     end process;                     • Enables programmable description of circuits
                                        and systems



September, 00
50
                               Mixed Schematic-HDL Entry

     Schematic Drawing
                                                         • Schematic is used to
                                                           capture structural view
                        4_ADDER                            using IC vendor-supplied
                                                           logical gates

                                                         • HDL is used to capture
                                                           behavioral models for
                                                           one or more functional
                                                           blocks

     ......
     process                           Technology Dependent
     begin                             Logic Primitives/Gates
              carry <= (a and b);
              sum <= (a xor b);
     end process;
     ........

     HDL Description of 4_ADDER




September, 00
51
                 Schematic-Based
                Design Methodology




September, 00
52
                     Lattice Schematic-Based Design Flow
                                                Schematic and
                  Schematic                    Symbol Libraries



        Functional Simulation
                                              Simulation Libraries   • Technology Dependent
                                                                         IC Vendor Specific
                  Netlister                                              Libraries
                                                                        No FPGA/CPLD/ASIC
                                                                         Retargetability
                EDIF Netlist

            Logic Optimization               ispEXPERT Design
             Device Mapping                  Environment
                                                                       Lattice Design Solutions:
                                                                            • ispEXPERT+Mentor
                Placement &                                                 • ispEXPERT+Cadence
                   Route                                                    • ispEXPERT+OrCAD
                                                                            • ispEXPERT+Viewlogic
                                                     Timing                 • ispEXPERT+Synario*
                  Timing                           Simulation               * Data I/O Supplied Technology
                 Simulation                         Libraries               Independent Symbol Library



            Lattice Semiconductor Supplied



September, 00
53
                           Schematic-Based Design Flow

                                       Lattice Semiconductor Proprietary Functional
                                              Macros - Technology Dependent




                                  Optimization                            ispEXPERT
                    Lattice
                Semiconductor
                  Proprietary
                  Schematic
                    Library


                                                            Technology         ispLSI Devices

                                                             Mapping




September, 00
54
                    HDL-Based
                Design Methodology




September, 00
55
                        HDL-Based Design Phases


                  Models
     Idea          (HDL           HDL       • A model is an abstraction
                Description)   Simulation     i.e. a representation that
                                              shows relevant features of a
                                              design.
                                            • Design Synthesis and
                Translation
                                              Optimization takes detailed
                    and                       specifications of a design
                Optimization                  from the design model and
                                              optimizes key parameters
                                              such as performance and
                                              area.
                               Gate-Level
                  Netlist      Simulation   • Simulation is performed to
                                              remove all possible design
                                              errors.




September, 00
56
                                     What is HDL?



 • Hardware Description Language. The term model in HDL is
   analogous to the term program in software.


 • Language that enables description of circuits and systems


 • Examples:
           – Verilog-HDL - Verilog-HDL is a hardware description language (Cadence/OVI
             Standard) which provides a means of specifying a digital system at a wide range
             of levels of abstraction.
           – VHDL - Acronym for VHSIC hardware description language (ANSI/IEEE Standard).
             VHDL is a hardware description language which provides a means of specifying a
             digital system at a wide range of levels of abstraction.
           – Abel - Originally from Data I/O




September, 00
57
                                            Design Synthesis



 • HDL Synthesis - Transformations of HDL Models to microscopic
   (i.e., gate-level) structure of a design.




 • Logic Synthesis - Consists of two separate phases called Logic
   Optimization and Technology Mapping.

           –    Logic Optimization - The role of optimization is to enhance the overall quality of the design, such as
                performance and area.


           –    Technology Mapping - Transformation of the optimized design into a design that consists of restricted
                set of elements. In the CPLD environment, the elements are I/O and GLB cells.




September, 00
58
                                 Design Synthesis

      Synthesis = Translation + Optimization
     architecture data_flow of
     xgen is                     Technology Independent
     ....
     if (s1=1) then
           xref <= a and b;
     else
           xref <= a or b;
     z <= xref when not s0                                Technology Dependent
           c when s0;
     end data_flow;

                Translation



                                           Optimization




September, 00
59
                              Lattice HDL-Based Design Flow

                VHDL/Verilog-HDL
                  Description
                                                     Functional
                                                 Simulation Libraries
                                                                        • Technology Independent;
      VHDL/Verilog Simulation                                             FPGA/CPLD/ASIC
                                                                          Retargetability
                                                      Synthesis
                    Synthesis                         Libraries


                                                                        • Supports Top-Down Design
                  EDIF Netlist
                                                                          Methodologies
            Logic Optimization
             Device Mapping                       ispEXPERT Design
                                                  Environment
                                                                         Lattice Design Solutions:
                  Placement &                                                 • ispEXPERT+Viewlogic
                     Route                                                    • ispEXPERT+Mentor
                                                                              • ispEXPERT+Cadence
                                                       Timing                 • ispEXPERT+Synopsys
          Verilog/VHDL Timing                        Simulation
                                                      Libraries               • ispEXPERT+Exemplar
               Simulation

                Lattice Semiconductor Supplied



September, 00
60
                            HDL-Based Synthesis Design Flow
architecture data_flow of
xgen is                      Technology Independent
....
if (s1=1) then
         xref <= a and b;                             Lattice Semiconductor Proprietary Functional
else
         xref <= a or b;                                     Macros - Technology Dependent
z <= xref when not s0
         c when s0;
end data_flow;




         Synthesis
                 +
            Lattice
        Semiconductor                      Optimization                                 ispEXPERT
          Proprietary
          Synthesis
            Library




                                                                          Technology        ispLSI Devices

                                                                           Mapping




 September, 00
 61
                 Mixed HDL-Schematic Based Design Flow
architecture data_flow of
xgen is
....




                                   Synthesis
if (s1=1) then                                         Lattice
         xref <= a and b;                          Semiconductor      Lattice Semiconductor Proprietary
else
         xref <= a or b;
                                               +     Proprietary
                                                     Synthesis
                                                                   Functional Macros - Technology Dependent
z <= xref when not s0                                  Library
         c when s0;
end data_flow;




                                                        Optimization                            ispEXPERT




                                                                                  Technology        ispLSI Devices

                                                                                   Mapping

                                Lattice
                            Semiconductor
      Schematic               Proprietary
      Capture                 Schematic
                                Library




 September, 00
 62
                         Design Verification Overview

                Design Verification (Simulation) is performed to
                      remove all possible design errors

 Types Of Design Verification and Their Definitions

 • Technology Independent Functional Simulation
           – Performed Prior to Design Synthesis or Compilation
           – Verifies Only That The Design Performs As Logically Expected

 • Technology Dependent Functional Simulation
           – Performed After Design Synthesis Or Compilation and Targeted Toward a Specific
             Silicon technology
           – Verifies Only That The Design Performs as Logically Expected

 • Technology Dependent Timing Simulation
           – Performed after Device Fitting / Compilation and Targeted Toward A Specific
             Silicon Technology.
           – Verifies That Both Logic AND Timing Requirements For The design Have Been Met




September, 00
63
                ispEXPERT and Third Party Design Systems
 • Synplicity
           – Synplify
               » VHDL and Verilog
                   Synthesis
           – Edit Window
           – Lattice Simulator
           – Lattice Project Navigator
           – Lattice Schematic and
             ABEL

 • Viewlogic
           – Synopsys FPGA Express
               » VHDL and Verilog
                 Synthesis
           – Workview Office
               » Schematic Entry
               » Timing Simulator
               » Project Navigator
               » Intelliflow




September, 00
64
                                 Download Software



 Lattice Provides Several Methods of Programming Parts
 • ISP Code
           – Allows a Microprocessor to program device directly

 • ISP VM (Virtual Machine)
           – Software That Can Program Lattice Devices As Well As Our Comptetitor

 • ISP ATE (Automated Test Equipment)
           – Allows The Customers Test Equipment To Program Our Device

 • Turbo Download
           – Allows Multiple - Different Lattice Devices to be Programmed Simultaneously

 • ISP DCD (Daisy Chain Download)
           – PC / Workstation Based Software With Simple GUI (Graphical User Interface)




September, 00
65
                                ISP DCD Software

 • Interrogates Hardware Setup
           – Reads Devices in Chain
           – Displays Part Name And Order On Screen
           – Checks Cable Connection and Power

 • Builds Datastream From Fitter Output
 • Shifts Data Into Device




September, 00
66
                  ispEXPERT Design Tool Options
                            Third-Party Environments (Open Systems)
                   • Viewlogic (OEM)       • Aldec      • Cadence                         Concept
                   • Synopsys (OEM)        • Veribest   • Mentor Graphics
Design             • Synplicity (OEM)      • OrCAD      • Exemplar Logic
Entry / HDL
Synthesis
                     Lattice - Schematic Editor         Synplicity - Synplify         ispEXPERTTM
                       & ABEL-HDL Compiler           VHDL and Verilog Synthesis          System

                         ispEXPERTTM Compiler
                        Lattice Semiconductor HDL               ispGDXTM System
                    Synthesis-Optimized Logic Compiler
Device                                                              Lattice-HDL
Fitting &
                     Lattice - ispTATM & Physical Viewer
Debug
                                                                 Auto Place & Route
                         Lattice - ispANALYZERTM


                           Lattice Gate-Level Functional and Timing Simulator
Design
Verification
                          Synopsys/Viewlogic, Cadence, OrCAD, Mentor Graphics,
                  Aldec, VeriBest, Model Technology (and other OVI and VITAL compliant)
                                     Functional and Timing Simulators

ISPTM
                         Turbo ispDOWNLOADTM ispATETM ispSVFTM ispCODETM
Programming



  September, 00
  67
                PLD Usage




September, 00
68
                                   How PLDs are Used

 Low Density (GAL)
 • Anywhere a small amount of logic is needed
           –    Glue Logic
           –    Address decode for processor memory
           –    Simple I/O signal decode
           –    Simple State Machines / Counters



 High Density
 • Can Consolidate Groups of Low Density Into a Single Chip
 • Can Implement Large Functions / Systems
           –    Bus Arbitration
           –    Processor Control
           –    Error checking Functions
           –    Signal Processing
           –    Adders
           –    comparators
           –    Graphics


September, 00
69
                              Where PLDs are used

 PLDs Can Be Found in Most Major Electronics Industries
 • Datacom / Telecom
           –    Switches
           –    Routers
           –    Hubs
           –    Modems
           –    CDMA/TDMA

 • Peripherals
           – Printers
           – Scanners
           – Fax Machines

 • Processing
           – Embedded processors / Single board computers

 • Industrial
           – Equipment Controllers

 • Data Acquisition


September, 00
70
                         BFW PLD Applications

                                       2KE       5K         8K          FPGA
                                                                          FPGA

                                      2KE                        ASIC


                         ASSP                                    2KE
                                     ROM
                Memory




                                                                           Chip
                                                           GDX             Set
                                       Micro-
                                5K   Processor
                                                      5K

                                                                 8K
                          8K



                                     SPEED


                                     DENSITY




September, 00
71
                            BFW in Communications Equipment

                                                    Modem
                IBM Compatible        Workstation



                                 Switch                                                                        Wireless base station
                                                                                                   ATM/SONET
                                                               T1 Line                                          T1 or Microwave
                                      Router CSU/DSU
                  IBM laser printer
                                                                                Central Office
                                                             xDSL
                          Ethernet Hub                                                              ATM         WAN

                                          NIC

                                                                                                        T3
                  IBM Compatible                                                     DSLAM
                                          Workstation


                                                                                          Multiplexor
                                       Telephone
                                                                    T1 Line

                             Telephone PBX

                                                Office
                                                        T1

                       Remote Access                                          Central Office     Frame Relay


                  Frame Relay Access Device
     Internet Service Provider                                                   Wide Area Network (WAN)

September, 00
72

				
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