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					      VELO Upgrade Critical Issues
•Two step upgrade with installation around 2013/2017
•Implies a detector which can sustain 5/20/120 fb-1
    •Very tight schedule

40 MHz readout implies complete replacement of all modules and
considerable modifications to the signal chain
• RF foil a major component of the system -> Can we keep it?
• Can we keep the cooling interface?
    •cooling pipes and the connection to the module integral part of
    mechanical design
    •Does the cooling plant need modification?

Institutes keen to be involved include
• All current VELO institutes (CERN, Glasgow, L’pool, Nikhef,
Syracuse ..)
• New institutes – So far Bristol, Edinburgh, Manchester, Warwick      1
                    Module Irradiation
              Operating up to ~120 fb-1 gives
              severe challenges
                         Accumulate 1x1014 neqcm-2 per fb-1
                at tip
                         Electronics: 5 MRad per fb-1


• Operating voltage will increase
• Signal will drop – probably pixels can live with this, not strips
• Can pixel chip survive?
• Can innermost part be replaced e.g. silicon sensor, pixel tiles?
• Thermal implications

Latest studies give new results on thickness/annealing/CCE
Have to aim R&D at specific dose and sensor                      2
         Module Thermal Performance

Represents one of the key challenges

Currently we have a DT of 20o to the silicon tip
After 20 fb-1 we run at 60 uA/cm-2 and 7o -> limit of thermal runaway
Injection of heat from chips:
         Strip design: potentially could be avoided but major design change
         Pixel design: Power injection from the chip directly in fiducial volume: careful
design needed
Many ideas on the table: studies and R&D needed
                           -7 degrees buys factor 2
                           leakage current
                           -Cooling material is in
                           acceptance
                           -Module must fit within foil
                           -If a lower setpoint is needed -
                           >cooling plant upgrade
                           - Total power probably OK                                        3
    Module Mechanical Constraints
Current RF foil imposes mechanical constraints:




                                                  4
    Module Mechanical Constraints
Current RF foil imposes mechanical constraints:




                                                  5
      Module Mechanical Constraints
  Current RF foil imposes mechanical constraints:
  Tiling has to be inventive




In addition:
       Fixed width to module to fit into RF box
       Modules must not bend into foil in z (constraint system) 6
       Issue linked to cooling solution, kapton readout
                     Module Resolution
    Several resolution issues are still on the table
    • What is required for physics performance?
    • X0 and l will affect IP, P resolution and efficiency
    • What can we expect for binary/# ADC bits
    • How to optimise pixel power vs cell size/ADC
      **** It is Critical to know what we are designing to! **
 Some points to consider

• Pixel baseline solution is for asymmetric pixels and double sided modules
• Currently the strips aimed at 4 um resolution but probably do not achieve
this
• After irradiation resolution will go binary – a holistic solution must be
considered
• Innermost pixel plaquette of smaller dimension a possibility (but 2013 very
tight for small pixel 40 MHz readout)                                        7
  FE Electronics and Hybridisation

Dramatic changes for FE Electronics for 40 MHz readout
However occupancy remains relatively low: ~3% for strips

Pixel option: Look for a chip from which we can make a derivative
e.g. FPIX,MEDIPIX/TIMEPIX
        40MHz Front End, and digital periphery
        zero suppressed output, coarse digitization
        Issues:
        EMI pick up in kaptons, Baseline restoration
        Power, noise tolerance
        Bump bonding, High Speed flex

Strip option: Develop chip together with silicon tracker
         Discussions underway for a chip with functionality from
charge amplifier to serialiser
                                                                    8
         Issues: # bits/gain/derandomiser/power/250/130 nm etc..
                   1 R&D line: FPIX2 evolution (FNAL-Syracuse)
FPIX2
                   Sparsification and digitization giving good resolution in 1 dimension
                   Current compensation circuit implemented
                   Low noise performance at short peaking times (~60 ns)
                   Fast serial data output (840 Mbps)
                   Tested with protons up to 87 MRad with no degradation in analog
                   peromance
                   Issues:
                        • Data push speed
                        • Timing parameters of analog front-end
                        • Match to optimized PIXEL-VELO cell
           FPIX2        • Migration to a technology different than 0.25 um? impact on
                        analog design, speed, power consumption, radiation hardness

                   Other R&D lines?
                   Medipix/Timepix2:
                   Synchronous readout to 40 MHz ++ possible
                   Move to 55 or 30 um square – connect to bump bonding R&D
                   Possible ADC (multiple threshold)
                   Good hopes for radiation hardness
                   Need to give our input to the architecture now
                   Tiling very important (dead areas/possible laser cutting..)

        TIMEPIX
                                                                                      9
                                                                                      9
      Interconnects and Transmission
   Each “equivalent ASIC” will generate ~5 Gbit/s
   Gives about 1400 links for whole detector. Data volume
   for pixels similar.
Special issue for VELO: Getting the signals
out of the vacuum
Dedicated R&D on feedthroughs needed
high speed copper cables
Use of GBT (interface/speed) to be discussed
        CERN standard
        down link for TTC and ECS incorporated
        10 links of 320 MBits / GBT: we would prefer fewer
Current thinking favours electrical/optical
transition outside tank
        power and space on hybrid
Need a decent input on data sizes and
uniformity in time and space                                 10
                      Software studies
 Upgrade dedicated software studies urgently
 needed
 Look at pattern recognition/ghost rate issues
 Evaluate strip and pixel options (vary # modules)
 Quantify our “back of the envelope”
 guesstimates
 (data volumes, ip resolution, layouts…)




A very exciting option which is often mentioned but not yet
evaluated

pixels + magnetic field
What would this buy us in pattern recognition/resolution?     11
                       Due Diligence
Big enthusiasm within the group to make the sensor choice pixel based
• Practical reasons
    • The 40 MHz strip module is very complex and challenging
    • Synergy with world wide pixel effort
    • Interest from institutes
• Radiation hardness etc.
Essential to start an R&D line in this direction

We also need to convince ourselves, and future reviewers that
There is no significant advantage to strip option
(keep in mind issues of resolution, material, coverage...)
And we must be sure there is no showstopper for pixels




                                                                        12
                                 R&D plan
Document focussing on demonstrator pixel module already in existence
(Syracuse, Liverpool)
A more detailed R&D plan is being worked out.
  In addition we need independent and parallel R&D lines.
  Module thermal performance
          Decide on silicon operating temperature
          Design FEA process, validate with prototypes
          Decide on cooling pipe connection
  Development of vacuum feedthroughs, high speed cables and links
          Setup readout slice
          check integrity of signals/vacuum performance
  R/O architecture and electrical/optical transition
  Setup of testbenches and eventually testbeam facilities
  FE chip development lines and bump bonding
  Software infrastructure: layout, performance evaulation+optimisation
  Radiation hardness of sensors and electronics
  Hybridisation issues: fast flex, thinning                              13
                        Time line

2013/2017 timeline is extremely tight
      To integrate all parts of the project
      To do the necessary turnaround on the testing + QA
      Plus the detector debugging before physics readiness


  We are aware that there is the possibility of a one step
  upgrade, and this would allow a few more options onto
  the table

  It also has a big implication for the VELO, which is that
  we have to survive until 2017 (20-25 fb-1)

                                                              14
 Evaluation of Current detector performance

It may turn out that the current detector plus its replacement
has to survive more than the design 5 fb-1

Note that our depletion voltage is currently limited to 500V.

The thermal runaway in the current running condition must be
evaluated

VELO replacement is n-in-p which could give an advantage.
Also small cooling interface improvements not excluded.

Could we live until 2017 with VELO + VELO replacement?
Or is more drastic action needed? Can we reevaluate the
                                                                15
annealing policy in light of recent R&D?
                           Blue Sky

Aim is not to build the best
possible detector. But to build
a detector which does the job.

However it is natural that institutes
pursue some research lines which
fit into their profile and it is not excluded
that these could be integrated:

smaller pixel dimension,
diamond, 3d                                     They can’t stop me
TSV, thinning,                                  from dreaming
RF foil/wires/LN2 cooling...                                     16
                       Summary

Critical to know what we are designing to:
VELO Upgrade Group working on a Requirements
document on timescale of 2 months

R&D plan not yet fully available but work is going on and we
anticipate a draft within 3 weeks

Timeline is crucial. We will evaluate with respect to the
2013 scenario but also keep in mind the possible changes.




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posted:7/15/2011
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