Dennis Lau

							                                       Dennis Lau
                               1080 Oakridge Drive
                                Fremont, CA 93459
                    Home: (510)683-0922 Cell: (510)709-7567
                       Email: dennis_lau_2002@yahoo.com

OBJECTIVE: Seeking a responsible engineering position to make significant
technical contributions in CAD tools development and chip designs.

SUMMARY OF EXPERIENCE:
   Ten years experience in CAD tool & flow development, and five years experience in
    ASIC logic and custom design.
   Developed many Digital and Analog Mixed Signal design tools and flows resulting in
    shorter design cycle time and lower design cost.
   Developed design architecture and implemented ASIC logic code and custom logic
    circuitry for Ethernet products.

CAD Tools skills:
  Design Creation - Design Compiler, Power Compiler, Virtuoso Design Environment.
  Simulation - Spectre, Hspice, UltraSim, AMS Designer, VAVO, VCS, NC-Verilog.
  DFT- DFT Compiler, Tetramax, Memory BIST, IEEE 1149 TAP.
  Physical Design - JupiterXT, Astro, First Encounter, SOC Encounter.
  Post Layout Verification - StarRCXT, PrimeTime, Hercules, Assura, CeltIC.
  Other tools - Abstract Generator, Library Compiler.
Language: Verilog, SystemVerilog, Unix, Perl, TCL, SKILL.

PROFESSIONAL WORK EXPERIENCE:
National Semiconductor Inc., Santa Clara, California                         1999 to 2009
    Software project manager                                            2008 to 2009
     Implemented an internal standard design CAD tools and flow to all internal
       designers to shorten the design cycle to six months.
     Defined the standard operating procedure for tool development and evaluation.
     Defined CAD infrastructure, development process procedure, and implementing
       QA tests for CAD tools.

    CAD tools development engineer (Analog Mixed Signal)                2006 to 2007
     Developed and implemented design flows and methodologies for analog mixed-
      signal designs.
     Evaluated EDA commercial CAD tools to meet the design challenge, and
      interfaced with commercial vendors to improve the tools for design requirement.
     Supported CAD tools for analog mixed designs including: Schematic Entry,
      Transistor Level Simulation, Custom Routing, Extraction, Physical Verification,
      and Post Layout Analysis.
     Supported design teams to resolve design issues and CAD tool bugs.

    CAD tools development engineer (Digital)                                 1999 to 2005
       Developed and implemented design flows and methodologies for digital designs.
       Evaluated EDA commercial CAD tools to meet the design challenge, and interfaced with
        commercial vendors to improve the tools for design requirement.
       Supported CAD tools for digital designs including: Synthesis, Timing Analysis, Formal
        Verification, Gate Level Simulation, Place and Route, and Post Layout Analysis.
       Developed custom scripts and flows for many design applications.
       Generated EDA process tech files and libraries to support internal Fab processes.
        Accomplishments:
           Developed automated tools for Synthesis, Place & Route, and Timing Simulation for
            CML design. The design was originally performed manually. With the automation
            tools, the design cycle time was reduced by 60% as compared with manual design.
           Developed the antenna fixing flow in Astro and feedback repair flow from Hercules to
            Astro. The new flow was able to correct all the antenna violations.
           Developed scripts to generate the custom Dnwell ring in Place & Route, instead of
            manual layout. The scripts improved the layout productivity by 80% faster and more
            accurate.
           Deployed the new Encounter Place and Route tool, and developed the libraries and
            views to support the tool. The new tool replaced and improved the existing Place and
            Route flow.

Advanced Micro Device, Sunnyvale, California
    Design Engineer (Custom and Logic Design)                    1995 to 1999
     Developed a design from defining design architecture to physical layout.
       Responsible for all stages of the design activities.
     Designed modules by Implementing Verilog RTL codes for advanced digital
       architecture and test bench environment.
     Performed gate level synthesis and optimized for timing performance.
     Implemented design for testability, including Scan, BIST and Tag Controller.
     Improved IO design for signal interfacing and ESD performance.
        Accomplishments:
           Successfully completed design and taped-out 10 chips including designs in
            the area of Home Network Ethernet, Fast Ethernet QPHY, and10/100
            Repeater.
           Fast Ethernet Qphy design met all design specification in the first silicon tape-
            out without any mask re-spin.

EDUCATION:
   Master of Science in Electrical Engineering, University of Santa Clara
   Bachelor of Science in Electrical Engineering, Fresno State University

PATENTS:
   Signal Monitoring Circuit for Detecting Asynchronous Clock Loss (US patent number
    6222392, April 24, 2001).
   Physical Layer Transceiver Architecture for a Home Network (US patent number 6771750,
    Aug 3, 2004).

PUBLICATIONS:
   The ABOVE (Angle Based On-Chip Variation Estimation) technique for a process variation-
    immune design (SNUG conference 2004).
   Crosstalk aware timing analysis and noise analysis for CML cell-based design using
    integrated SI feature in PrimeTime (SNUG conference 2006).
   An incremental technology database structure for Digital-On-Top design methodologies
    (SNUG conference 2007).
   Achieving improved performance in power analysis using PrimeTime-PX (SNUG conference
    2008).