IeMRC Flagship Project Power Electronics by shuifanglj


									          IeMRC Flagship Project:
             Power Electronics

             What is Driving Future Power Electronics?
          • Power electronics holds the key to annual energy
            savings of around $400 billion!
          • Lightweight, high performance products such as
            mobile computing, home entertainment and power
          • High efficiency, high power density electric drives in
            products such as air conditioning
          • Proliferation of automotive and aerospace electronic
          • Increased use of power electronics in transmission
            and distribution systems
          • Energy storage systems
          • Pulsed power

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                       Common Themes
• Increased power densities
• Lower electromagnetic
• Plug-and-go systems
• Extreme operating
• Higher levels of integration
• Lower cost

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                                           Power Semiconductor Devices

                                                                           6kV, 6kA     8kV, 4kA
                                                                                               6kV, 6kA
                                                               4kV, 3kA                    4.5kV, 4kA
                                                2.5kV, 0.5kA
                            10                                                         12kV, 1.5kA
                                                                                                 4.5kV, 2.1kA
    Switched Power (MVA)

                                                                          4.5kV, 3kA
                                                                                                 6.5kV 0.9kA
                                                                 2.5kV, 1.5kA
                                                                                          3.3kV, 1.2kA
                                  1kV, 0.15kA
                                                           2.5kV, 0.6kA                 1.7kV, 1.2kA
                             1                                                                                  ETT
                                                                                 1.2kV, 0.6kA
                                                                             1kV, 0.3kA                         GTO
                                     0.4kV, 0.08kA       0.6kV, 0.2kA                                           IGBT
                            0.1                                            0.5kV, 0.2kA
                                                                          1kV, 25A                              GCT
                              1960        1970            1980            1990            2000

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                 Power Electronic Packaging
     • Physical containment for one or more basic
       component building blocks e.g. semiconductor dies,
       capacitors, inductors, resistors
     • Protection from environment e.g. ingress of liquids,
       dust etc.
     • Circuit interconnections (internal and external)
     • Electromagnetic management – EMC issues
     • Thermal Management

                                 Passive components

                             Semiconductor dies
                                                      Power Module

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              Power Electronic Packages

30V, 50A                     600V, 30A
MOSFET                       MOSFET

                                                       4.5kV, 2.1kA
600V, 200A               Integrated
Half-bridge              power                       1200V, 200A
IGBT                     module                      module for
module                                               aircraft flight
                                                     surface actuation

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            Why Manufacture Power Electronics in UK?

          • UK based technology and manufacturing capability is
            currently relatively strong
          • UK is internationally competitive across the whole
            supply chain
          • Many systems are application specific, highly
            customised and tend to have a relatively high added
          • Suited to a technologically advanced manufacturing
            base and can absorb the relatively high UK labour

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             Power Electronic Performance Limitations

          • Semiconductor devices
             – Silicon max. power device die temperatures from 125°C
               to 200°C
             – Silicon Carbide, Gallium Nitride and Diamond > 300°C
          • Passive devices
             – Capacitors
          • Packaging
             – Thermal cycling
             – Power density
             – Environmental

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            Anatomy of Typical Package and Heatsink

          Lead-out interconnect
          Bond wire                             Die
          Encapsulation                         Solder
          Housing                               Direct bonded copper
                                                Direct bonded copper
                                                Copper baseplate
                                                Thermal Grease

    Thermal stack has 9 layers, 8 interfaces!

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           IeMRC Flagship Project in Power Electronics

          To enhance the competitiveness of the UK power
          electronics industry through improvements to the
          design and manufacturing capability for high power
          density systems and in particular those intended for
          high reliability applications and challenging

          Programme started 1st July 2005
          Duration 42 months
          Total IeMRC funding £811 k, 5 Academic partners

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          1. Establish and maintain a roadmap for power
             electronics modules and associated thermal
             management systems.
          2. Maintain a “technology watch” on emerging
             technologies for power electronic modules and
             associated thermal management systems.
          3. Develop an enhanced physics of failure approach to
             the design and qualification of power electronic
          4. Establish the feasibility of a range of advanced power
             electronic module manufacturing technologies and
             apply selected technologies in a manufacturing

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                           Academic Partners

                                        point analysis tools,
          power electronics,            physics-of-failure reliability
          module design and             predictions, multi-physics
          failure analysis              modelling and numerical

                         partial discharge     high-permittivity
heat transfer            effects               dielectrics and Silicon
and thermal                                    Carbide device
management                                     fabrication

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                            Industrial Partners
          •   Dynex Semiconductor
          •   Goodrich
          •   International Rectifier
          •   Morgan Technical Ceramics
          •   QinetiQ
          •   Raytheon Systems
          •   Rohm and Haas
          •   Rolls-Royce
          •   SELEX
          •   Semelab
          •   SR-Drives
          •   TRW Automotive

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                               Work Packages

          • WP0 – Management
          • WP1 – Road mapping
          • WP2 – Technology watch
          • WP3 – Reliability and physics of failure
          • WP4 – Advanced packaging

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                       Management Structure
WP1: Cyril Buttay
                                Project Steering
Team 1: Mark Johnson
Team 2: Ian Cotton
Team 3: David Newcombe
Team 4: Mark Johnson                 Shef. PI

          WP1                                      WP2   Team 4   WP4

                              Team 2
                    Team 1
                                        Team 3
                              WP 3

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          Work-Package and Team Composition
WP1 (Road-Mapping)
• Sheffield, Loughborough
  Team leaders: Cyril Buttay, Paul Palmer
WP3 (Reliability)
• Team 1 (substrate-level reliability): Sheffield, Greenwich, Dynex,
  Semelab, Goodrich
  Team leader: Mark Johnson
• Team 2 (partial discharge): Manchester, Greenwich, Dynex, Rolls-
  Team leader: Ian Cotton
• Team 3 (whole module): Sheffield, Greenwich, Manchester, Dynex,
  Semelab, Goodrich
  Team leader: David Newcombe
WP2/4 (Advanced Packaging)
• Team 4 (technology watch/advanced packaging): Sheffield,
  Greenwich, Oxford, Newcastle, Dynex, Semelab, Goodrich, Rolls-
  Team leader: Mark Johnson

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                           WP1 Road Mapping

          • Two events held:
             – workshop during November 2005
             – on-line follow-up event in January
          • Data captured in a database using a spreadsheet-
            based form
          • Results from the workshop (keywords, issues and
            metrics) circulated to delegates and discussed at the
            on-line workshop in January
          • Consensus that more application focussed events
          • Future event on power electronics for the more
            electric aircraft is planned for May 2006

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                                     Drivers, Metrics and Keywords

            Power Electronic System, Power Electronic Converter                                        Top-Down Drivers
               Topology                                 Lifetime (years, cycles)
               Cost/kVA                                 Environment (thermal,                          Customer requirements
               Power density (kVA/m       3
                                              ,         vibration radiation)                           Application requirements
               kVA/kg)                                  Efficiency                                     Societal demands
                                                  Hardware                               Software      Legislation
                                                                                                       Global economics
            Active                        Passive                    Sensor/ control                   Obsolescence
            Components                    Components
            Cost/unit                     Cost/unit                  Cost/unit         Functionality
            Cost/ kVA                     Cost/ µF, µH etc.          Lifetime          Integrity
            Lifetime                      Lifetime                   Environment       Security
            Environment                   Environment                Losses            GUI
            On-state loss                 Losses                     Accuracy
            Off-state loss                                           Cost/function
            Switching loss
            performance                                                                                Bottom -Up Drivers

                                                                                                       Materials technologies
                                                                                                       Assembly technologies
                                                                                                       New concepts
                                                                                                       Legislation ( RoHS etc.)
          Metrics                                                                                      Global economics
          Each metric (e.g. cost/unit) will be                                                         Obsolescence
          influenced by a combination of
          quantifiable factors: e.g. materials used,
          assembly technology, device design,
          thermal management technology etc.

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                       WP3 Summary of Activities
          • A series of initial reliability tests were agreed to
            establish the capability of the current state-of-the-art.
          • Coupons were acquired for thermal cycling testing of
            the substrate tiles
          • Experimental work commenced at Sheffield in
            October 2005. An interim report has been produced
            and further tests are ongoing
          • Greenwich has undertaken a number of thermal
            cycling simulations to help identify suitable test
            procedures that will be used to gather failure
            information for particular mechanisms.
          • Greenwich has also reviewed the CENELEC and IEC
            standards on semiconductor power modules

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                         Summary of Activities

          • Manchester is working to describe problems relating
            to partial discharge in power electronic modules
          • Provide techniques for minimising its likelihood
          • Provide a physics of failure model
          • Modelling of modules has been carried out in FEA
            simulation software

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                  Thermal Cycling Limitations

   Repeated heating and cooling of assembly leads to
   repetitive mechanical stress and eventual failure

           Flexing of bond wires
           causes fatigue failure          Bond wire
           (de-bonding) at heel            Die
  CTE mismatch                             Direct bonded copper
  causes fatigue failure                   Ceramic
  at interfaces                            Direct bonded copper
                                           Copper baseplate

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                    Substrate Wear-Out
   • DBC substrates are composed of a ceramic
     insulator e.g. Al2O3 (aluminum oxide) or AlN
     (aluminum nitride) onto which pure copper metal is
   • The different expansion coefficients of copper and
     ceramic lead to mechanical stresses in the ceramic
   • Cracks originate at the copper/ceramic interface,
     propagating at an angle of 45 0
   • As the crack reaches about one third of the way
     through the ceramic, the crack direction turns
     parallel to the substrate surface resulting in
     conchoidal fracture

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                    Fatigue failure: Conchoidal fracture
                     %conchoidal fracture vs temperature cycles





                                         Front of tile
 % fracture





                      Back of tile
                                 temperature cycles

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                                        Failure rate of tiles due to temp cycling

          number of cycles to failure

                                                                                    -60 to 150 C
                                                                                    -10 to 200 C

                                        1   2    3     4       5   6    7   8   9
                                                      substrate tiles

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          Ultrasonic Wire Bonding Mechanism

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             Failure: Crack at the Bonding Interface

                                       Heating process     Cooling process
             Crack                        induces              induces
             propagation              compressive Stress    tensile Stress

                                            Al                   Al
          Substrate (Si)                   Wire                 Wire
          coated with Al
                                      Substrate (Si)       Substrate (Si)

                                      Coefficient of thermal
                                      expansion: αAl ≈ 12x αSi

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                         Wire Bond Degradation

  100 cycles -55 to              1500 cycles
  +125 deg C
                                                        3000 cycles

          • Degradation of bond begins immediately
          • Crack propagates in the bond wire close to the weld
          • After 3000 cycles virtually all bond wires have lifted

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                               Wire Bond Life
• Number of cycles to                                      10000.0
  failure can be

                                     Thousands of Cycles
  represented by Coffin-
  Mason law                                                  100.0
          N 2 ' (T2   $
             =%       "
          N 1 % (T1
                      #                                        1.0

• K ~ 6.5                                                            10      100        1000
• Rapid degradation in                                                    delta T (K)
  performance with ΔT

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              Multi-Physics Modelling at Greenwich

     Manufacturing                Testing       Field

           Failure Mechanisms, Reliability
              Temperature             Stress
                 CFD, FEA, Optimisation…


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                           Project Management
  • Greenwich Team
          – Chris Bailey                    IeMRC
          – Hua Lu
                                      POWER ELECTRONICS
          – Tim Tilford
                                       FLAGSHIP PROJECT

                                      MODELLING POWER
                                       MODULES (MPM)

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                         IeMRC - Reliability

          Accelerated Life Testing
                       Fatigue, etc

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                         Solder Interconnect
                                    • thermal load profiles
     Predict effects of:
                                    • design parameters:
                                       • geometry, material properties

                                                   13.5 mm
     Chip 330 microns
     Solder 100 microns
     Cu     0.3 mm
     Alumina 1 mm
     Cu     0.3 mm
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                                          Thermal Cycles
               •    4 temperature cycles are investigated
               •    Each cycle consists of 15 min ramps and dwells at both low
                    and high temperature extremes.
                              Cycle   1
                   140        Cycle   2
                              Cycle   3
 T(degree C)

                    90        Cycle   4
                                                  Cycle   Tmin   Tmax   dT
                    40                             1      -55    125    180

                                                   2      -25    155    180
                   -10                             3      -40    110    150
                                                   4      -10    140    150

                         0    10          20        30           40           50   60

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                      Model Dimension and Materials

           330µm                    Silicon
           100µm                                Solder
           300µm                         Cu

            1mm                          Alumina

           300µm                         Cu

              Symmetry plane

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                         Results: Sn3.8Ag0.7Cu(SAC)


              Plastic work dW distribution at the end of a thermal cycle

                                CYC1          CYC1           CYC3             CYC4
          Max(dW)/Mpa             0.4         0.383          0.318            0.296
                 Nf*           1315.789      1374.193       1655.081         1778.094

    *N is actually the life time of an element with a length of 73 microns.
    The lifetime of the whole solder joint is much greater.

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                          Life-time Prediction (SnPb)
      Number of cycles to crack initiation and crack propagation
      rate  Cycles             N            dl/dN (µm/cycle)
                                               0             L10000(mm)*

          Tmin     Tmax       dT       SnAg        SnPb   SnAg   SnPb    SnAg   SnPb

          -55       125       180                  126           0.135          1.346

          -25       155       180                  150           0.111          1.105

          -40       110       150                  162           0.101          1.011

          -10       140       150                  196           0.081          0.815

     * L10000 is the crack length after 10000 cycles.

     1. For SnPb, FEA results can be correlated to crack initiation
        time and crack propagation time
     2. For SAC solder this is not available.
     3. No lifetime model for SnAg at the moment.

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                   Residual Stress in Substrate Tiles
          • Simple models have been used to calculate the stress
            distribution in tiles
          • The effects of the following parameters on the stress
            distribution in a round tile have been investigated:
             –   gap width
             –   radius
             –   ceramic thickness
             –   margin

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          Tile with Patterned Copper

                          Symmetry plane

Symmetry plane
                 Von Mises Stress Distribution

                                  Symmetry plane

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                   Partial Discharge Phenomena

    • Research student appointed October 2005
    • Two day visit to Dynex for student to experience
      manufacturing techniques / design issues
    • Literature review completed
    • FEA Modelling of in-use versus test conditions
    • Experimental activity commenced
          – Investigation of acoustic monitoring
          – Testing of specific materials

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                    Key Literature Review Findings

          • For substrates:
             – Voids within substrates typically dominant failure
             – DC breakdown strength of ALN typically double that of
             – Breakdown strengths appear to be non-linear
             – No significant temperature effect noted
          • For gels:
             – Gels also strongly degraded by PD but evidence of self-
               healing exists
             – Large influence of humidity on strength of gels
             – Inverse relationship of temperature with strength of gels

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                                FEA Modelling

          • Electrostatic modelling of a module has been carried
            out for conditions where the module is under test and
          • When tested in production, all HV terminals bonded
            to each other and raised in voltage while baseplate is
          • In use, voltage differences exist between HV terminals
          • Does the production test actually stress all
            components of the module?

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          Comparison of Test and In-Service E-Fields

          Substrate in test           Substrate in use

             Gel in test               Gel in use

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                               WP2/4 (Team 4)

          • A meeting of Team 4 was held on 17th October 2005
            to define the future activities of WP2/4. A range of
            activities were discussed and the following were
            identified for further action:
             – Baseplate materials: survey of alternatives
             – Baseplate-less designs: utilising direct cooling of the
               substrate tile
             – Substrate tiles: survey of alternatives
             – Interconnect: evaluation of alternative techniques such
               as soldered Cu strip and TLP-bonded Ag foil
             – Cooling technologies: survey of heat-lane coolers

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                          Summary of Activities

          • A survey of base-plate and substrate materials has
            commenced under the “technology watch” theme
          • Oxford has performed an extensive review of heat
            lane literature to furnish understanding of this
            potentially promising cooling technology
             – A simple demonstration unit has been designed and is
               undergoing trials.
          • Newcastle has initiated work on using deposition
            techniques for forming substrate-level high-k based
            decoupling capacitors

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                     Closed Loop Pulsating Heat Pipes
          •   Constant volume system
          •   Filled with working fluid at saturation
              (boiling) conditions
          •   Serpentine arrangement of channels or
          •   Hot and Cold side; evaporator and
     •        Boiling of water at the evaporator and bubble formation
     •        Condensing of water at the cold end and bubble collapse
     •        Heat stored in latent heat, transferred by oscillations and
     •        Push and pull of fluid leads to oscillations
     •        Instabilities cause circulations

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                 Closed Loop Pulsating Heat Pipes
  •       Improved design built and tested
          •   Narrower channels, 2mm => 1.6mm
          •   More loops, 12 => 24
          •   Non-moving part valves incorporated

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                 Closed Loop Pulsating Heat Pipes
  •       Non-moving part valves encourage fluid circulation
          •   A number of valve designs were tested using air flow
              through a stereolith model in ABS plastic.
          •   Teslar non-moving part valve design chosen.

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                      Closed Loop Pulsating Heat Pipes
•       Testing
        •     Successful operation in vertical orientation
        •     Difficultly maintaining oscillations when the device is horizontal
                                                      Pulsating channels

                Pulsating channels migrate
                   from left to the right

                    Vapour and boiling
                      water droplets                  Droplets of water
                                                     feed the evaporator

    5/22/06                     CONFIDENTIAL
                 Closed Loop Pulsating Heat Pipes
 •        Thermal resistance decreases as heat input is increased
          •   An effective conductivity for the device of 4990W/mK
          •   Twelve times higher than silver
                                                                   Vertical Wet - 100mm PHP
                                                             Thermal Resistance vs Heat Transferred


                       Thermal Resistance (K/W)


                                                                                           y = 28.13x-0.8292



                                                      0.00        50.00         100.00        150.00           200.00
                                                                       Heat Transferred (Watts)

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                   Integrated Capacitor Technology
       •   The capacitor is deposited in a series of layers on a DBC (or
           similar ceramic) substrate.
       •   A multi-layer structure offers higher capacitance (energy storage)
           per unit volume.

                                                             High-k dielectric
      ~500-                                                  Metal (e.g. Au/Al)
      600 µm
  ~200-                                                          DBC copper layer
  300 µm
~500-                                                             DBC ceramic layer
600 µm

       •   Area: 60 mm x 20 mm.
       •   Total height: around 600 microns.
       •   Voltage rating: 1000 V
       •   Leakage current less than 1 mA / mm2 at 200°C and 1000 V

 5/22/06                CONFIDENTIAL
              Initial Results for a SiC-based structure

          • Fabricated on 5x1015cm-3 n-type Cree wafers
          • Thermally oxidised layer (25nm)
          • 50nm Ti layer deposited and oxidised at 800oC to give
            75 nm TiO2 layer
          • Palladium gate (50nm thick) deposited
          • Tested in air in a light-tight box on a hotplate

5/22/06                CONFIDENTIAL

          Capacitance (pF)

              110                                                         10kHz
                      90                                                 100kHz
                             100          200          300         400       500
                                                  Temperature (oC)

5/22/06                            CONFIDENTIAL
                Power Electronics Flagship Summary

          • All academic partners now “up to speed” with staff in
          • Technical work packages underway
             – Road mapping
             – Reliability and physics of failure
             – Advanced packaging
          • Initial progress is promising
          • Need to maximise gearing through other initiatives
            e.g. DTI technology programme
          • Additional industrial partners are welcome to join

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          Summary of Current and Potential Future Links
      Aerospace            IeMRC             Power                       EPSRC-funded
      Innovation and
      Growth Team:                           electronics                 research in SiC
      AIN, TVP                               roadmap                     (ASCENT)

      DTI-funded             Packaging
      programmes in          technology
      power                  qualification                               DTI-funded
      electronics (5th                                       Advanced    research into
      Call)                                                  packaging   improved bonding
      research in                                                        DTI-funded
      power module                           Design for                  research into
      technology                             qualification               modelling of power
                                                                         modules (MPM)

                                                                         funded activities
                EPPIC                                                    (TBA)
                                             Foresight Vehicle

5/22/06                   CONFIDENTIAL
                     Web Site, Further Information

          • Public section has information on the project, its work
            packages, dissemination of key results etc.
          • Project partner forum will be used to keep minutes of
            meetings, project reports etc.

5/22/06                CONFIDENTIAL

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