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A mm-Wave Transformer Based TransmitReceive Switch in 90nm CMOS

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A mm-Wave Transformer Based TransmitReceive Switch in 90nm CMOS Powered By Docstoc
					  A mm-Wave Transformer Based Transmit/Receive
       Switch in 90nm CMOS Technology
                                               Ehsan Adabi, Ali M. Niknejad
                                    EECS Department, University of California at Berkeley
                                        2108 Allston Way, Berkeley, CA 94704, USA
                                                adabi@eecs.berkeley.edu
                                               niknejad@eecs.berkeley.edu


   Abstract— A 50 GHz transformer based single pole double
throw (SPDT) shunt switch was designed and fabricated in
90nm digital CMOS process. It has a minimum insertion loss
of 3.4dB at 50GHz from the single pole to the ON-thru port
and a leakage of 19dB from the single pole to the OFF-thru
port. The isolation is 13.7dB between the two thru ports. Return
loss for the single pole and ON-thru ports is better than -10dB.
Large signal measurements verify that the switch is capable
of handling +14dBm of input power at its 1dB compression
point. The fabricated SPDT switch has a small active area of
60µm×60µm.

                      I. I NTRODUCTION
   Due to the rapid technology scaling, CMOS transistors           Fig. 1. A fully integrated transceiver with an on-chip antenna requires an
that were traditionally employed in digital and low frequency      integrated T/R switch to save die area.
analog and RF circuits are nowadays capable of handling
signals at mm-wave frequencies. Previous work [1][2] has
demonstrated the feasibility of many key mm-wave transceiver       frequencies is an important goal toward the realization of a
building blocks in standard digital CMOS processes. On the         low cost mm-wave system.
other hand, there have been relatively few demonstrations of          The design of T/R switches is challenging since it resides
switches operating at mm-wave frequencies, which is a key          before the LNA and after the PA. In order not to degrade the
building block in RF systems.                                      sensitivity of the receiver and the transmit power, switches
   Operating at mm-wave frequencies has many advantages.           should incur low insertion loss in the ON mode. To have
One key advantage is due to small wavelength, which allows         enough directivity, insertion loss should be rather high when
antennas to be realized on chip or on the package, further         the switch is OFF. To keep the LNA and PA isolated, enough
reducing the cost of a system. Moreover many antennas              isolation between the two thru ports should be ensured and
could be integrated with suitable phase shifters to create         finally switches should be capable of handling high powers
phased array systems that effectively increase the aperture        beyond the PA output compression point. As with all high
size and directivity of transmit/recieve antennas by a factor      frequency circuits, input and output ports should be matched
of N (number of antennas). Spatial filtering achieved by a          to guarantee adequate return loss for incident signals.
phased antenna array system alleviates impairments such as            In addition to transmit/receive (T/R) switching, single pole
delay spread and co-channel interference and further helps to      double thru (SPDT) switches have many other useful appli-
extend the communication range and bandwidth. Without a            cations. Examples include modulators, stepped attenuators,
transmit/receive (T/R) switch, two separate antennas should        and phase shifters. In this work we demonstrate a miniature
be employed for the receiver and transmitter, which translates     transformer based mm-wave SPDT switch implemented in
to half the transmit/receive antenna gain and aperture size for    a 90nm digital CMOS technology. In section II different
a given area. Whereas if T/R switches with performances that       switching structures are compared and the transformer based
pass system requirements can be implemented in the same            shunt switch is described. Section III deals with the proposed
CMOS chip, a single antenna will be shared between the             switch design methodology. Measurement results are presented
transmitter and receiver and twice the number of antennas will     in section IV.
be fabricated on the same die area. Moreover, if the antenna
is realized on-chip, a T/R switch can save a great deal of                  II. T RANSFORMER -BASED S HUNT S WITCH
area, and thus lower the cost, since antennas are relatively         By its nature, when the gate of a MOS transistor is driven
large. Therefore designing CMOS T/R switches at mm-wave            by a rail to rail voltage, it acts as a switch. In fact this
Fig. 2. Measured S21 of an NMOS transistor acting as a series switch in a          Fig. 4.   Small signal equivalent circuit of proposed switch.
50Ω environment.



                                                                            capacitance) and adding a shunt switch in between two series
sole transistor switch is sufficient for many digital and analog
                                                                            switches with an inverted gate signal with respect to the series
applications. When the switch is on, the transistor is in the
                                                                            switches (shorting out the feedthrough signal). These tech-
triode region and a low resistive channel connects source and
                                                                            niques are mostly applicable to lower RF frequencysystems
drain terminals of a MOS transistor. To the first order, the
                                                                            since at mm-wave frequencies having multiple transistors in
on-mode resistance of a MOS switch(RON ) is equal to 1/gm
                                                                            the signal path introduces substantial insertion loss. Switches
where the transconductance is calculated at the edge of the sat-
                                                                            cannot be made too large due to parasitic capacitance limi-
uration. When the switch is off, there is no conducting channel
                                                                            tations. In mm-wave regime, a switching structure with the
between source and drain and the resistive path that connects
                                                                            least number of transistors is desirable to reduce parasitics.
source-drain terminals exhibits a very large ROF F . In the off
                                                                            Furthermore, any transistors in series with the signal path can
mode there is a feedthrough path through parasitic capacitors
                                                                            incur a noticeable loss and a structure that removes series
between source and drain. This path could is through both
                                                                            transistors is more suitable.
Cgd − Cgs and Cdb − Csb networks. At low frequencies, when
the transistor is operating at frequencies much lower than its                 Shunt SPDT switches were traditionally designed exploiting
fT , the capacitive feedthrough path introduces a much higher               two quarter-wave transmission line sections (Fig. 3). A λ/4
off-mode reactance than the resistance of the channel in the                line converts a short impedance from the off-port to an open
on-mode. But at mm-wave frequencies, when the device is                     impedance at the common input port in order to direct all the
operating close to the fT frequency, the impedance of the                   input power toward the on-port. The impedance of the on-port
switch in the off state is comparable to when it is on. Fig. 2              is matched to the quarter-wave line characteristic impedance
depicts the measured S21 of a 40µm NMOS transistor acting                   and to the input impedance respectively .
as a switch in a 50Ω environment. As can be seen in this                       Even at mm-wave frequencies, λ/4 lines are too bulky and
figure, S21 for on and off states at 60GHz are comparable.                   take too much area to be implemented on chip. Therefore
                                                                            devising a lumped component counterpart for the shunt SPDT
   There are techniques to diminish the feedthrough path by
                                                                            switch is highly valuable. In this work we introduce a trans-
cascading multiple switches (decreasing the effective series
                                                                            former based shunt switch employing a transformer and two
                                                                            NMOS transistors as shown in Fig. 3 .
                                                                               The input is connected across the primary winding and each
                                                                            end of the secondary winding is connected to an output with
                                                                            an NMOS transistor shunted to ground. Input current flowing
                                                                            in the primary winding produces magnetic flux that passes
                                                                            through the secondary winding and induces a voltage across
                                                                            the secondary. For each switching state, one transistor is on
                                                                            and the other one is off. When a transistor is on, it introduces a
                                                                            low impedance at its port, and the induced voltage will appear
                                                                            at the other end. Unlike the traditional distributed switch, this
                                                                            structure introduces a 180◦ phase difference between the two
Fig. 3.     Traditional shunt switch and a miniature lumped component
counterpart
                                                                            outputs. In a TR switch, this 180◦ phase shift is of minor
                                                                            concern since this corresponds to moving the transceiver a
                                                                 Fig. 6. Measured insertion loss, leakage(input to off-port) and isolation
                                                                 (between an on-port and an off-port)
                  Fig. 5.   Die microphotograph.


                                                                 realized by small loops, which results in a small layout.
distance of λ/2 and most circuits that are sensitive to RF       However if the transformer is made very small, primary and
phase use carrier locking techniques.                            secondary inductances will be comparable to trace inductances
                                                                 connecting the transformer to the peripheral circuitry. This
   As shown in Fig. 4, all parasitic capacitances in this
                                                                 makes the design more sensitive to parasitics while lowering
structure are shunt capacitors to ground and do not provide
                                                                 the insertion loss. In our design an overlay structure for a 1:1
a feedthrough path between the input and output. Moreover,
                                                                 transformer employing two top metals is used. The diameter
these capacitances will be resonated out with the equivalent
                                                                 of the octagon loop is 42µm. The coupling between the loops
inductance appearing at the transformer terminals at the de-
                                                                 is k = 0.72 and the minimum insertion loss of the transformer
sired frequency and hence in theory no signal is lost due to
                                                                 is -1dB at the passband of the transformer.
parasitic capacitance.
                                                                    The prototype uses 40µm NMOS transistors. Channel
   Shunt switches shown in Fig. 3 are reflective type of
                                                                 lengths are set to the minimum for smallest RON . However,
switches which means that when the input is not connected
                                                                 since RGate does not effect the switch performance, finger
to an output port, that port sees a short circuit and hence it
                                                                 widths that result in maximum fmax were not used. To isolate
is not matched. A mismatch at the input of LNA and output
                                                                 two switching signals from each other, RG = 1kΩ was
of PA can be problematic and cause oscillation. Since these
                                                                 inserted at the gate of each transistor in series. This added
switches are used in a time division duplexing (TDD) scheme,
                                                                 RG also attenuates the effect of any gate line inductance.
whenever one output is disabled, the connecting block can be
                                                                 Inductance at the gate line is detrimental to the linearity as
turned off. Shutting down the block not only eliminates the
                                                                 it resonates out some part of parasitic gate capacitance to the
potential oscillation problems but also it has the advantage
                                                                 ground. The voltage at the gate induced by the drain voltage is
of saving power dissipation at the expense of recovery time
                                                                 increased due to the increment of the capacitive divide ratio. At
needed for those blocks to be turned on and reach their steady
                                                                 high output powers, this induced gate voltage can partially turn
state condition.
                                                                 on the channel and cause non-linearity issues. The magnetic
       III. T RANSFORMER BASED S WITCH D ESIGN                   coupling between the two loops of the transformer plays an
                                                                 important role in the switch functionality and care must be
   The small signal model of the transformer based switch        taken not to disturb this magnetic field.
is shown in Fig. 4. ROF F is much larger than RLOAD ,
and can be neglected since they are in parallel. Parasitic                 IV. P ROTOTYPE M EASUREMENT R ESULTS
shunt capacitances will be resonated out and the impedance          A prototype STDP TR switch has been fabricted in a
loading the secondary loop is RON + RLOAD . To minimize          90nm CMOS process. The die photo is shown in Fig. 5 and
the insertion loss, the RRON ratio should be minimized
                           LOAD
                                                                 the active area of the switch is only 60×60 µm2 . On-wafer
which means that larger transistor sizes are required. Larger    measurement results are shown in Fig. 6 - 8. The input/output
transistor sizing result in more parasitic capacitances and      GSG pads have been de-embedded from the measuremetns
correspondingly smaller effective inductance being required      using open/short de-embedding. As depicted in Fig. 6, the
to resonate out this capacitance at the desired frequency. So    switch has its minimum insertion loss of 3.4dB at 50GHz
the transformer winding inductance needed for this structure     and its 3dB bandwidth extends beyond 40GHz-60GHz. When
to work at mm-wave frequency will be small and easily            the input is not connected to an output, there is 19dB of
                                                                           Ref.            This Work       [5]             [6]


                                                                      CMOS Process           90nm        130nm      90nm triple-well


                                                                     Frequency(GHz)            50          60              24


                                                                    Insertion Loss (dB)        3.4         4.5            3.5


                                                                       Isolation (dB)         13.7         24              16


                                                                    Supply voltage(V)           1          1.2            1.2


                                                                      IP−1dB (dBm)             14          4.1            28.7

             Fig. 7.   Measured input and output match
                                                                       Area (mm2 )           0.004        0.221          0.018

                                                                                               TABLE I
                                                                  C OMPARISON TO RECENTLY      PUBLISHED MM - WAVE     T/R   SWITCHES




                                                              process. It has a minimum insertion loss of 3.4dB at 50GHz
                                                              from the single pole to the ON-thru port and a leakage of
                                                              19dB from the single pole to the OFF-thru port. The isolation
                                                              is 13.7dB between the two ports. Matching for the single
                                                              pole and ON-thru ports is better than 10dB. Large signal
                                                              measurements verify that the switch is capable of handling
                                                              +14dBm of input power at its 1dB compression point. The
                                                              fabricated chip has a small active area of 60µm×60µm.
                                                                                   VI. ACKNOWLEDGEMENT
                                                                 This project was funded by C2S2. The authors acknowledge
                                                              sponsors of Berkeley Wireless Research Center, the NSF In-
                                                              frastructure Grant No. 0403427, and the foundry chip donation
                  Fig. 8.   Linearity measurement
                                                              of STMicroelectronics.
                                                                                           R EFERENCES
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                                                                  June. 2004.
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insertion loss and die area. Beyond 50GHz it has a record         applications ,”IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 486-492,
linearity performance in CMOS technology.                         March. 2001.
                                                              [5] C. M. Ta and R. J. Evans, “A 60 GHz CMOS transmit/receive switch,”
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                        V. C ONCLUSION                        [6] P. Park, D. H. Shin, J. J. Pekarik, M. Rodwell and C. P. Yue, “A high-
                                                                  linearitty, LC-tuned, 24GHz T/R Switch in 90nm CMOS,” IEEE RFIC
   A new lumped-element switch topology has been proposed.        Symp. Dig., pp. 369-372, June 2008.
The switch only incorporates shunt transistors, which makes
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prototype was designed and fabricated in 90nm digital CMOS

				
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