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System In Package _SiP_ and Stacked Package Solutions Ansoft

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									System In Package (SiP) and
Stacked Package Solutions


     Ansoft Corporation
   2006 Worldwide Application Workshop
              Objectives

System in Package Overview

SiP Engineering Challenges

Ansoft Solution for SiP

Proper De-embedding
   What is System-in-Package (SiP)?
SiP is an advanced technology to incorporate multiple
components into a single package

  SiP contains one or more die
  Combinations of wire-bond and flip-chip
  Memory and logic are combined with passives, filters, antennas
                    SiP Benefits
SiP provides a solution to a system design challenges
  Smaller system size
  Increased system density
  Lower system power consumption
                   SiP Applications
Cell phones features throughout the history
  Basic phone call
  SMS messages
  Photo, video, music, sports, Live TV, web…..
Memory requirements are increasing                               2006 model
                                                                 SCH-B570
  Diverse application type




                                                 8 GB HD (16 movies)
                                                 2Mp camera
                                                 GPS
                                                 MP3 (1600 files)
                                                 Picture in picture
                            Inside look to SiP
        Samsung SPH-X4200 cell phone layout
               3DG CDMA technology
               Memory requirements for cell phones are increasing
               Package on Package example
               Different companies collaboration
                                                                                     AMD
                                                                       Stacked Memory Package
                                                                          AMD/Fujitsu Flash Die
                                                                           Samsung SRAM Die




                                                                           Fujitsu
                                                                Stacked Memory Package
                                                                    AMD/Fujitsu Flash Die
Source: Portelligent
                                                                      NEC FCRAM Die
           Overview of SiP Flow
SiP Engineering Challenges
     Packages from different companies
     More complex than single-chip package
      – Bondwire coupling within single package
      – Coupling between stacked packages


Quality Tools and Development Investment
  “NXP will raise the development budget" for products, "seeking the
  best tools. We will not skimp on quality, and we will aim for zero
  defect and first-time-right silicon." - Frans van Houten NXP CEO


Accurate and easy co-design and co-optimization of
entire chip, package and PCB is needed.
 Ansoft SiP Solution

Top Package            Bottom Package
 Vendor A                 Vendor B



                System Initial Design
              Performance Validation

                          Electrical,
  Optimization           Thermal and
                         Mechanical


  Final System           System Jitter,
   Verification          Eye Diagram
                Ansoft SiP Solution
                     (emphasis on PoP)




Source: Amkor
             Package-on-Package
                        (courtesy of Amkor)


Top package : Memory device (DRAM and flash)
Bottom package : High density digital or mixed-signal logic
devices
Design Validation   Optimization   Final System Verification




            Design Validation
            Merge Package Layouts
              Full Package RLC
              Crosstalk Analysis
 Design Validation      Optimization       Final System Verification




          Package/PCB Merge Utility
Overview of Ansoft Merge utility
                         • 3rd party top package
                          • 3rd party bottom package



                          • Merge .siw files to preserve:
                             • All R, L, C Components
                             • All IO, IC Discrete Device
                               Footprint and Pin Information
Package on Package/View
Design Validation         Optimization   Final System Verification




        Full Package RLC Extraction
      TM
TPA v5.0
   Designed to handle complex
   SiP layouts
   Full package and selected nets
   SPICE model export
   Automatic terminal assignments
   along with net names
  Design Validation           Optimization   Final System Verification




                         PoP Validation
    TM
TPA v5.0
  Initial Layout Validation
  Simulation data
         Selected Nets
  Design Validation               Optimization       Final System Verification




                       SiP Validation
    TM                                 TM
                                                 ®
TPA v5.0 data in DesignerSI /Nexxim
  Quick validation
  Crosstalk data of critical nets
  Nominal case
  Merged Design
         Top and bottom package
Design Validation       Optimization   Final System Verification




                    Optimization:
                      Automation
                       Electrical
                       Thermal
                      Mechanical
           Design Validation                  Optimization           Final System Verification




                                      Optimize 3D Layout
       3D complexity of SiP packages is increased
              Multiple dies (die to die coupling)
              Different stacking approaches (stacked, side to side…)
              3D nature of wirebonds and bumps and balls
       Need for accurate and fast 3D electrical modelling
              Parametric Co-design analysis is required




                                                             Frequency

Source: Tessera's µZ®-Ball Stack Technology
 Design Validation             Optimization                  Final System Verification




                          Automation
                     TM
AnsoftLinks v4.0
   Prepare the Design for Optimization
   Automated 3D Model creations




                                                                      Q3D project




                                                                      HFSS project

                                          Auto defined
                                      Ports and boundaries
 Design Validation      Optimization   Final System Verification




    Electrical, Thermal, Mechanical
Routing (trace width and spacing)
Bondwire profile
Solderball profile
    Design Validation            Optimization               Final System Verification




              Optimize Bondwire profile
                        ®
Q3D Extractor simulation data
   Critical design parameter
   True 3D bondwire modelling
   Impact of wire length on resistance

               Bondwire Length            Bondwire Height




URAM_D0
URAM_D1
URAM_D3
URAM_D5
Design Validation                    Optimization             Final System Verification




      Wire Length Resistance Effect




                                                        URAM_D0
                                                        URAM_D1
                                                        URAM_D3
                                                        URAM_D5




                    Bondwire resistance will increase dramatically
                           due to increase in wire length
Design Validation                   Optimization                Final System Verification




   Optimize Simulation Run Times
Distributed Solve
    Distributed solve enables engineers to distribute the computational load of a
    parametric design sweep or frequency sweep across a network or cluster of
    computer workstations.
    Distributed Solve enables engineers to efficiently characterize an entire design
    space in a fraction of the time it takes a single computer

                                  Host Computer




                                                           …
                                                           …
                                Remote Computers
              (Up to 10 remote computers per Distributed Solve license)
Design Validation                            Optimization   Final System Verification




   Optimize Simulation Run Times
 Trace width and spacing parameterization using Q3D
 Distributed Solve Option in action


                    DSO Solution Progress




                                            Trace width
 Design Validation                Optimization             Final System Verification




                     Optimize 3D Routing
3D EM Based circuit co-design
  Changed Routing
       Trace length and spacing
  Crosstalk analysis
       Improved Case
  Component Editor
                                                                Nominal Case




                                                                     Improved Case


                     TM   ®
       DesignerSI /Nexxim
         Schematic view                          Near-End Crosstalk noise data
                                                          Tr=200ps
  Design Validation      Optimization            Final System Verification




     Optimize Simulation Run Times
DSO Setup
  25 Parametric Case
  HeadNode: Dual-Dual-Core
  AMD 2.2GHz 16GB RAM
  Nodes: 16 Dual Processor
  AMD 2.6GHz 8GB RAM
Nominal Case
  6 hrs 51 min
DSO Solution Time
  26 min !!!

                                                         6hr 51 min
Time Savings
  15x speed up !

                             DSO Solution Time
  Design Validation                 Optimization                    Final System Verification




                      Thermal Effects
             TM
ePhysics
  Critical 3D Thermal and stress
  analysis
  Solderball interconnect reliability
  Stress induced strains in solder
  joints



                                                    Thermal distribution on bondwires
                                                       Single vs. double bondwire




                          Thermal distribution wire pads
                             No wirebonds present
  Design Validation             Optimization   Final System Verification




             TM
                      Mechanical Effects
ePhysics
  Reduced design cycle time limits
  the use of testing to evaluate
  reliability.
  Stress induced strains in solder
  joints
Design Validation   Optimization   Final System Verification




      Final System Verification
          Input/Output driver effects
                Eye Diagram
                    Jitter
                Design Validation                                                                   Optimization       Final System Verification




                                  Final System Verification
                                                                                                                   ®
               Time domain simulations using Nexxim
                    Rise time = 200 ps
                    Dynamically linked parameterized Q3D project
                    IBIS v4.0 driver model for DDR 2

           1
                        Vcc                                vcc2
                                      1e-009
                                                                         0.1pF




1.8V

                                                                                         U1
                                                                                         Nexxim2
                1




       0                                        pullup               0
                                                                          Port1
                                                                           Tx               Port2
                 E244             logic_in                 out
                                                                                                     0
                                                                                 0.1pF




                                  enable                 out_of_in



                                               pulldown




                              0
                                                                                 1




                                                                            0
               Conclusion (v1)
Top Package   Bottom Package
 Vendor A        Vendor B

                           Automation


           System          Initial Design
         Performance         Validation


                                Electrical,
         Optimization          Thermal and
                               Mechanical


        Final System       System Jitter,
         Verification      Eye Diagram
            Acknowledgments
Special Thanks to:

  NXP

  Tessera

  Amkor

  for their contribution and assistance with creating
  this material.

								
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