DESIGN HINTS AND ISSUES
Printed Circuit Board
Design Considerations by PETER ALFKE x (firstname.lastname@example.org)
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teady advances in IC technology have This means that the PCB plays an important
fueled 30 years of rapid progress in digital role in controlling the integrity of interconnect
system speed and complexity. In the past, signals. Trace width and trace spacing as low as
system speed was determined by gate and 4 mils (0.1 mm), controlled line impedance, and
register performance, and you could easily multi-layer boards with clean ground and Vcc
take advantage of ever faster, bigger, and planes, are all required to minimize reflections,
cheaper integrated circuits. ground bounce, and crosstalk. Maintaining
The printed circuit board (PCB) was just a clock integrity is a big problem.
means to hold ICs in
place; PCB layout was an Year Max.System PC-Board PC-Board IC Design
exercise in topology and Clock Complexity Min.Trace Width Rules
22 economics. Analog issues
such as crosstalk, phase
1965 1 MHz
1980 10 MHz
100 mil = 2.5 mm
20 mil = 0.5 mm
and amplitude distortion, 1995 100 MHz 4-8 layers 4 mil = 0.1 mm 0.5µ
reflections, ground 2010 ? 1000 MHz 8-16 layers 1 mil = 25 µ 0.1µ
bounce and so on could
thus safely be ignored, or treated as minor
irritants, because synchronous digital logic is Time Domain vs Frequency Domain
forgiving in amplitude and timing variations. Digital designers usually express delays and
Times have changed. At today’s circuit rise times in the time domain, while analog
speed, the PCB and its analog characteristics designers often use the frequency domain to
play a strong, if not dominating, role in deter- describe circuit and component performance.
mining digital system performance. The frequency domain is more meaningful for
CMOS ICs are no longer the slow and forgiv- analyzing many analog phenomena. For rough
ing circuits of the past. They are now as fast as estimates, we can easily convert rise and fall
(if not faster than) the fastest TTL circuits; out- times into a frequency spectrum as follows:
puts ramp between 0 and 5 volts in 1 ns, clock There is a knee frequency
rates approach 150 MHz, and ICs have up to F = 0.5•(1/ (Trise or Tfall))
500 signal connections to accommodate mul-
For analyzing circuit behavior, it is suffi-
tiple 32-bit wide busses. The trend is moving
cient to evaluate the frequency response up to
toward much higher speed and far more I/Os.
the knee frequency, but there is no need to go
However, signals still travel along PCB
traces at only half the speed of light, and
For a typical rise time of 2 ns, the knee
sharp signal edges get reflected at every trace
frequency is 250 MHz. When low-pass circuits
discontinuity. You must now not only control
are cascaded, the resulting transition time is
the source-to-destination path, but you must
the square root of the sum of the squared
also pay attention to the complete circuit loop
transition times. For example:
and its inductance, from the positive power
® A 250 MHz scope with a 250 MHz probe
supply terminal back to the negative terminal,
displays a 2 ns rise time as a 3.5 ns rise
then through the decoupling capacitors back
time (√22 + 22 + 22). This is a +75% error.
to the positive supply terminal.
® A 500 MHz scope with a 500 MHz scope Transmission Lines Figure 1.
probe displays a 2 ns rise time as a 2.4 ns Short connections can be treated
rise time (√22 + 12 + 12). This is only a as lumped capacitors, but any line
+20% error. with a propagation delay of more
Beware of slow scopes and slow scope probes. than 30% of the signal transition
time must be analyzed as a trans-
mission line. With a 3-ns transition
® Min. trace width: typically 10 mil
time, any line longer than six
(0.25 mm), down to 4 mil (0.1 mm)
inches (15 cm) is a transmission
® Min. trace pitch: twice trace width
line. With a 1-ns transition time,
® Hole diameter: 20 mil, down to 8 mil
any line longer than two inches (5
(0.5 mm to 0.2 mm). Thin traces and small
cm) is a transmission line.
holes make the board more expensive.
® Layer thickness: typically 8 mil (0.2 mm), Characteristic Impedance
down to 4 mil (0.1 mm). The dielectric of a PCB Trace
constant ε is 4.5 for typical FR4 PCB ® 50 Ω for outer trace, width = 2x PCB layer
thickness (microstrip). Figure 2.
® 75 Ω for outer trace, width = 1x
Beware of Trace Inductance
PCB layer thickness (microstrip).
A 0.5-inch long, 10-mil wide trace, over an
® 50 Ω for inner trace, width =
8-mil thick PCB layer, connected to the under-
0.6x PCB layer thickness
lying ground plane through a 14-mil via at the
end, has an inductance of 9 nH. To a 2-ns rise
® 75 Ω for inner trace, width =
time, this is an impedance of 15 Ω.
0.25x PCB layer thickness
Typical Lumped Parameters (stripline).
® Capacitance - A narrow trace has a capaci- Higher characteristic impedances
tance of 2 pF per inch (0.8 pF per cm). are unrealistic on modern PCBs.
Copper area has 130 pF per square inch (20
How to Prevent Signal Degradation
pF per cm2). Due to Reflections (Ringing)
® Ceramic decoupling capacitors have a ® Keep the trace short (best solution, but
series resistance of several ohms, and an often impossible).
inductance of 3 to 30 nH. Use several Figure 3.
® Terminate at the destination
capacitors in parallel to lower the high- (end termination). (See Figure1.)
frequency impedance. Problem: High sink or source
® Via capacitance is 0.5 pF (insignificant) current, or both. High power
but the inductance of >1 nH can be consumption.
significant for very fast transitions Solution: Capacitive coupling to
(3 Ω for a 1-ns transition). the terminating resistor. Time
® Inductance - A 1-inch long wire (25 mm) constant should be longer than
has an inductance of 80 nH, which at 100 the transition, but much shorter
MHz means 50 Ω (definitely not a short than the flat time. For example:
circuit). 200 pF x 50 Ω = 10 ns.
® Resistance - 1/4 W axial resistors have a See Figure 2.
series inductance of 2.5 nH and a parallel ® Terminate at the source
capacitance of ~2 pF. 1/8 W axial resistors (series termination).
have 1 nH and <2 pF. Advantage: No static power consumption.
PCB Design Problem: Use only for single-destination. only matter at setup time before the next active
Continued from 50% amplitude along the trace! clock edge. However, beware of all asynchronous
the previous page See Figure 3. inputs and clocks — they are susceptible to mis-
Signals propagate at the speed of light di- interpretation due to ground bounce. Make sure
vided by the square root of the effective dielec- these signals are parked far away from the input
tric constant. The speed is therefore higher on thresholds.
the outer traces that have air on one side, than Crosstalk
on the inner traces that are completely sur- Crosstalk is especially strong when many lines
rounded by epoxy. run closely parallel, as in data busses. Inductive
® Propagation delay on an outer trace: crosstalk is usually bigger than capacitive.
140 ps per inch ( 55 ps per cm ). Crosstalk can be minimized by using an unob-
® Propagation delay on an inner trace: structed ground plane. Synchronous busses can
180 ps per inch ( 70 ps per cm ). tolerate a lot of crosstalk if it occurs only after the
Ground Plane synchronous data transitions.
Always analyze the whole current loop: Vcc
Problem: Asynchronous control lines, strobes,
terminal to Vcc distribution, to Vcc-pin, to
interrupts that run parallel to the data or ad-
device output, to PCB trace, to ground distribu-
tion, to ground terminal, through the
Solution: Increase the spacing.
decoupling capacitors, and back to Vcc. Keep
24 this loop inductance as small as possible by Vcc Decoupling Capacitors
reducing the area of the loop. The return cur- Supply decoupling is not a luxury. For fast
rent tries to follow the signal trace; it follows internal and external transitions, these capacitors
the path of least inductance (least energy). are the only instant source of current. The power
® Make it easy for the signal and return paths supply with its big electrolytic capacitor is too far
to stay close together. away and has too much inductance. (See XCell
® Avoid obstacles in the ground plane. #20, pages 42-43). Low-impedance ceramic
® Investigate the reason for any detour of the decoupling capacitors are required to supply
current. dynamically changing Icc inside the chip, and to
® Watch out for slots in the ground plane provide a return path for external current
causing detours in the return path, leading changes. In CMOS systems, all power is dynamic.
to crosstalk and ringing. The instantaneous current peaks are much higher
than the average dc current, which is between
100 mA and 2 A for the larger Xilinx devices.
Ground bounce is caused by a voltage drop
Decoupling capacitors must have low induc-
on the inductance between chip internal
tance and low series resistance. The capacitance
ground (bonding wire + leadframe, especially
value is irrelevant, as long as it is sufficient. Use
in ceramic PGAs) and PCB ground. The pulse
0.01 to 0.1 µF capacitors, mounted very close to
width increases with capacitive loading, but the
each Vcc pin and directly connected to the
pulse amplitude is independent of capacitive
ground plane. Keep the lines very short. A nar-
loading. Ground bounce can cause wrong
row, 0.25-inch (6 mm) long trace represents 20
output levels on adjacent outputs and can
nH; a current change of 100 mA/ns causes a
cause inputs to be misinterpreted. For a High-
voltage drop of 2 volts across this inductance.
to-Low transition, the internal ground jumps
first to a positive voltage, then undershoots. Credits
(See the 1998 Xilinx Data Book, pages 13-16) For an excellent, in-depth treatment of these
Synchronous designs with one common subjects, read “High-Speed Digital Design” by
clock are surprisingly resilient. They tolerate Johnson and Graham, Prentice Hall, 1993, or attend
ground bounce, because it occurs directly after a class given by the author, Howard W. Johnson,
the triggering clock edge, whereas input levels Redmond WA. (email@example.com). x