CSP (Chip Scale Package) package, chip-scale packaging means. CSP packages the latest generation of memory chip packaging technology, its technical performance has a new upgrade. CSP CSP package installed seal allows the chip area and packaging area ratio exceeds 1:1.14, very close to 1:1 has been the ideal situation, the absolute size is also only 32 square millimeters, about the ordinary BGA 1 / 3, only very TSOP memory chips in the area of ??1 / 6. Compared with the BGA package, under the CSP and the same space can be three times more storage capacity.
Plastic Packages for Integrated Circuits Wafer Level Chip Scale Package (WLCSP) W3x3.9B 3x3 ARRAY 9 BALL WAFER LEVEL CHIP SCALE PACKAGE E (Intersil Standard) SYMBOL MILLIMETERS NOTES A 0.54 Min, 0.65 Max - PIN A1 ID AREA D A1 0.24 ±0.03 - A2 0.355 ±0.03 - b 0.32 ±0.03 - TOP VIEW bb θ 0.30 REF. - D 1.45 ±0.05 - D1 1.00 BASIC - bb E 1.45 ±0.05 - E1 1.00 BASIC - A2 A e 0.50 BASIC - A1 SD 0.00 BASIC - N 9 3 b Rev. 0 6/06 SIDE VIEW NOTES: 1. Dimensions are in Millimeters. E1 2. Dimensioning and tolerancing conform to ASME 14.5M-1994. 3. Symbol “N” is the actual number of solder balls. C 4. Reference JEDEC MO-211-C, variation DD. B SD D1 A 1 2 3 b BOTTOM VIEW 1
Pages to are hidden for
"Plastic Packages for Integrated Circuits Wafer Level Chip Scale "Please download to view full document