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					       INDEX OF 2007 FOCUS ITWG TABLES

       System Drivers
TEXT   Table SYSD1
       Table SYSD2
       Table SYSD3
       Table SYSD4


       Design
TEXT   Table DESN1
       Table DESN2
TEXT   Table DESN3
       Table DESN4
TEXT   Table DESN5
       Table DESN6
TEXT   Table DESN7
       Table DESN8
       Table DESN9
TEXT   Table DESN10
TEXT   Table DESN11
TEXT   Table DESN12

       Test and Test Equipment
TEXT   Table TST1
       Table TST2
       Table TST3
       Table TST4
       Table TST5
       Table TST6
       Table TST7
       Table TST8
       Table TST9
TEXT   Table TST10
       Table TST11
       Table TST12
TEXT   Table TST13
       Table TST14
       Table TST15

       RF and AMS for Wireless
       Table RFAMS1
       Table RFAMS2
       Table RFAMS3
       Table RFAMS4
       Table RFAMS5
       Table RFAMS6
       Table RFAMS7
       Table RFAMS8

       Process Integration, Devices, and Structures (PIDS)
TEXT   Table PIDS1
       Table PIDS2
       Table PIDS3a and b
       Table PIDS3c and d
       Table PIDS4
       Table PIDS5
TEXT   Table PIDS6
       Table PIDS7

       Emerging Research Devices
TEXT   Tables ERD 1-10 are text tables. For ease of editing, please use the Word file found online at:

       Emerging Research Materials
TEXT   Tables ERM 1-8 are text tables. For ease of editing, please use the Word file found online at:

       Front End Processes
TEXT   Table FEP1
       Table FEP2
       Table FEP3
       Table FEP4a
       Table FEP4b
       Table FEP5
       Table FEP6
       Table FEP7
       Table FEP8
       Table FEP9

       Lithography
TEXT   Table LITH1
TEXT   Table LITH2
       Table LITH3
       Table LITH4a and b
       Table LITH4c
       Table LITH5a and b
       Table LITH5c and d
       Table LITH5e and f
       Table LITH6

       Interconnect
TEXT   Table INTC1
       Table INTC2
       Table INTC3
       Table INTC4
TEXT   Table INTC5
       Table INTC6
       Table INTC7

       Factory Integration
TEXT   Table FAC1
TEXT   Table FAC2
       Table FAC3
       Table FAC4
       Table FAC5
       Table FAC6
       Table FAC7
TEXT   Table FAC8
TEXT   Table FAC9

       Assembly and Packaging
TEXT   Table AP1
       Table AP2
       Table AP3
       Table AP4
       Table AP5a and b
       Table AP5c and d
       Table AP6
       Table AP7
TEXT   Table AP8
       Table AP9
TEXT   Table AP10
       Table AP11
       Table AP12a and b
TEXT   Table AP12c
TEXT   Table AP13
TEXT   Table AP14
       Table AP15
TEXT   Table AP16
TEXT   Table AP17
TEXT   Table AP18
TEXT   Table AP19
       Table AP20
F 2007 FOCUS ITWG TABLES


            Major Product Market Segments and Impact on System Drivers                            http://www.itrs.net/ITWG/word_file
            SOC Consumer Driver Design Productivity Trends
            Projected Mixed-Signal Figures of Merit for Four Circuit Types
            Embedded Memory Requirements—Near and Long-term Years




            Overall Design Technology Challenges                                                  http://www.itrs.net/ITWG/word_file
            System-Level Design Requirements—Near and Long-term Years
            Correspondence Between System-Level Design Requirements and Solutions                 http://www.itrs.net/ITWG/word_file
            Logical/Circuit/Physical Design Technology Requirements—Near and Long-term Years
            Correspondence Between Logical/Circuit/Physical Requirements and Solutions            http://www.itrs.net/ITWG/word_file
            Design Verification Requirements—Near and Long-term Years
            Correspondence Between Design Verification Requirements and Solutions                 http://www.itrs.net/ITWG/word_file
            Design for Test Technology Requirements—Near and Long-term Years
            Design for Manufacturability Technology Requirements—Near and Long-term Years
            Correspondence Between Design for Manufacturability Requirements and Solutions        http://www.itrs.net/ITWG/word_file
            Near-term Breakthroughs in Design Technology for AMS                                  http://www.itrs.net/ITWG/word_file
            Design Technology Improvements and Impact on Designer Productivity                    http://www.itrs.net/ITWG/word_file


est Equipment
           Summary of Key Test Drivers, Challenges, and Opportunities                             http://www.itrs.net/ITWG/word_file
           Multi-site Test for Product Segments—Near and Long-term Years
           System on Chip Test Requirements—Near and Long-term Years
           Logic Test Requirements—Near and Long-term Years
           Vector Multipliers
           Memory Test Requirements—Near and Long-term Years
           Mixed-signal Test Requirements—Near-term Years
           RF Test Requirements—Near and Long-term Years
           Burn-in Requirements—Near and Long-term Years
           Test Handler and Prober Difficult Challenges                                           http://www.itrs.net/ITWG/word_file
           Prober Requirements—Near and Long-term Years
           Handler Requirements—Near and Long-term Years
           Probing Difficult Challenges
           Wafer Probe Technology Requirements—Near and Long-term Years
           Test Socket Technology Requirements—Near and Long-term Years

MS for Wireless
            RF and Analog Mixed-Signal CMOS Technology Requirements—Near and Long-term years
            RF and Analog Mixed-Signal Bipolar Technology Requirements—Near and Long-term years
            On-Chip Passives Technology Requirements—Near and Long-term years
            Embedded Passives Technology Requirements—Nearand Long-term years
             Power Amplifier Technology Requirements—Near and Long-term years
             Base Station Devices Technology Requirements—Near and Long-term years
             Millimeter Wave 10 GHz–100 GHz Technology Requirements
             RF and Analog Mixed-Signal RFMEMS

tegration, Devices, and Structures (PIDS)
             Process Integration Difficult Challenges—Near and Long-term Years                            http://www.itrs.net/ITWG/word_file
             High-performance Logic Technology Requirements—Near and Long-term Years
             Low Standby Power Technology Requirements—Near and Long-term Years
             Low Operating Power Technology Requirements—Near and Long-term Years
             DRAM Technology Requirements—Near and Long-term Years
             Non-volatile Memory Technology Requirements—Near-term Years
             Reliability Difficult Challenges                                                             http://www.itrs.net/ITWG/word_file
             Reliability Technology Requirements—Near and Long-term Years

Research Devices
D 1-10 are text tables. For ease of editing, please use the Word file found online at:                    http://www.itrs.net/ITWG/word_file


Research Materials
M 1-8 are text tables. For ease of editing, please use the Word file found online at:                     http://www.itrs.net/ITWG/word_file



             Front End Processes Difficult Challenges
             Starting Materials Technology Requirements—Near and Long-term Years                          http://www.itrs.net/ITWG/word_file
             Front End Surface Preparation Technology Requirements—Near and Long-term Years
             Thermal, Thin Film, Doping and Etching Technology Requirements—Near-term Years
             Thermal, Thin Film, Doping and Etching Technology Requirements—Long-term Years
             DRAM Stacked Capacitor Technology Requirements—Near and Long-term Years
             DRAM Trench Capacitor Technology Requirements—Near and Long-term Years
             FLASH Non-volatile Memory Technology Requirements
             Phase Change Memory (PCM) Technology Requirements—Near and Long-term Years
             FeRAM Technology Requirements—Near and Long-term Years


             Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography
                                                                                                       http://www.itrs.net/ITWG/word_file
             Lithography Difficult Challenges                                                          http://www.itrs.net/ITWG/word_file
             Lithography Technology Requirements—Near and Long-term Years
             Resist Requirements—Near and Long-term Years
             Resist Sensitivities
             Optical Mask Requirements—Near and Long-term Years
             EUVL Mask Requirements—Near and Long-term Years
             Imprint Template Requirements—Near and Long-term Years
             Maskless Technology Requirements—Near and Long-term Years


             Interconnect Difficult Challenges                                                            http://www.itrs.net/ITWG/word_file
             MPU Interconnect Technology Requirements—Near and Long-term Years
            DRAM Interconnect Technology Requirements—Near and Long-term Years
            Interconnect Surface Preparation Technology Requirements—Near and Long-term Years
            Options for Interconnects Beyond the Metal/Dielectric System                             http://www.itrs.net/ITWG/word_file
            High Density Through Silicon via Draft Specification
            M inimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivity


             Factory Integration Difficult Challenges—Near and Long-term Years                   http://www.itrs.net/ITWG/word_file
             Key Focus Areas and Issues for FI Functional Areas Beyond 2007                      http://www.itrs.net/ITWG/word_file
             Factory Operations Technology Requirements—Near and Long-term Years
             Production Equipment Technology Requirements—Near and Long-term Years
             Material Handling Systems Technology Requirements—Near and Long-term Years
             Factory Information and Control Systems Technology Requirements—Near and Long-term Years
             Facilities Technology Requirements—Near and Long-term Years
             Crosscut Issues Relating to Factory Integration                                     http://www.itrs.net/ITWG/word_file
             List of Next Wafer Size Challenges                                                  http://www.itrs.net/ITWG/word_file


and Packaging
            Assembly and Packaging Difficult Challenges                                              http://www.itrs.net/ITWG/word_file
              Single-chip Packages Technology Requirements—Near and Long-term Years
            Chip-to-package Substrate Technology Requirements—Near and Long-term Years
            Substrate to Board Pitch—Near and Long-term Years
            Package Substrates—Near and Long-term Years
            Package Substrate Design Parameters—Near and Long-term Years
            Wafer Level Packaging—Near and Long-term Years
            Key Technical Parameters for Stacked Architectures Using TSV
            Comparison of SoC and SiP Architecture                                                   http://www.itrs.net/ITWG/word_file
            Package Level System Integration
            Processes for SiP
            System in Package Requirements—Near and Long-term Years                                  http://www.itrs.net/ITWG/word_file
            Thinned Silicon Wafer Thickness 200 mm/300 mm—Near and Long-term Years
            Challenges and Potential Solutions in Thinning Si Wafers
            SiP Failure Modes                                                                        http://www.itrs.net/ITWG/word_file
            Some Common Optoelectronic Packages and Their Applications                               http://www.itrs.net/ITWG/word_file
            Protocol with Distance
            Optoelectronic Packaging Challenges and Potential Solutions                              http://www.itrs.net/ITWG/word_file
            MEMS Packaging Methods                                                                   http://www.itrs.net/ITWG/word_file
            MEMS Packaging Examples                                                                  http://www.itrs.net/ITWG/word_file
            Materials Challenges                                                                     http://www.itrs.net/ITWG/word_file
            Package Substrate Physical Properties
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INDEX LINK   Table SYSD1        Major Product Market Segments and Impact on System Drivers

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK                        Table SYSD2                                 SOC Consumer Driver Design Productivity Trends
                                                                              2007   2008   2009   2010   2011   2012   2013   2014
             Trend: SOC total logic size                                       1     1.29   1.62   2.12   2.64   3.24   4.07   5.29
             (normalized to 2007)
             Requirement: % of reused design                                  38%    42%    46%    50%    54%    58%    62%    66%
             Requirement: Productivity for new designs (normalized to 2007)    1     1.25   1.54   1.96   2.38   2.84   3.47   4.37

             Requirement: Productivity for reused designs (normalized to       2     2.51   3.08   3.92   4.76   5.68   6.94   8.74
             productivity for new designs at 2007)
ctivity Trends
                 2015    2016    2017    2018    2019    2020    2021    2022
                 6.62    8.52    10.33   12.76   16.17   21.14   24.6    34.4

                 70%     74%     78%     82%     86%     90%     92%     94%
                 5.31    6.63    7.78     9.3    11.38   14.36   16.4    22.51

                 10.62   13.26   15.56   18.59   22.75   28.71   32.79   45.02
INDEX LINK   Table SYSD3                       Projected Mixed-Signal Figures of Merit for Four Circuit Types
                   Year of Production             2007               2010              2013              2016              2019
                   RF-CMOS ½ Pitch                 65                 45                32                22                18
             FoM LNA (GHz)                         20               28–32             40–50             50–80             60–90
             FoM VCO (1/J) ×10 22                  1.4             1.5–1.7            1.8–2             2–2.4             2.4–3
             FoM PA (W×GHz 2 ) ×10 4               15                30               50–70            90–100            110–130
             FoM ADC (GHz/W) ×10 3                 1.5              2–2.5            2.5–3.5             3–5               4–6

             [1]
             [1] Lower bound is for "high-resolution/thermal noise limited" A/D converters; upper bound is for "low-resolution/speed limited" A/D converters.
                        2022                        Driver
                         13
                       70-100       Refer to the RF and AMS
                      2.7–3.5       Technologies for Wireless chapter
                      120-140
                        6–10


esolution/speed limited" A/D converters.
INDEX LINK   Table SYSD4                                                           Embedded Memory Requirements—Near and Long

             Year of Production                                                     2007         2008          2009
             CMOS SRAM High-performance, low standby power (HP/LSTP)
             DRAM ½ pitch (nm), Feature Size – F                                     65           65            65
                              2
             6T bit cell size (F ) [1]                                             140F²         140F²        140F²
             Array efficiency [2]                                                   0.7           0.7          0.7
             Process overhead versus standard CMOS – #added mask layers              2             2            2
             Operating voltage – Vdd (V) [4]                                        1.1          1/1.1        1/1.1
             Static power dissipation (mW/Cell) [5]                              3E-4/1E-6     3E-4/1E-6     3E-4/1E-6

             Dynamic power consumption per cell (mW/MHz) [6]                     4.5E-7/7E-7 4E-7/6.5E-7 4E-7/6E-7
             Read cycle time (ns) [7]                                               0.3/1.5    0.3/1.5    0.3/1.5
             Write cycle time (ns) [7]                                              0.3/1.5    0.3/1.5    0.3/1.5
             Percentage of MBU on total SER                                          16%        16%        16%
             Soft error rate (FIT/Mb) [8]                                            1150       1150       1150
             Embedded Non-Volatile Memory (code/data), DRAM ½ pitch (nm)              90         90         90
                        2                                                            2     2       2     2      2     2
             Cell size (F ) – NOR FLOTOX / NAND FLOTOX [9]                        10F /5F       10F /5F    10F /5F
             Array efficiency – NOR FLOTOX/ NAND FLOTOX [10]                       0.6/0.8       0.6/0.8    0.6/0.8
             Process overhead versus standard CMOS – #added mask layers [3]          6–8           6–8        6–8
             Read operating voltage (V)                                              2V            2V         2V
             Write (program/erase) on chip maximum voltage (V) – NOR/NAND [11]    12V/15V       12V/15V    12V/15V
             Static power dissipation (mW/cell) [5]                               1.00E-06      1.00E-06   1.00E-06
             Dynamic power consumption per cell (mW/MHz) [6]                      6.00E-09      6.00E-09   6.00E-09
             Read cycle time (ns) – NOR FLOTOX / NAND FLOTOX [7]                   Oct-50        Oct-50     Oct-50
             Program time per cell (µs) – NOR FLOTOX / NAND FLOTOX [12]          1.0/1000.0    1.0/1000.0 1.0/1000.0
             Erase time per cell (ms) – NOR FLOTOX / NAND FLOTOX [12]             10.0/0.1      10.0/0.1   10.0/0.1
             Data retention requirement (years) [12]                                  10            10         10
             Endurance requirement [12]                                            100000        100000     100000
             Embedded DRAM, ½ pitch (nm)                                             90            90         65
                                  2
             1T1C bit cell size (F ) [13]                                          12–30        12–30         12–30
             Array efficiency [2]                                                    0.6          0.6           0.6
             Process overhead versus standard CMOS – #added mask layers [3]          3–5          3–5           3–5
             Read operating voltage (V)                                               2            2            1.8
             Static power dissipation (mW/Cell) [5]                               1.00E-11     1.00E-11      1.00E-11
             Dynamic power consumption per cell (mW/MHz) [6]                      1.00E-07     1.00E-07      1.00E-07
             DRAM retention time (ms) [12]                                            64           64            64
             Read/Write cycle time (ns) [7]                                          0.7          0.7           0.5
             Soft error rate (FIT/Mb) [8]                                             60           60            60
ory Requirements—Near and Long-term Years

              2010          2013             2016             2019             2022

               45            35               25               18               13
                                   2                2                2                2
              140F²         140F             140F             140F             140F
               0.7           0.7              0.7              0.7              0.7
                2             2                2                2                2
                1           0.9/1    0.8/0.9     0.7/0.8   0.7/0.8
           5E-4/1.2E-6 1E-3/1.5E-6 2E-3/2E-6 3E-3/2.5E-6 5E-3/3E-6
                       2.5E-7/4.5E-
            3E-7/5E-7        7      2E-7/4E-7 1.5E-7/3E-7 1E-7/2E-7
             0.2/1.2     0.15/0.8    0.1/0.5    0.07/0.3   0.07/0.3
             0.2/1.2     0.15/0.8    0.1/0.5    0.07/0.3   0.07/0.3
              32%          64%        100%       100%       100%
              1200         1250       1300        1350       1400
               65           45         35          25         18
                2     2       2        2       2        2       2        2       2        2
             10F /5F       10F /5F          10F /5F          10F /5F          10F /5F
              0.6/0.8       0.6/0.8          0.6/0.8          0.6/0.8          0.6/0.8
                6–8           6–8              6–8              6–8              6–8
               1.8V          1.5V             1.3V             1.2V             1.1V
             12V/15V       12V/15V          12V/15V          12V/15V          12V/15V
             1.00E-06      1.00E-06         1.00E-06         1.00E-06         1.00E-06
             6.00E-09      4.00E-09         3.50E-09         3.00E-09         3.00E-09
              Jul-35        25-May           3.5/18           2.5/12           10-Feb
            1.0/1000.0    1.0/1000.0       1.0/1000.0       1.0/1000.0       1.0/1000.0
             10.0/0.1      10.0/0.1         10.0/0.1         10.0/0.1         10.0/0.1
                 10            10               10               10               10
              100000        100000           100000           100000           100000
                65             45               35               25               25
             12–30         12–30            12–30            12–30            12–30
               0.6           0.6              0.6              0.6              0.6
               3–5           3–6              3–6              3–6              3–6
               1.7           1.6              1.5              1.5              1.5
            1.00E-11      1.00E-11         1.00E-11         1.00E-11         1.00E-11
            1.50E-07      1.60E-07         1.70E-07         1.70E-07         1.70E-07
                64            64               64               64               64
               0.4           0.3             0.25              0.2              0.2
                60            60               60               60               60
INDEX LINK   Table DESN1             Overall Design Technology Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table DESN2                                                               System-Level Design Requirements—Near and Long-term
             Year of Production                                                        2007      2008     2009     2010
             Design Reuse
             Design block reuse [1] % of all logic                                      35%      36%      38%      40%
             Platform Based Design
             Available platforms [2] Normalized to 100% in the start year [3]           87%      83%      75%      70%
             Platforms supported [4] % of platforms fully supported by tools [5]        10%      25%      35%      50%

             High Level Synthesis
             Accuracy of high level estimates (performance, area, power, costs) [6]     60%      63%      66%      70%
             % versus measurements
             Reconfigurability
             SOC reconfigurability [7] % of SOC functionality that is reconfigurable    28%      28%      30%      35%

             Analog/Mixed Signal
             Analog automation [8] % versus digital automation [9]                      17%      17%      24%      24%
             Modeling methodology, description languages, simulation environments       55%      58%      60%      62%
             [10] % vs. digital methodology
irements—Near and Long-term Years
              2011     2012     2013   2014   2015   2016   2017   2018   2019   2020

              41%      42%      44%    46%    48%    49%    51%    52%    54%    55%

              60%      55%      52%    48%    45%    43%    40%    37%    35%    32%
              57%      64%      75%    80%    85%
                                                     90%    92%    94%    95%    97%

              73%      76%      80%    83%    86%
                                                     90%    92%    94%    95%    97%

              38%      40%      42%    45%    48%
                                                     50%    53%    56%    60%    62%

              27%      30%      32%    35%    38%    40%    43%    46%    50%    52%
              65%      67%      70%    76%    78%
                                                     80%    83%    86%    90%    92%
2021   2022

57%    58%

29%    27%

99%    100%


99%    100%


65%    68%

55%    58%

95%    98%
INDEX LINK   Table DESN3       Correspondence Between System-Level Design Requirements and Solutions

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table DESN4                                                            Logical/Circuit/Physical Design Technology Requiremen
             Year of Production                                                     2007   2008   2009    2010   2011
             Asynchronous global signaling:                                          7%    11%    15%     17%    19%
             % of a design driven by handshake clocking
             Parameter uncertainty:%-effect (on signoff delay)                      6%      8%     10%    11%     11%
             Simultaneous analysis objectives:                                       4       5      6      6       6
             # of objectives during optimization
             Circuit families: # of families in a single design                      3       3      4       4      4
             Synthesized analog content: % of total design analog content           15%    16%     17%    18%     19%
             Full-chip leakage (normalized to full-chip leakage power dissipation    1      1.5     2      2.5    2.75
             in 2007)
Design Technology Requirements—Near and Long-term Years
             2012   2013   2014   2015   2016   2017      2018   2019   2020   2021   2022
             20%    22%    23%    25%    30%    30%       30%    35%    40%    43%    45%

             12%    14%    15%    18%    20%     20%      20%    22%    25%    26%    28%
              6      7      8      8      8       8        8      8      8      8      8

              4       4     4      4      4       4        4      4      4      4      4
             20%    23%    25%    28%    30%     35%      40%    45%    50%    55%    60%
              3      3.5    4      6      8       8        8      8      8      8      8
INDEX LINK   Table DESN5        Correspondence Between Logical/Circuit/Physical Requirements and Solutions

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
rements and Solutions
INDEX LINK   Table DESN6                                                        Design Verification Requirements—Near and Long-term Year
             Year of Production                                                 2007      2008     2009     2010
             Productivity
             Design size verifiable by 1 engineer-year (in millions of           7.9      10.3     13.5      17.6
             transistors - based on an SOC design and a 10-person
             engineering team) [1]
             Methodology
             Design errors exposed using formal or semi-formal verification      4.7      7.1       9.4      11.8
             (%, versus simulation)
             Effort spent on system-level verification: software, hardware       11.6     13.1     14.7      16.3
             and electrical effects (%)
             Portion of the design specification formalized for verifiability    13.8     17.5     21.3      25
             (%)
             Bugs
             Escape rate: bugs found after first tapeout (per each 100K lines     8        7        7         7
             of design code)
             Bugs found after system integration until tapeout (per each         62        68       74       79
             100K lines of design code)
             Reuse
             Portion of the verification infrastructure (e.g., test beds,        73.9     70.8     67.8      64.7
             coverage, checkers) which is newly developed (versus reused
             components and acquired IP) (%) [2]
             Portion of the verification infrastructure which is acquired        15.5     18.3     21.1      23.8
             from third parties (i.e., verification IP) (%) [2]
             Functional coverage
             Portion of design for which verification quality is evaluated       46.5     49.7     52.9      56.2
             through functional coverage (%)
             Coverage goal density (expressed as number of coverage goals       1294      1608     1922     2235
             for each million transistors of the design) [3]
rements—Near and Long-term Years
              2011     2012        2013   2014   2015   2016   2017   2018    2019    2020

              23.1     30.3        39.8   52.3   69.6   91.8   121    159.7   210.9   278.6




              14.1     16.5        18.8   21.2   23.5   25.9   28.2   30.6    32.9    35.3

              17.8     19.4        20.9   22.5   24.1   25.6   27.2   28.8    30.3    31.9

              28.8     32.5        36.3    40    43.8   47.5   51.3    55     58.8    62.5


               6        6           6      6      5      5      5      4       4       4

               85       91          97    103    109    115    121    126     132     138


              61.6     58.6        55.5   52.5   49.4   46.4   43.3   40.2    37.2    34.1


              26.6     29.4        32.1   34.9   37.6   40.4   43.2   45.9    48.7    51.5


              59.4     62.6        65.9   69.1   72.4   75.6   78.8   82.1    85.3    88.5

              2549     2863        3176   3490   3804   4118   4431   4745    5059    5373
2021    2022

368.5   487.6




37.6     40

33.4     35

66.25    70


 3       3

144     150


31.1     28


54.2     57


91.8     95

5686    6000
INDEX LINK   Table DESN7            Correspondence Between Design Verification Requirements and Solutions

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
nts and Solutions
INDEX LINK   Table DESN8                                                             Design for Test Technology Requirements—Near and Lon
             Year of Production                                                      2007   2008   2009   2010   2011
             System Driver: Analog/Mixed-signal/RF
             All-digital DFT for analog/mixed-signal/RF circuits and systems.         40     45     50     55     60
             % digital circuits in DFT implementations
             Correlation of DFT results with existing specification-based test        40     45     50     55     60
             methods. % results correlated
             Availability of fault/defect models for DFT-oriented test methods. %     25     30     35     40     45
             AMS/RF blocks with accepted fault models
             System Drivers: MPU/PE/DSP
             DFT coverage of digital blocks or subsystems. % blocks with DFT          70     70     70     75     75
             DFT for delay test of critical paths. % paths covered                    55     55     60     60     60
             DFT for fault tolerance in logic blocks.                                 40     40     45     45     50
             % blocks with fault tolerance
             System Drivers: Memories
             DFT for yield improvement.                                               85     90     90     90     90
             General SOC/SIP requirements
             DFT support for logic and other non-memory circuit repair.               50     60     60     60     70
             % blocks with repair
             DFT reuse for performance calibration, and measurement purposes.         35     35     40     40     40
             % DFT circuits reused
             DFT impact on system performance (noise, power, sensitivity,             15     15     10     10     10
             bandwidth, etc.). % performance impact (aggregate figure of merit)
             DFT efficacy in test volume reduction. Reduction factor                  5×     5×     5×     10×    10×
             DFT / ATE interface standard, including DFT control via standard test    45     45     50      50     60
             access protocols. % of test interface standardized
gy Requirements—Near and Long-term Years
             2012   2013   2014   2015     2016   2017   2018   2019   2020   2021   2022

              60     60     60     80       85     90     90    100    100    100    100

              60     60     60     80       85     90     90    100    100    100    100

              50     55     60     65       70     75     80     85     90     95    100


              75     80     80     85
              60     70     70     70       85     90     90     95     95    97.5   100
              50     55     55     60       80     80     90     90    100    100    100
                                            65     70     80     90    100    100    100

              95     95     95     95       98     98     98    100    100    100    100

              70     70     80     80       80     90     90    100    100    105    110
                                            60     60     70     70     70    72.5    75
              45     45     50     50

              10     10     10     10       5      5      5      5      5      5      5


             10×    20×    20×    20×      20×    50×    50×    50×    50×    50×    50×
              60     70     70     75       90     80     90    100    100    100    100
INDEX LINK   Table DESN9                                                  Design for Manufacturability Technology Requirements—N
             Year of Production                                               2007       2008       2009       2010
             Normalized mask cost from public and IDM data                  1         1.3        1.7        2.3
             % Vdd variability: % variability seen in on-chip circuits     10%       10%        10%        10%
             % Vth variability: doping variability impact on Vth,
             (minimum size devices, memory)                                31%       35%        40%        40%
             % Vth variability: includes all sources                       33%       37%        42%        42%
             % Vth variability: typical size logic devices, all sources    16%       18%        20%        20%
             % CD variability                                              12%       12%        12%        12%
             % circuit performance variability
               circuit comprising gates and wires                          46%       48%        49%        51%
             % circuit total power variability
               circuit comprising gates and wires                          56%       57%        63%        68%
             % circuit leakage power variability
               circuit comprising gates and wires                         124%       143%       186%       229%
ity Technology Requirements—Near and Long-term Years
                 2011       2012       2013       2014       2015      2016      2017      2018      2019      2020
               3         3.9        5.1        6.6        8.7       11.4      14.9      19.6      25.6      33.6
              10%       10%        10%        10%        10%        10%       10%       10%       10%       10%

              40%       58%        58%        81%        81%        81%       81%       112%      112%      112%
              42%       58%        58%        81%        81%        81%       81%       112%      112%      112%
              20%       26%        26%        36%        36%        36%       36%       50%       50%       50%
              12%       12%        12%        12%        12%        12%       12%       12%       12%       12%

              60%       63%        63%        63%        63%        63%       65%       66%       69%       69%

              72%       76%        80%        84%        88%        92%       96%       102%      110%      121%

             255%       281%       287%       294%       331%       368%      381%      395%      360%      325%
   2021      2022
44.2      57.7
10%       10%

112%      112%
112%      112%
50%       50%
12%       12%

71%       73%

130%      140%

477%      628%
INDEX LINK   Table DESN10       Correspondence Between Design for Manufacturability Requirements and Solutions

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
ts and Solutions
INDEX LINK   Table DESN11        Near-term Breakthroughs in Design Technology for AMS

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table DESN12        Design Technology Improvements and Impact on Designer Productivity

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table TST1     Summary of Key Test Drivers, Challenges, and Opportunities

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table TST2                        Multi-site Test for Product Segments—Near and Long-term Years
                        Year of Production       2007      2008     2009      2010      2011     2012
             High Performance ASIC/MPU
             Wafer test (# of sites)              8         16       16        16        16       32
             Package test (# of sites)            4         8        8         8         8        16
             Low Performance Microcontroller
             Wafer test (# of sites)              32        64       64        64        64       64
             Package test (# of sites)            32        64       64        64        64       64
             Mixed-signal
             Wafer test (# of sites)              4         8        8         16        16       16
             Package test (# of sites)            8         16       16        16        16       16
             Commodity DRAM Memory
             Wafer test (# of sites)              256      512       512      1000      1000     1000
             Package test (# of sites)            256      512       512      512       512      512
             Commodity Flash Memory
             Wafer test (# of sites)              256      512      1000      1000      1000     1000
             Package test (# of sites)            512      512      512       1024      1024     1024
             RF
             Wafer test (# of sites)              4         4        8         8         16       16
             Package test (# of sites)            8         16       32        48        64       64
Long-term Years
              2013     2014   2015   2016   2017   2018   2019   2020   2021   2022

                  32    32     64     64     64     64     64     64     64     64
                  16    16     32     32     32     32     32     32     32     32

                  64    64    128    128    128    128    128    128    128    128
                  64    64    128    128    128    128    128    128    128    128

                  16    16     32     32     64    128    128    256    256    256
                  64    64    128    128    256    256    256    512    512    512

              1000     1000   1000   1000   1000   1000   1000   1000   1000   1000
              512      512    1024   1024   1024   1024   1024   1024   1024   1024

              1000     1000   1000   1000   1000   1000   1000   1000   1000   1000
              1024     1024   2048   2048   2048   2048   2048   2048   2048   2048

                  16    32     32     32     64    128    128    256    256    256
                  64   128    128    128    256    256    256    512    512    512
MPU
MPU

MCU
MCU

Mixed
Mixed

DRAM
DRAM

NAND
NAND

RF
RF
INDEX LINK                         Table TST3                               System on Chip Test Requirements—Near and Long-term Years
             Year of Production                                                    2007        2008        2009        2010        2011
             Embedded Cores: Logic
               Random Pattern Logic BIST
                  Area Investment beyond Scan (%) [1]                          3.1        3.1         3.1         3.1         3.1
               Compressed Deterministic Pattern Test
                  Area Investment beyond Scan (%) [2]                          1.1         1.1         1.2        1.3         1.4
                  Supported Fault Models by ATPG for Overall Test             SA+T        SA+T        SA+T        +SD         +SD
             (SA+T: Stuck-at & Transition, SD: Small Delay, SDX:
             Extended Small Delay, NDF: New Defect-based Fault
             Model)
                  Ratio of Overall Pattern Count per Gate to Stuck-at          ×5         ×5          ×5          × 15        × 15
             Fault Pattern [3]
              Estimation & Requirements for SoC Test Pattern (without
             Core-Parallel Test)
                SAF Pattern Count per Chip (k)                                 11          14          17          22          28
                Overall Pattern Count per Chip (k)                             53          68          85         334         416
                Ratio of Test Application Time per Chip to 2007's [4]         1.00        1.29        1.62        4.24        5.29

                 Ratio of Test Application Time per Gate to 2007's            1.00        0.96        0.93        2.00        2.00
                 = Required Reduction Ratio [5]
                 Required Test Data Volume Compression Ratio [6]               30          51          84         202         314
               DFT Methodology for SoC Level Design
                 DFT method in High Level Design Phase                        DRC         DRC         DRC         +TA         +TA
                 (DRC: DFT Design Rule Check, TA: Testability
             Analysis and Fault Coverage Estimation, SYN: Test
             Synthesis)
                 Application of BISR for Logic Cores                           AH         AH          AH          PA          PA
              (AH: Ad hoc Method, PA: Partially Automated Method,
             LA: Limited Use of Automated Method, GA: General Use of
             Automated Method)
                  DFT/ATPG Approach to Reduce Yield-Loss                       PA         PA          PA          +NA         +NA
                  (PA: Power-Aware DFT/ATPG, NA: Noise Aware
             DFT/ATPG, NAX: Extended Noise-Aware DFT/ATPG)
             Embedded cores: Memory (SRAM)
                  Repairing Mechanism of Memory Cells to improve Yield         RC         RC          RC          RCM         RCM
             [7]
             ( RC: BISR/BISD for a few Row & Col R/D, RCM: for more
             Row & Col R/D, M: for More Sophisticated R/D)
                  Area Investment of BIST/BISR/BISD [8] (Kgates/Mbits)         35          35          35         35          35

                 Standardized High-Speed Memory Test I/F [9] (S: Some,         S           S           S           P           P
             P: Partially, F: Fully)
             Core Integration
                 Standardization of I/F for Reusable IP Cores [10] (P:         P           P           P           P           P
             Partial Use, F: Full Use)
                  Standardization of DFT-ATE I/F [11] (LP: Limited Use         LP         LP          LP          LF          LF
             of Partial Information, LF: Limited Use of Full Information,
             F: General Use of Full Information)
                  SoC Level Fault Coverage [12] (AH: Adhoc, L: Logic,          AH         AH          AH          L+M         L+M
             M: Memory, IO: I/O, A: Analog)
                  Inter-Core/Core-Interface Test (F: Complemental              F           F           F          PA          PA
             Functional Test; PA: Partially Automated ; FA: Fully
             Automated)
             SoC Manufacturing
                 Systematic Hierarchical Diagnosis (L: Logic, M:               L           L           L          +M          +M
             Memory, I: Interface)
    Supported Defect Type for Fault Diagnosis                     C       C       C       +D       +D
(C: Conventional (SAF, TF, BF), D: Delay Fault Model
Considering Defective Delay Size, CT: Cross-talk, TRF:
Transient Response Fault)
    Standardized Diagnosis Interface/Data in the diagnosis       ATE     ATE     ATE     +DFT     +DFT
flow (ATE: Tester Log, DFT: DFT Method, PFA: Physical
Failure Analysis)
    Volume Diagnosis Data Base (SI: Collection and Storing       SI(B)   SI(B)   SI(B)   +SI(G)   +SI(G)
Defect Information (B: Bad sample, G: Good sample), AD:
Automated SoC Diagnosis)

   Manufacturable solutions exist, and are being optimized
                     Manufacturable solutions are known
                              Interim solutions are known    
                 Manufacturable solutions are NOT known
ear and Long-term Years
                    2012        2013        2014        2015 2016         2017         2018         2019         2020         2021



               3.1          3.1         3.1         3.1             3.1          3.1          3.1          3.1          3.1          3.1

               1.5          1.6         1.6         1.7         1.8          1.9           2           2.1          2.1          2.1
               +SD         +SDX        +SDX        +SDX        +NDF         +NDF         +NDF         +NDF         +NDF         +NDF




               × 15        × 30        × 30        × 30         × 60         × 60         × 60        × 120        × 120        × 120




                34           43          56          70          90          109          134          170          222          258
               510         1,283       1,665       2,085       5,370        6,510        8,040        20,370       26,640       30,990
               6.48        10.81       14.03       17.57       30.26        36.69        45.31        76.68        100.28       116.66

               1.90        2.65        2.65        2.65         3.55         3.55         3.55         4.74         4.74         3.67

               496         746         1,257       1,972       3,269        4,805        7,329        11,761       20,116       35,180

               +TA         +TA         +TA         +TA         +SYN         +SYN         +SYN         +SYN         +SYN         +SYN




               PA           LA          LA          LA          GA           GA           GA           GA           GA           GA




               +NA         +NAX        +NAX        +NAX        +NAX         +NAX         +NAX         +NAX         +NAX         +NAX




              RCM           M           M           M               M            M            M            M            M            M




               35           35          35          35              35           35           35           35           35           35

                P           P           P           P               F            F            F            F            F            F


                P           F           F           F               F            F            F            F            F            F

               LF           F           F           F               F            F            F            F            F            F


               L+M         +IO         +IO         +IO              +A           +A           +A           +A           +A           +A

               PA           PA          PA          PA              FA           FA           FA           FA           FA           FA




               +M           +I          +I          +I              +I           +I           +I           +I           +I           +I
 +D       +CT      +CT      +CT     +CT    +TRF   +TRF   +TRF   +TRF   +TRF




+DFT     +PFA     +PFA     +PFA     +PFA   +PFA   +PFA   +PFA   +PFA   +PFA


+SI(G)   +SI(G)   +SI(G)   +SI(G)   +AD    +AD    +AD    +AD    +AD    +AD
2022



       3.1

   2.1
  +NDF




  × 240




   361
  86,700
  217.29

   5.04

  66,721

  +SYN




   GA




  +NAX




       M




       35

       F


       F

       F


       +A

       FA




       +I
+TRF




+PFA


+AD
INDEX LINK   Table TST4                                            Logic Test Requirements—Near and Long-term Years
             Year of Production                                        2007            2008    2009      2010      2011
             Device Characteristics
             # of Transistors (M) — CPU                                 386            486     613       772       973
             # of Transistors (M) — Consumer                            254            344     450       608       773
                                           2
             Chip size at production (mm       ) — CPU                  140            140     140       140       140
                                           2
             Chip size at production (mm       ) — Consumer             64              64      64        64        64
             non differential data rate (GT/s)                           2            2          2         2        3.2
             Internal Scan data rate (MHz)                               50           50         50        75        75
             Single ended External Scan Data rate (Mb/s)                400          400        800       800       800
             Differential External Scan Data rate (Gb/s)                 3            3          3         3         3
             Vdd                                                      0.8–1.1      0.8–1.0    0.8–1.0   0.7–1.0   0.7–1.0
             CPU
             CPU total cores                                             4               4       5         6         6
             CPU Unique cores                                            1               1       2         2         2
             Percentage of Memory transistors                          65%             65%     70%       70%       70%
             Percentage of random logic transistors                     5%              5%      5%        5%        5%
             Percentage of core transistors                            30%             30%     25%       25%       25%
             Transistors per Flip Flop                                  26              26      26        26        26
             Supplies per DUT                                          1–6             1–6     1–6       1–4       1–4
             Number of patterns for high coverage SAF only             6572            7003    8744      9524     10456
             Total # of bits scanned in (same as scan out) Gb            4               6      11        14        19
             Maximum power consumption at test (W)                     200             200     300       300       300
             Maximum power consumption at test (W) - Server            300             300     300       300       300
             Number of logic gates (M)                                  34              43      46        58        73
             Consumer
             Consumer total cores                                       32           44         58        79       101
             Consumer Unique cores                                       4            6          7        10        13
             Percentage of Memory transistors                          83%          84%        85%       85%       86%
             Percentage of random logic transistors                     2%           2%         1%        1%        1%
             Percentage of core transistors                            15%          14%        14%       14%       13%
             Transistors per Flip Flop                                  26           26         26        26        26
             Supplies per DUT                                          1–6          1–6        1–6       1–4       1–4
             Number of patterns for high coverage SAF only            10,795       13,760     16,875    22,800    27,055
             Total # of bits scanned in (same as scan out) Gb            2            3          3         5         8
             Number of logic gates (M)                                  11           14         17        23        27

                         Manufacturable solutions exist, and are being optimized
                                           Manufacturable solutions are known
                                                  Interim solutions are known      
                                      Manufacturable solutions are NOT known
ong-term Years
                 2012      2013      2014      2015      2016      2017      2018      2019      2020      2021

                 1,226    1,545     1,946     2,452     3,090     3,893     4,905     6,181     7,788     9,812
                  926     1,225     1,609     2,031     2,633     3,205     3,973     5,049     6,623     7,714
                  140      140       140       140       140       140       140       140       140       140

                  64        64        64        64        64        64        64        64        64        64
               3.2          3.2       3.2       3.2       3.2       3.2       3.2       3.2       3.2       3.2
                75          113       113       113       169       169       169       253       253       253
               800         1200      1200      1200      1200      1200      1200      1200      1200      1200
                5            5         5         5         5         5         5         5         5         5
             0.7–0.9      0.6–0.9   0.6–0.9   0.6–0.8   0.5–0.8   0.5–0.7   0.5–0.7   0.4–0.7   0.4–0.6   0.4–0.6

                    7        8         9        10        11        12        14        16        17        20
                    2        2         4         4         4         4         4         6         6         6
                  70%      70%       75%       75%       75%       75%       75%       80%       80%       80%
                   5%       5%        5%        5%        5%        5%        5%        5%        5%        5%
                  25%      25%       20%       20%       20%       20%       20%       15%       15%       15%
                   26       26        26        26        26        26        26        26        26        26
                  1–3      1–3       1–3       1–3       1–3       1–3       1–3       1–3       1–3       1–3
                 11571    12911     17828     20193     23025     26426     30524     37458     43706     51278
                   24       32        69        92       123       167       228       353       490       685
                  300      300       300       300       300       300       300       300       300       300
                  300      300       400       400       400       400       400       400       400       400
                   92      116       122       153       193       243       307       309       389       491

                  126      161       212       268       348        424       526       669       878      1023
                   16       20        27        34        44         53        66        84       110       128
                  86%      86%       86%       86%       86%       86%       87%       87%       87%       87%
                   0%       0%        0%        0%        0%        0%        0%        0%        0%        0%
                  14%      14%       14%       14%       14%       14%       13%       13%       13%       13%
                   26       26        26        26        26         26        26        26        26        26
                  1–3      1–3       1–3       1–3       1–3        1–3       1–3       1–3       1–3       1–3
                 32,410   42,875    56,315    71,085    92,155    112,175   129,123   164,093   215,248   250,705
                    7       13        22        36        60         89       118       191       328       445
                   32       43        56        71        92        112       129       164       215       251
 2022

12,364
10,816
 140

  64
  3.2
  380
 1200
   5
0.4–0.6

  22
   6
 80%
  5%
 15%
  26
 1–3
60479
 965
 300
 400
 618

 1435
  179
 87%
  0%
 13%
   26
  1–3
351,520
  875
  352
INDEX LINK   Table TST5                Vector Multipliers
                                           Vector           Multiplier
                   Fault Type               Min               Max
                BF (Bridging Fault)         1.3               1.3
               TF (Transition Fault)         3                  5
                 SD (Small Delay)            2                 40
INDEX LINK   Table TST6                                   Memory Test Requirements—Near and Long-term Years
             Year of Production                               2007            2008    2009      2010         2011         2012
             DRAM Characteristics
             Capacity (Gbits)
              R&D                                               8              8       16        16           16           32
              Mass production                                   2              2        4         4            4            8
             Mass production I/O data rate (Gb/s)              1.1            1.3      1.3       1.6          1.6          2.1
             Performance I/O data rate (Gb/s)                  1.9            2.4      2.4       2.9          2.9          3.8
             Mass production I/O width                         16             16       16        16           16           16
             Mass Production CLK rate (GHz)                    0.5            0.7      0.7       0.8          0.8          1.1
             NAND Characteristics
             Capacity (Gbits)
               R&D                                              64           64        128       128          128          256
               Mass production                                  16           16         32        32           32           64
             Maximum I/O data rate (Mb/s)                      0.05         0.05       0.05     0.066        0.066         0.1
             Data width (bits)                                  16           16         16        16           16           16
             Power supply voltage range                      1.5–5.5      1.5–3.5    1.5–3.5   1.5–3.5      1.5–3.5      1.5–3.5
             Power supplies per device                          2            2          2         2            2            2
             Maximum current (MA)                               35           35         35        35           35           35
             Tester channels per device                         24           24         24        24           24           24
             NOR Characteristics
             Capacity (Gbits)
               R&D                                              4            4          8         8            8            16
               Mass production                                  1            1          2         2             2           4
             Maximum I/O data rate (Mb/s)                      0.2          0.2       0.266     0.266        0.266        0.333
             Data width (bits)                                  16           16         16        16           16           16
             Power supply voltage range                      1.0–5.5      1.0–5.5    0.9–3.5   0.9–3.5      0.9–3.5      0.9–3.5
             Power supplies per device                          2            2          2         2             2           2
             Maximum current (MA)                              150          150        150       150          150          150
             Tester channels per test site                      72           72         72        72           72           72
             Embedded DRAM
             Capacity (Mbits)                                  256            512     512       512          1024         1024
             DFT                                                                                          BIST/BISR
             Embedded Flash
             Capacity (Mbits)                                  64             128     128       128           256         256
             DFT                                                                                         BIST/BIST/DAT
             Embedded SRAM
             Capacity (Mbits)                                  0.5             1       1         1            2            2
             DFT                                                                                          BIST/BISR

                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                          Interim solutions are known     
                              Manufacturable solutions are NOT known
              TableMemory Test Requirements—Long-term Years
                   TST6b
             Year of Production        2016    2017    2018    2019    2020    2021
DRAM Characteristics
Capacity (Gbits)
 R&D                                    64      64     128     128     128     256
 Mass production                        16      16      32      32      32      64
Mass production I/O data rate (Gb/s)    3.2     4.3    5.3     5.4     6.4     6.4
Performance I/O data rate (Gb/s)        5.8     7.7    9.6     9.6     11.5    11.5
Mass production I/O width               16      16      16      16      16      16
Mass Production CLK rate (GHz)          1.6     2.1    2.7     2.7     3.2     3.2
NAND Characteristics
Capacity (Gbits)
  R&D                                   512     512    1024    1024    1024    2048
  Mass production                       128     128     256     256     256     512
Maximum I/O data rate (Mb/s)           0.133   0.133   0.133   0.133   0.266   0.266
Data width (bits)                        16      16      16      16      16      16
Power supply voltage range      1.0–3.5   1.0–3.5   1.0–3.5      1.0–3.5      1.0–3.5   1.0–3.5
Power supplies per device          2         2         2            2            2         2
Maximum current (MA)               50        50        50           50           50        50
Tester channels per device         24        24        24           24           24        24
NOR Characteristics
Capacity (Gbits)
  R&D                              32       32         64           64           64       128
  Mass production                  8          8        16           16           16        32
Maximum I/O data rate (Mb/s)      0.4       0.4      0.533        0.533        0.533     0.533
Data width (bits)                  16        16        16           16           16        16
Power supply voltage range      0.9–3.5   0.9–3.5   0.9–3.5      0.9–3.5      0.9–3.5   0.9–3.5
Power supplies per device          2        2          2           2             2         2
Maximum current (MA)              150      150        150         150           150       150
Tester channels per test site      72       72         72          72            72
Embedded DRAM
Capacity (Mbits)                 2048      4096      4096         4096         4096      4096
DFT                                                            BIST/BISR
Embedded Flash
Capacity (Mbits)                 512       1023      1024         1024         1024      2048
DFT                                                           BIST/BIST/DAT
Embedded SRAM
Capacity (Mbits)                  4         8         8            8            16        16
DFT                                                            BIST/BISR
       2013      2014      2015      2016      2017      2018         2019         2020      2021      2022



        32        32        64        64        64       128          128          128       256       256
         8         8        16        16        16        32           32           32        64        64
        2.7       2.7       3.2       3.2       4.3      5.3          5.4          6.4       6.4       8.5
        4.8       4.8       5.8       5.8       7.7      9.6          9.6          11.5      11.5      15.4
        16        16        16        16        16        16           16           16        16        16
        1.3       1.3       1.6       1.6       2.1      2.7          2.7          3.2       3.2       4.3



        256       256       512       512       512      1024         1024         1024      2048      2048
         64        64       128       128       128       256          256          256       512       512
        0.1       0.1       0.1      0.133     0.133     0.133        0.133        0.266     0.266     0.266
         16        16        16        16        16        16           16           16        16        16
      1.5–3.5   1.0–3.5   1.0–3.5   1.0–3.5   1.0–3.5   1.0–3.5      1.0–3.5      1.0–3.5   1.0–3.5   1.0–3.5
         2         2         2         2         2         2            2            2         2         2
         35        35        50        50        50        50           50           50        50        50
         24        24        24        24        24        24           24           24        24        24



         16        16        32        32        32        64           64           64       128       128
         4          4        8         8          8        16           16           16        32        32
       0.333     0.333      0.4       0.4       0.4      0.533        0.533        0.533     0.533     0.533
         16        16        16        16        16        16           16           16        16        16
      0.9–3.5   0.9–3.5   0.9–3.5   0.9–3.5   0.9–3.5   0.9–3.5      0.9–3.5      0.9–3.5   0.9–3.5   0.9–3.5
         2          2        2         2          2        2             2           2         2         2
        150       150       150       150       150       150          150          150       150       150
         72        72        72        72        72        72           72           72

       1024      2048      2048      2048      4096      4096         4096         4096      4096      8192
R                                                                  BIST/BISR

       256       512       512       512       1023      1024          1024        1024      2048      2048
DAT                                                               BIST/BIST/DAT

        2         4         4         4         8         8            8            16        16        16
R                                                                  BIST/BISR
2022



256
 64
8.5
15.4
 16
4.3



2048
 512
0.266
  16
1.0–3.5
   2
   50
   24



  128
   32
 0.533
   16
0.9–3.5
   2
  150



 8192



 2048



  16
INDEX LINK   Table TST7                         Mixed-signal Test Requirements—Near-term Years
             Year of Production                     2007          2008            2009     2010        2011       2012
             Low Frequency Waveform
             BW (MHz)                                50            75         75         75           100        100
             Sample rate (MS/s)                                   Moving from Nyquist sample rates to over/under sampling sources/digitizers
             Resolution (bits)                                     DSP computation to 24 bits, effective number of bits limited by noise floor
             Noise floor (dB/RT Hz)                 -155          -160       -160       -160          -165       -165
             Very High Frequency Waveform
             Source
             Level V (pk–pk)                          4             4           <4          <4          <4          <4
             Accuracy (±)                          0.50%         0.50%        0.50%       0.50%       0.50%       0.50%
             BW (GHz)                                1.6           1.9         2.25         2.7         2.7          3
             Sample rate (GS/s)                      6.4           7.6           9         10.8         11          12
             Resolution (bits) AWG/Sine†           10-Aug        10-Aug       10-Aug      10-Aug      10-Aug      12-Oct
             Noise floor (dB/RT Hz)                 -140          -140         -140        -140        -140        -145
             Very High Frequency Waveform
             Digitizer
             Level V (pk–pk)                          4             4            <4         <4          <4          <4
             Accuracy (±)                          0.50%         0.50%         0.50%      0.50%       0.50%       0.50%
             BW (GHz) (under sampled)                9.2          10.8          10.8       12.5        12.5         15
             Sample rate (GS/s)                      0.4           0.4           0.4        0.4         0.4         0.6
             Min resolution (bits)                   12            12            12         12          12          14
             Noise floor (dB/RT Hz)                 -145          -145          -145       -145        -145        -150
             Time Measurement
             Jitter measurement (ps RMS)                                      Will be driven by high-speed serial communication ports
             Frequency measurement (MHz)                                       Will be driven by high-performance ASIC clock rates
             Single shot time capability (ps)                                 Will be driven by high-speed serial communication ports

                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                              Interim solutions are known     
                                  Manufacturable solutions are NOT known
                   2013         2014    2015     2016       2017         2018        2019        2020        2021        2022

                     100         100     100     100        100         100          100        100           100         100
 /under sampling sources/digitizers              Moving from Nyquist sample rates to over/under sampling sources/digitizers
 mber of bits limited by noise floor              DSP computation to 24 bits, effective number of bits limited by noise floor
                    -165         -165    -165    -165       -165       -165          -165       -165         -165         -165


                    <4           <4       <4       <4         <4          <4          <4          <4          <4          <4
                  0.50%        0.50%    0.50%    0.50%      0.50%       0.50%       0.50%       0.50%       0.50%       0.50%
                     3          3.75     3.75     3.75       3.75        3.75        3.75        3.75        3.75        3.75
                    12           15       15       15         15          15          15          15          15          15
                  12-Oct       12-Oct   12-Oct   12-Oct     12-Oct      12-Oct      12-Oct      12-Oct      13-Oct      14-Oct
                   -145         -145     -145     -145       -145        -145        -145        -145        -145        -145


                     <4          <4       <4       <4         <4          <4          <4          <4          <4          <4
                   0.50%       0.50%    0.50%    0.50%      0.50%       0.50%       0.50%       0.50%       0.50%       0.50%
                     15          15       15       15         15          15          15          15          15          15
                     0.6         0.6      0.6      0.6        0.6         0.6         0.6         0.6         0.6         0.6
                     14          14       14       14         14          14          14          14          14          14
                    -150        -150     -150     -150       -150        -150        -150        -150        -150        -150

rial communication ports                                   Will be driven by high-speed serial communication ports
mance ASIC clock rates                                      Will be driven by high-performance ASIC clock rates
rial communication ports                                   Will be driven by high-speed serial communication ports
INDEX LINK   Table TST8                        RF Test Requirements—Near and Long-term Years
             Year of Production                   2007          2008            2009   2010    2011    2012    2013
             Carrier Frequency (GHz) Leading
             Edge                                   18           18              22     22      60      77      77
             Carrier Frequency (GHz) High
             Volume                                 6             8              12     12      22      22      36
             Modulation RF BW (MHz)
             Leading Edge                          80            528            528     528     528     528     528
             Modulation RF BW (MHz) High
             Volume                                20            40              80    528     528      528     528
             Amplitude Accuracy (dB)              <0.8          <0.6            <0.5   <0.5    <0.5    <0.25   <0.25
             ACLR (dB)                             65            65              70     72      72       72      75
             Number of RF Ports per Device         <9           <12             <16    <20     <24      <20     <18
             Phase Noise (dBc/Hz at 100K
             offset)                              -125          -130         -135       -140    -142    -145    -148
             Error Vector Magnitude 3G/4G         1-2%          1-2%        0.50%      0.50%   0.50%   0.50%   0.50%
             OIP3 (dBm)                            30            30           30         30      30      30      30
             IIP3 (dBm)                            40            50           60         60      60      60      60

                  Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                           Interim solutions are known      
                               Manufacturable solutions are NOT known
2014    2015    2016    2017    2018    2019     2020     2021     2022

 95      95      95      95      95      95       95       95       95

 36      36      36      36      36       36       36       36       36

 528     528     528     528     528    1000     1000     1000     1000

 528     528     528     528     528     528      528      1000     1000
<0.25   <0.25   <0.25   <0.25   <0.25   <0.125   <0.125   <0.125   <0.125
  75      80      80      80      85      85       85       85       85
 <16     <16     <16     <16     <16     <16      <16      <16      <16

 -150    -150    -150    -152    -152    -152     -152     -152     -152
0.50%   0.50%   0.50%   0.50%   0.50%   0.50%    0.50%    0.50%    0.50%
  30      30      30      30      30      30       30       30       30
  60      60      60      60      60      60       60       60       60
INDEX LINK   Table TST9                                     Burn-in Requirements—Near and Long-term Years
             Year of Production                                2007          2008         2009        2010      2011      2012
             Clock input frequency (MHz)                        400           400          400         400       400       400
             Off-chip data frequency (MHz)                       75            75           75          75        75        75
             Power dissipation (W per DUT)                      600           600          600         600       600       600
             Power Supply Voltage Range (V)
              High-performance ASIC / microprocessor /
             graphics processor                              0.5–2.5       0.5–2.5       0.5–2.5     0.5–2.5   0.5-2.5   0.5–2.5
               Low-end microcontroller                       0.7–10.0      0.7–10.0      0.7–10.0     0.5–10    0.5–10    0.5–10
               Mixed-signal                                  0.5–500       0.5–500       0.5–500     0.5–500   0.5–500   0.5–500
             Maximum Number of Signal I/O
               High-performance ASIC                            384           384          384        384       384       384
               High-performance microprocessor / graphics
             processor / mixed-signal                           128           128          128        128       128       128
               Commodity memory                                  72            72           72         72        72        72
             Maximum Current (A)
               High-performance microprocessor                  450           450          450        450       450       450
               High-performance graphics processor              100           150          200        200       200       200
               Mixed-signal                                      20            20           20         30        30        30
             Burn-in Socket
               Pin count                                       3000          3000         3000        3000      3000      3000
               Pitch (mm)                                       0.3           0.3          0.3         0.2       0.2       0.2
               Power consumption (A/Pin)                         3             4            4           5         5         5
             Wafer Level Burn-In
               Maximum burn-in temperature (ºC)                175±3        175±3         175±3      175±3     175±3     175±3
             Pad Layout — Linear
               Minimum pad pitch (μm)                            65            65           65         65        65        65
               Minimum pad size (μm)                             50            50           50         50        50        50
               Maximum number of probes                         70K           70K          70K        70K       70K       70K
             Pad Layout — Periphery, Area Array
               Minimum pad pitch (μm) *1                        100           80           80          80        80        80
               Minimum pad size (μm)                             40           35           35          35        35        30
               Maximum number of probes                        150K          150K         150K        150K      150K      150K
             Power consumption (W/DUT — Low-end
             microcontroller, DFT/BIST )                         10           10           10          20        20        20
             Vector memory depth (M vectors — DFT/BIST
             )                                                   32           64           64          64        64        64

                               Manufacturable solutions exist, and are being optimized
                                                 Manufacturable solutions are known
                                                        Interim solutions are known              
                                            Manufacturable solutions are NOT known
 2013      2014      2015       2016       2017       2018       2019       2020       2021       2022
  400       400       400        400        400        400        400        400        400        400
   75        75        75         75         75         75         75         75         75         75
  600       600       600        600        600        600        600        600        600        600


0.5–2.5   0.5–2.5    0.5–2.5    0.5–2.5    0.5–2.5    0.4–2.5    0.4–2.5    0.4–2.5    0.4–2.5    0.4–2.5
 0.5–10    0.5–10    0.5–10     0.5–10     0.5–10     0.5–10     0.5–10     0.5–10     0.5–10     0.5–10
0.5–500   0.5–500   0.5–1000   0.5–1000   0.5–1000   0.5–1000   0.5–1000   0.5–1000   0.5–1000   0.5–1000

 384       384        384        384        384        384        384        384        384        384

 128       128        128        128        128        128        128        128        128        128
  72        72         72         72         72         72         72         72         72         72

 450       450        450        450        450        450        450        450        450        450
 200       200        200        200        200        200        200        200        200        200
  30        30         30         30         30         30         30         30         30         30

 3000      3000      3000       3000       3000       3000       3000       3000       3000       3000
  0.2       0.2       0.1        0.1        0.1       0.08       0.08       0.08       0.08       0.08
   5         5         5          6          6         6          6          6          6          6

175±3     175±3      175±3      175±3      175±3      175±3      175±3      175±3      175±3      175±3

  65        65        50         50         50         50         50         50         50         50
  50        50        40         40         40         40         40         40         40         40
 70K       70K       140K       140K       140K       140K       140K       140K       140K       140K

  80        80        60         60         60         60         60         60         60         60
  30        30        25         25         25         25         25         25         25         25
 150K      150K      300K       300K       300K       300K       300K       300K       300K       300K

  20        20         20         20         20         20         20         20         20         20

  64        64        128        128        128        256        256        256        256        256
INDEX LINK   Table TST10         Test Handler and Prober Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table TST11                                       Prober Requirements—Near and Long-term Years
             Year of Production                                   2007         2008         2009       2010        2011        2012
             Wafer diameter (mm)                                   300          300          300        300         300         300
             Wafer thickness (µm)                                80–775       80–775       80–775     80–775      80–775      80–775
             Maximum I/O pads                                     3000         4000         4000       5300        5300        5300
             Chuck X and Y positioning accuracy ( μm)               2            2            1           1           1           1
             Chuck Z positioning accuracy ( μm)                     1            1           0.5         0.5         0.5         0.5
             Probe-to-pad alignment (µm)                           4.5          4.5          4.5         3.5         3.5         3.5
             Maximum chuck force (kg)                              100          100          100        100         100         100
             Set point range (ºC)                              -30 to +85   -30 to +85   -30 to +85 -45 to +125 -45 to +125 -45 to +125
             Total power (Watts)                                   130          130          250        250         250         250
             Power density (Watt/cm2)                               60           60          120        120         120         120

     Manufacturable solutions exist, and are being optimized
                       Manufacturable solutions are known
                              Interim solutions are known      
                  Manufacturable solutions are NOT known
   2013        2014         2015       2016        2017         2018        2019        2020        2021        2022
    300         450          450        450         450          450         450         450         450         450
  80–775      50–1000     50–1000     50–1000     50–1000     50–1000     50–1000     50–1000     50–1000     50–1000
   5300         5300        5300        5300        5300        5300        5300        5300        5300        5300
      1           1           1           1           1           1           1           1           1           1
     0.5         0.5         0.5         0.5         0.5         0.5         0.5         0.5         0.5         0.5
     3.5         3.5         3.5         3.5         3.5         3.5         3.5         3.5         3.5         3.5
    100         100          100        100         100          100         100         100         100         100
-45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125 -45 to +125
    250         250          250        250         250          250         250         250         250         250
    120         120          120        120         120          120         120         120         120         120
INDEX LINK   Table TST12                                        Handler Requirements—Near and Long-term Years
             Year of Production                                     2007       2008         2009         2010         2011         2012
             High, Medium and Low Power
             Temperature set point range (ºC)                   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175
             High Power — >10W per DUT
             Temperature accuracy at DUT (ºC)                      ±2           ±2           ±2           ±2           ±2           ±2
             Number of pins/device                                 750          750          800         800          850          850
             Parallel testing:                                     1-2          1-2          1-2          1-2          1-2          1-2
             Throughput (devices per hour)                       1.5–2K       1.5–2K       1.5–2K       2–3.5K       2–3.5K       2–3.5K
             Index time (S)                                        0.3          0.3         0.25         0.25         0.25         0.25
             Sorting Categories                                    3–6          3–6          3–6         3–6          3–6          3–6
             Allowable device temperature rise (ºC)                 20           20           20          20           20           20
             Maximum socket load per unit (kg)                      24           27           30          30           35           35
             Asynchronous capability                               Yes          Yes          Yes         Yes          Yes          Yes
             Pin/land pitch (mm)                                   1.1          1.1           1            1           0.8          0.6
             Medium Power — 0.5 to 10W per DUT
             Temperature accuracy at DUT (ºC)                        ±2         ±2           ±2           ±2           ±2           ±2
             Number of pins/device                                   800        800          850         850          850          850
             Parallel testing:                                      8-16       8-16         8-16         8-16         8-16         8-16
             Throughput (devices per hour)                          4–6K       4–6K         4–6K        6–10K        6–10K        6–10K
             Index time (S)                                          0.3        0.3          0.3          0.3         0.25         0.25
             Sorting Categories                                      3–6        3–6          3–6         3–6          3–6          3–6
             Allowable device temperature rise (ºC)                   5          5            5            5            5            5
             Maximum socket load per unit (kg)                        50         50           35          60           35           60
             Asynchronous capability                                 Yes        Yes          Yes         Yes          Yes          Yes
             Pin/land pitch (mm)                                     0.3        0.3          0.3          0.3          0.3          0.3
             Low Power — < 0.5W per DUT
             Temperature accuracy at DUT (ºC)                       ±2           ±2          ±1.5         ±1.5         ±1.5         ±1.5
             Number of pins/device                                6–250        6–250        6–250        6–250        6–250        6–250
             Parallel testing:                                   128-512     128-1024     128-1024     128-1024     128-1024     128-1024
             Throughput (devices per hour)                        8–10K       12–20K       12–20K       12–20K       12–20K       12–20K
             Index time (S)                                        2–5          2–5          2–4          2–4          2–4          2–4
             Sorting Categories                                    5–9          5–9          5–9          5–9          5–9          5–9
             Min. Pkg. Size(mm2)                                   4×6          3×5          3×5          3×5          3×5          3×5
             Pin pitch (mm)                                      0.4–1.0     0.25–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0
             Ball edge to package edge clearance (mm)              0.25         0.25         0.25         0.25         0.25          0
             Minimum package thickness (mm)                      0.4–1.8      0.3–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8

      Manufacturable solutions exist, and are being optimized
                        Manufacturable solutions are known
                               Interim solutions are known      
                   Manufacturable solutions are NOT known
  2013         2014         2015         2016         2017         2018         2019         2020         2021         2022

-55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175   -55 to 175

   ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2
  850          850          850          850          900          900          900          1000         1000         1000
   1-2          1-2          1-2          1-2          1-2          1-2          1-2          1-2          1-2          1-2
 2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K       2–3.5K
  0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25
  3–6          3–6          3–6          3–6          3–6          3–6          3–6          3–6          3–6          3–6
   20           20           20           20           20           20           20           20           20           20
   35           35           35           35           35           35           35           35           35           35
  Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes
   0.6          0.6          0.6          0.6          0.4          0.4          0.4          0.4          0.4          0.4

   ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2           ±2
  850          850          900          900          900          1000         1000         1000         1000         1000
  8-16         8-16         8-16         8-16         8-16         8-16         8-16         8-16         8-16         8-16
 6–10K        6–10K        6–10K        6–10K        6–10K        6–10K        6–10K        6–10K        6–10K        6–10K
  0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25         0.25
  3–6          3–6          3–6          3–6          3–6           3–6          3–6          3–6          3–6          3–6
    5            5            5            5            5            5            5            5            5            5
   60           60           65           65           65           75           75           75           75           75
  Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes          Yes
   0.2          0.2          0.2          0.2          0.2          0.2          0.2          0.2          0.2          0.2

   ±1.5         ±1.5         ±1.5         ±1.5         ±1.5         ±1.5         ±1.5         ±1.5         ±1.5         ±1.5
  6–250        6–250        6–250        6–250        6–250        6–250        6–250        6–250        6–250        6–250
128-1024     128-1024     128-2048     128-2048     128-2048     128-2048     128-2048     128-2048     128-2048     128-2048
 12–20K       12–20K       12–20K       12–20K       12–20K       12–20K       12–20K       12–20K       12–20K       12–20K
   2–4          2–4          2–4          2–4          2–4          2–4          2–4          2–4          2–4          2–4
   5–9          5–9          5–9          5–9          5–9          5–9          5–9          5–9          5–9          5–9
   3×5          2×3          2×3          2×3          2×3          2×3          2×3          2×3          2×3          2×3
 0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0      0.2–1.0
    0            0            0            0            0            0            0            0            0            0
 0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8      0.2–1.8
INDEX LINK   Table TST13        Probing Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table TST14                                          Wafer Probe Technology Requirements—Near and Long-term Years
             Year of Production                                              2007                       2008                       2009
             MPU and ASIC Products
             Wirebond—inline pad pitch                                        40                         35                         35
             Bump—array pad pitch                                             130                        130                        120
             I/O Pad Size (µm)                                         X               Y        X                 Y        X
             Wirebond                                                  30             55        30               55        30
             Bump                                                      65             65        65               65        60
             Scrub (% of pad)                                         AREA           DEPTH    AREA              DEPTH    AREA
             Wirebond                                                  25             50        25               50        25
             Bump                                                      30             30        30               30        30
                                    2
             Size of Probed Area (mm )                                       2050                       2400                       2400
             Number of Probe Points /Touchdown—Asics                         5000                       6000                       7500
             Number of Probe Points / Touchdown—MPU                          20000                      20000                      20000

             Maximum Current (mA)                                 Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip

             ASIC                                                     400            <.001     500              <.001     500
             MPU                                                      1000           <.001     1000             <.001     1200
             Maximum Resistance (Ohm)                              Contact           Series   Contact           Series   Contact
                                                                      <0.5            <3       <0.5              <3       <0.5
             Memory Products
             Wirebond—inline pad pitch                                        75                         75                         70
             I/O Pad Size (µm)                                         X               Y        X                 Y        X
             Wirebond                                                  65             80        65               80        60
             Scrub (% of pad)                                         AREA           DEPTH    AREA              DEPTH    AREA
             Wirebond                                                  25             50        25               50        25
                                    2
             Size of Probed Area (mm )                                  100% of wafer             100% of wafer              100% of wafer
             Number of Probe Points / Touchdown—Memory                       20000                      20000                      25000

             Maximum Current (mA)                                 Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip

                                                                      200            <.001     200              <.001     200
             Maximum Resistance (Ohm)                              Contact           Series   Contact           Series   Contact
                                                                      <0.5            <3       <0.5              <3       <0.5
             RF and Mixed Signal Products
             Wirebond—inline pad pitch                                        40                         35                         35
             Bump—array pad pitch                                             130                        130                        120
             I/O Pad Size (µm)                                         X               Y        X                 Y        X
             Wirebond                                                  30             55        30               55        30
             Bump                                                      65             65        65               65        60
             Scrub (% of pad)                                         AREA           DEPTH    AREA              DEPTH    AREA
             Wirebond                                                  25             50        25               50        25
             Bump                                                      30             30        30               30        30
                                    2
             Size of Probed Area (mm )                                       1600                       1600                       1600
             Number of Probe Points /Touchdown                               680                        680                        680
             Maximum Resistance (Ohm)                              Contact           Series   Contact           Series   Contact
                                                                      <0.5            <3       <0.5              <3       <0.4


        Manufacturable solutions exist, and are being optimized
                          Manufacturable solutions are known
                                  Interim solutions are known     
                      Manufacturable solutions are NOT known
s—Near and Long-term Years
          2009                       2010                       2011                       2012                       2013                       2014

            35                        30                         30                         25                         25                         25
           120                        120                        120                        110                        110                        100
                    Y        X                 Y        X                 Y        X                 Y        X                 Y        X
                   55        25               45        25               45        20               35        20               35        20
                   60        60               60        60               60        55               55        55               55        50
                  DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    Offline
                   50        20               40        20               40        20               40        20               40        20
                   30        30               30        30               30        30               30        30               30        30

           2400                      2400                       2400                       2400                       2400                       2400
           7500                      7500                       7500                       9000                       9000                       9000
          20000                      20000                      20000                      30000                      30000                      30000

             DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip

                  <.001     500              <.001     500              <.001     1000             <.001     1000             <.001     1000
                  <.001     1200             <.001     1500             <.001     1500             <.001     1500             <.001     1500
                  Series   Contact           Series   Contact           Series   Contact           Series   Contact           Series   Contact
                   <3       <0.5              <3       <0.5              <3       <0.5              <3       <0.5              <3       <0.5


            70                        70                         65                         65                         60                         60
                    Y        X                 Y        X                 Y        X                 Y        X                 Y        X
                   80        60               80        55               80        55               80        55               80        55
                  DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    AREA
                   50        25               50        25               50        25               50        25               50        25

       100% of wafer           100% of wafer              100% of wafer              100% of wafer              100% of wafer              100% of wafer
          25000                      25000                      30000                      30000                      30000                      30000

             DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip

                  <.001     200              <.001     250              <.001     250              <.001     250              <.001     250
                  Series   Contact           Series   Contact           Series   Contact           Series   Contact           Series   Contact
                   <3       <0.5              <3       <0.5              <3       <0.5              <3       <0.5              <3       <0.5


            35                        30                         30                         25                         25                         25
           120                        120                        120                        110                        110                        100
                    Y        X                 Y        X                 Y        X                 Y        X                 Y        X
                   55        25               45        25               45        20               35        20               35        20
                   60        60               60        60               60        55               55        55               55        50
                  DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    AREA              DEPTH    Offline
                   50        20               40        20               40        20               40        20               40        20
                   30        30               30        30               30        30               30        30               30        30

           1600                      1600                       1600                       1600                       1600                       1600
           680                       680                        680                         680                       680                        680
                  Series   Contact           Series   Contact           Series   Contact           Series   Contact           Series   Contact
                   <3       <0.4              <3       <0.4              <3       <0.4              <3       <0.4              <3       <0.4
   2014                       2015                       2016                      2017                      2018                    2019

     25                        25                         25                        25                        25                         25
    100                        100                        95                        95                        90                         90
             Y        X                 Y        X                Y        X                Y        X                Y         X
            35        15               25       15                25      15                25      15                25       15
            50        50               50       45                45      45                45      45                45       45
           DEPTH    AREA              DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH     AREA
            40        20               40       20                40      20                40      20                40       20
            30        30               30       30                30      30                30      30                30       30

    2400                      2400                       2400                      2400                      2400                      2400
    9000                      9000                     9000                      9000                      9000                       9000
   30000                      30000                   30000                     30000                     30000                      30000

      DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage                         Probe Tip

           <.001     1000             <.001     1000            <.001     1000            <.001     1000            <.001     1000
           <.001     1500             <.001     1500            <.001     1500            <.001     1500            <.001     1500
           Series   Contact           Series   Contact          Series   Contact          Series   Contact          Series   Contact
            <3       <0.5              <3       <0.5             <3       <0.5             <3       <0.5             <3       <0.5

     60                        55                         55                        50                        50                         50
             Y        X                 Y        X                Y        X                Y        X                Y         X
            80        50               80       50                80      50                80      65                80        65
           DEPTH    AREA              DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH     AREA
            50        25               50       25                50      25                50      25                50       25

100% of wafer           100% of wafer             100% of wafer             100% of wafer             100% of wafer             100% of wafer
   30000                      30000                   30000                     30000                     30000                      30000

      DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage                         Probe Tip

           <.001     250              <.001      250            <.001      250            <.001      250            <.001      250
           Series   Contact           Series   Contact          Series   Contact          Series   Contact          Series   Contact
            <3       <0.5              <3       <0.5             <3       <0.5             <3       <0.5             <3       <0.5

     25                        25                         25                        25                        25                         25
    100                        100                        95                        95                        90                         90
             Y        X                 Y        X                Y        X                Y        X                Y         X
            35        15               25       15                25      15                25      15                25       15
            50        50               50       45                45      45                45      45                45       45
           DEPTH    AREA              DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH     AREA
            40        20               40       20                40      20                40      20                40       20
            30        30               30       30                30      30                30      30                30       30

    1600                      1600                       1600                      1600                      1600                      1600
    680                       680                        680                       680                       680                       680
           Series   Contact           Series   Contact          Series   Contact          Series   Contact          Series   Contact
            <3       <0.4              <3       <0.4             <3       <0.4             <3       <0.4             <3       <0.4
    2019                   2020                      2021                      2022

     25                       25                        25                        25
     90                       85                        85                        85
             Y        X                Y        X                Y        X                Y
             25      15                25      15                25      15                25
             45      40                40      40                40      40                40
           DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH
             40      20                40      20                40      20                40
             30      30                30      30                30      30                30

    2400                      2400                      2400                      2400
    9000                    9000                      9000                      9000
   30000                   30000                     30000                     30000

      DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage

           <.001     1000            <.001     1000            <.001     1000            <.001
           <.001     1500            <.001     1500            <.001     1500            <.001
           Series   Contact          Series   Contact          Series   Contact          Series
            <3       <0.5             <3       <0.5             <3       <0.5             <3

     50                       50                        50                        50
            Y         X               Y         X               Y         X               Y
            80        65              80        65              80        65              80
           DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH
             50      25                50      25                50      25                50

100% of wafer         100% of wafer             100% of wafer             100% of wafer
   30000                   30000                     30000                     30000

      DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage Probe Tip DC Leakage

           <.001      250            <.001      250            <.001      250            <.001
           Series   Contact          Series   Contact          Series   Contact          Series
            <3       <0.5             <3       <0.5             <3       <0.5             <3

     25                       25                        25                        25
     90                       85                        85                        85
             Y        X                Y        X                Y        X                Y
             25      15                25      15                25      15                25
             45      40                40      40                40      40                40
           DEPTH    AREA             DEPTH    AREA             DEPTH    AREA             DEPTH
             40      20                40      20                40      20                40
             30      30                30      30                30      30                30

    1600                      1600                      1600                      1600
    680                       680                       680                       680
           Series   Contact          Series   Contact          Series   Contact          Series
            <3       <0.4             <3       <0.4             <3       <0.4             <3
INDEX LINK   Table TST15                                      Test Socket Technology Requirements—Near and Long-term Years
             Year of Production                                     2007       2008       2009       2010       2011       2012
             TSOP—Flash (NAND)—Contact blade [1]
             Commodity NAND Memory
             Lead Pitch (mm)                                      0.4        0.3        0.3        0.3        0.3       0.3
             Data rate (MT/s)                                     50         50         50         66         66        100
             Contact blade
             Inductance (nH)                                   15-Oct      10-May     10-May     10-May     10-May     10-May
             Contact Stroke (mm)                               0.3-0.5     0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3
             Contact force (N)                                 0.2-0.4     0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3
             Contact resistance (m Ohm)                          30          30         30         30         30         30
             Slit width (mm)                                    0.22        0.17       0.17       0.17       0.17       0.17
             BGA—DRAM—Spring Probe [2]
             Commodity DRAM (Mass production)
             Lead Pitch (mm)                                      0.65      0.65       0.65        0.5        0.5        0.5
             DRAM RM GT/S                                         1.1       1.3        1.3         1.6        1.6        2.1
             Spring Probe
             Inductance (nH)                                      1.5       1.5        1.5         1          1          1
             Contact Stroke (mm)                                  0.3       0.3        0.3        0.3        0.3        0.3
             Contact force (N)                                    <0.4      <0.4       <0.4       <0.3       <0.3       <0.3
             Contact resistance (m Ohm)                           100       100        100        100        100        100
             BGA—SoC—Spring Probe (50 Ohm) [3]
             Logic (High volume microprocessor)
             Lead Pitch (mm)                                      0.8        0.8        0.8       0.65       0.65       0.65
             I/O data (GT/s)                                       6          6         12         12         12         12
             Spring Probe (50 Ohm)
             Impedance (Ohm)                                       50        50         50         50         50         50
             Contact Stroke (mm)                                  0.3       0.3        0.3        0.3        0.3        0.3
             Contact force (N)                                    <0.4      <0.4       <0.4       <0.3       <0.3       <0.3
             Contact resistance (m Ohm)                           100        70         70         50         50         50
             BGA—SoC—Conductive Rubber [4] [5]
             Logic (High volume microprocessor)
             Lead Pitch (mm)                                      0.8        0.8        0.8       0.65       0.65       0.65
             I/O data (GT/s)                                       6          6         12         12         12         12
             Spring Probe (50 Ohm)
             Inductance (nH)                                      0.15      0.15       0.15       0.15       0.15       0.15
             Contact Stroke (mm)                                  0.15      0.15       0.15       0.15       0.15       0.15
             Contact force (N)                                    0.2       0.2        0.2        0.15       0.15       0.5
             Contact resistance (m Ohm)                            50        50         50         50         50         50
             Thickness (mm)                                       0.5       0.5        0.5        0.5        0.5        0.5


    Manufacturable solutions exist, and are being optimized
                      Manufacturable solutions are known
                             Interim solutions are known      
                 Manufacturable solutions are NOT known



                            Test TST15b
                           Table Socket Technology Requirements—Long-term Years
             Year of Production                                     2016       2017       2018       2019       2020       2021
             TSOP—Flash (NAND)—Contact blade [1]
             Commodity NAND Memory
             Lead Pitch (mm)                                      0.3       0.3        0.3        0.3        0.3        0.3
             Data rate (MT/s)                                     133       133        133        133        266        266
             Contact blade
Inductance (nH)                      10-May    10-May    10-May    10-May    10-May    10-May
Contact Stroke (mm)                  0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3
Contact force (N)                    0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3   0.2-0.3
Contact resistance (m Ohm)             30        30        30        30        30        30
Slit width (mm)                       0.17      0.17      0.17      0.17      0.17      0.17
BGA—DRAM—Spring Probe [2]
Commodity DRAM (Mass production)
Lead Pitch (mm)                        0.5       0.5       0.5       0.5       0.5       0.5
DRAM RM GT/S                           3.2       4.3       5.3       5.4       6.4       6.4
Spring Probe
Inductance (nH)                       0.3       0.3       0.2       0.2       0.15      0.15
Contact Stroke (mm)                   0.2       0.2       0.2       0.2       0.2       0.2
Contact force (N)                     <0.2      <0.2      <0.2      <0.2      <0.2      <0.2
Contact resistance (m Ohm)            100       100       100       100       100       100
BGA—SoC—Spring Probe (50 Ohm) [3]
Logic (High volume microprocessor)
Lead Pitch (mm)                        0.5       0.5       0.5       0.5       0.5       0.5
I/O data (GT/s)                        20        20        20        40        40        40
Spring Probe (50 Ohm)
Impedance (Ohm)                        50        50        50        50        50        50
Contact Stroke (mm)                   0.3       0.3       0.3       0.3       0.3       0.3
Contact force (N)                     <0.2      <0.2      <0.2      <0.2      <0.2      <0.2
Contact resistance (m Ohm)             50        50        50        50        50        50
BGA—SoC—Conductive Rubber [4] [5]
Logic (High volume microprocessor)
Lead Pitch (mm)                        0.5       0.5       0.5       0.5       0.5       0.5
I/O data (GT/s)                        20        20        20        40        40        40
Spring Probe (50 Ohm)
Inductance (nH)                       0.15      0.15      0.15      <0.1      <0.1      <0.1
Contact Stroke (mm)                   0.15      0.15      0.15      0.15      0.15      0.15
Contact force (N)                     0.1       0.1       0.1       0.1       0.1       0.1
Contact resistance (m Ohm)             50        50        50        50        50        50
Thickness (mm)                        0.5       0.5       0.5       0.5       0.5       0.5
Long-term Years
                  2013       2014       2015       2016       2017       2018       2019       2020       2021       2022



             0.3          0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3
             100          100        100        133        133        133        133        266        266        266

            10-May       10-May     10-May     10-May     10-May     10-May     10-May     10-May     10-May     10-May
            0.2-0.3      0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3
            0.2-0.3      0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3    0.2-0.3
              30           30         30         30         30         30         30         30         30         30
             0.17         0.17       0.17       0.17       0.17       0.17       0.17       0.17       0.17       0.17



              0.5          0.5        0.5        0.5        0.5        0.5        0.5        0.5        0.5        0.5
              2.7          2.7        3.2        3.2        4.3        5.3        5.4        6.4        6.4        8.5

             0.5          0.5        0.3        0.3        0.3        0.2        0.2        0.15       0.15       0.15
             0.2          0.2        0.2        0.2        0.2        0.2        0.2        0.2        0.2        0.2
             <0.2         <0.2       <0.2       <0.2       <0.2       <0.2       <0.2       <0.2       <0.2       <0.2
             100          100        100        100        100        100        100        100        100        100



             0.65         0.65       0.65        0.5        0.5        0.5        0.5        0.5        0.5        0.5
              15           15         15         20         20         20         40         40         40         40

              50           50         50         50         50         50         50         50         50         50
             0.3          0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3
             <0.3         <0.3       <0.3       <0.2       <0.2       <0.2       <0.2       <0.2       <0.2       <0.2
              50           50         50         50         50         50         50         50         50         50



             0.65         0.65       0.65        0.5        0.5        0.5        0.5        0.5        0.5        0.5
              15           15         15         20         20         20         40         40         40         40

             0.15         0.15       0.15       0.15       0.15       0.15       <0.1       <0.1       <0.1       <0.1
             0.15         0.15       0.15       0.15       0.15       0.15       0.15       0.15       0.15       0.15
             0.15         0.15       0.15       0.1        0.1        0.1        0.1        0.1        0.1        0.1
              50           50         50         50         50         50         50         50         50         50
             0.5          0.5        0.5        0.5        0.5        0.5        0.5        0.5        0.5        0.5




                  2022



             0.3
             266
10-May
0.2-0.3
0.2-0.3
  30
 0.17



  0.5
  8.5

 0.15
 0.2
 <0.2
 100



  0.5
  40

  50
 0.3
 <0.2
  50



  0.5
  40

 <0.1
 0.15
 0.1
  50
 0.5
INDEX LINK   Table RFAMS1                                                 RF and Analog Mixed-Signal CMOS Technology Requirements—Ne
             Year of Production                                               2007   2008     2009    2010     2011
             Performance RF/Analog [1]
              Supply voltage (V) [2]                                          1.2    1.1      1.1       1        1
                 Tox (nm) [2]                                                  2     1.9      1.6      1.5      1.4
                 Gate Length (nm) [2]                                          53     45       37      32       28
                 gm/gds at 5·Lmin-digital [3]                                  32     30       30      30       30
                 1/f-noise (µV²·µm²/Hz) [4]                                   160    140      100       90      80
                 s Vth matching (mV·µm) [5]                                    6      6        5        5       5
                 Ids (µA/µm) [6]                                               13     11       9        8       7
                 Peak Ft (GHz) [7]                                            170    200      240      280     320
                 Peak Fmax (GHz) [8]                                          200    240      290      340     390
                 NFmin (dB) [9]                                               0.25   0.22     0.2      <0.2    <0.2
             Precision Analog/RF Driver [1]
              Supply voltage (V)                                              2.5    2.5      2.5      1.8      1.8
                 Tox (nm) [10]                                                 5      5        5        3        3
                 Gate Length (nm) [10]                                        250    250      250      180      180
                 gm/gds at 10·Lmin-digital [11]                               220    220      220      160      160
                 1/f Noise (µV²·µm²/Hz) [4]                                   500    500      500      180      180
                       s Vth matching (mV·µm) [5]                              9      9        9        6        6
                 Peak Ft (GHz) [7]                                             40     40       40       50       50
                 Peak Fmax (GHz) [8]                                           70     70       70       90       90


                CMOS NFET [1 HP CMOS lag 2 yrs]
             V dd : Power Supply Voltage (V) [13]                             1.1    1.1      1.1       1        1
             EOT: Equivalent Oxide Thickness (Å) [13]                          12     11       11       9       7.5
             Lg: Physical Lgate for High Performance logic (nm) [13]           32     28       25       22       20
                  Peak Ft (GHz) [7]                                           280    320      360      400      440
                  Peak Fmax (GHz) [8]                                         340    390      440      510      560
                  NFmin (dB) at 24GHz[14]                                      2     1.8      1.6      1.4      1.3
                  NFmin (dB) at 60GHz[14]                                     5.1    4.5       4       3.6      3.3




                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                          Interim solutions are known     
                              Manufacturable solutions are NOT known
echnology Requirements—Near and Long-term years
              2012     2013     2014     2015      2016   2017   2018          2019       2020       2021

               1        1       0.95     0.85      0.8    0.8    0.8            0.8           0.75   0.75
              1.3      1.2      1.1      1.2       1.1    1.1     1              1            0.9    0.9
               25       22       20       18        16     14     13            12            11      10
               30       30       30       30        30     30     30            30            30      30
               70       60       50       60        50     50     40            40         30         30
               5        5        5        5         4      4      4             4          3          4
               6        6        5        4         4      3      3             3          2          2
              360      400      440      490       550    630    670           730        790        870
              440      510      560      630       710    820    880           960        1050       1160
              <0.2     <0.2     <0.2     <0.2      <0.2   <0.2   <0.2          <0.2       <0.2       <0.2

              1.8      1.8       1.8      1.8      1.8    1.8    1.8            1.5           1.5    1.5
               3        3         3        3        3      3      3             2.6           2.6    2.6
              180      180      180       180      180    180    180           130            130    130
              160      160      160       160      160    160    160           110            110    110
              180      180      180       180      180    180    180           135            135    135
               6        6        6         6        6      6      6             5              5      5
               50       50       50        50       50     50     50            70             70     70
               90       90       90        90       90     90     90           120            120    120
                                       switch to
                                       DG device                        switch to DG device

               1       0.95     0.9       0.9       0.9    0.8    0.8           0.7        0.7        0.7
              6.5      5.5       5         6         6      6     5.5           5.5        5.5         5
               18       16       14        13       11     10      9             8          7          6
              490      550      630       670      790    870    960           1080       1220       1420
              630      710      820       880      1050   1160   1300          1470       1690       1990
              1.2      1.1       1        0.9       0.8    0.7    0.6           0.6        0.5        0.4
               3        2.7      2.4      2.3       2     1.8    1.6            1.4           1.2     1
                                       switch to
                                       DG device                        switch to DG device
2022

0.7
0.8
 10
 30
 30
 5
 2
870
1160
<0.2

1.5
2.6
130
110
135
 5
 70
120




0.65
  5
 5.5
1550
2180
 0.4
0.9
INDEX LINK   Table RFAMS2                                                  RF and Analog Mixed-Signal Bipolar Technology Requirements—N
             Year of Production                                                2007   2008     2009     2010      2011
             General Analog NPN Parameters
               Emitter width (nm) (HS and HV NPN)                              130     120      100      100      100
               1/f-noise (µV²·µm²/Hz)                                           2       2        2       1.5      1.5
               s current matching (%·µm)                                        2       2        2        2        2
             High Speed (HS) NPN (Common to mmWave Table)
               Peak Ft (GHz) [Vcb=1V]                                          250     275      300      320      340
               Peak Fmax (GHz)                                                 280     305      330      350      370
               Nfmin (dB) at 60GHz                                              3      2.5      2.2      1.9      1.7
               BVceo (V)                                                       1.8     1.7      1.65     1.6      1.55
               Jc at Peak Ft (mA/µm2)                                           13     15       17       18        19
             High Voltage (HV) NPN
               Peak Ft (GHz) [Vbc=1V]                                           90     90       100      100      110
               Peak Fmax (GHz)                                                 170     180      190      200      210
               BVceo                                                           3.1     3.1      2.9      2.9      2.8
               NFmin (dB) at 5GHz                                              0.26   0.24      0.2      <0.2     <0.2
               Ic (µA/µm) at 50GHz Ft                                           28     22       16       15        14
             Power Amplifier (PA) NPN (Common to PA Table)
               Peak Ft (GHz) [Vbc=1V]                                           35     35       40       40        40
               Peak Fmax (GHz)                                                 60      60       80       80       80
               Bvceo (V)                                                       8.5     8.5      7.5      7.5      7.5
               BVcbo (V)                                                        18     18       16       16        16

                 Manufacturable solutions exist, and are being optimized
                                   Manufacturable solutions are known
                                          Interim solutions are known      
                              Manufacturable solutions are NOT known
Technology Requirements—Near and Long-term years
              2012     2013     2014     2015      2016   2017   2018   2019   2020   2021

               90       90       90       80        80     80     70     70     70     70
               1.5      1        1        1         1      1      1      1      1      1
                2       2        2        2         2      2      2      2      2      2

               360      380      395      415      430    445    455    470    480    490
               390     410       425      445      460    475    485    500    510    520
               1.5     1.4       1.3      1.2      1.1     1      1     0.9    0.9    0.9
               1.5     1.45      1.4      1.35     1.35   1.3    1.3    1.3    1.3    1.25
               21       22       23       24        25     26     27     28     29     29


               110      120      120      130      130    140    140    150    150    160
               220      230      240      250      260    270    280    290    300    310
               2.8      2.6      2.6      2.5      2.5    2.4    2.4    2.4    2.4    2.3
              <0.2     <0.2      <0.2     <0.2     <0.2   <0.2   <0.2   <0.2   <0.2   <0.2
               13       12       11       10        9      8      7      6      5      5


               40       40       40       40        40     40     40     40     40     40
               80       80       80       80       80     80     80     80     80     80
               7.5      7.5      7.5      7.5      7.5    7.5    7.5    7.5    7.5    7.5
               16       16       16       16        16     16     16     16     16     16
2022

 70
 1
 2

500
530
0.8
1.25
 30


160
320
2.3
<0.2
 5


 40
80
7.5
 16
INDEX LINK   Table RFAMS3                                          On-Chip Passives Technology Requirements—Near and Long-term year
             Year of Production                                        2007     2008      2009      2010      2011
             Analog
               MOS Capacitor
                 Density (fF/µm²) [1]                                    7        7         7        11        11
                 Leakage (A/cm²) [8]                                   <1e-9    <1e-9     <1e-9     <2e-6     <2e-6
             Resistor
               Thin Film BEOL
                 Parasitic capacitance (fF/µm²)                        0.03     0.03       0.05      0.05      0.05
                 Temp. linearity (ppm/ºC)                              <100     <100      40-80     40-80     40-80
                  1s Matching (% µm)                                    0.2      0.2       0.15      0.15      0.15
                 Sheet resistance, Rs (Ohm/sq)                          50       50         50        50        50
             P+ Polysilicon
                 Parasitic capacitance (fF/µm²)                       0.1        0.1       0.1       0.1       0.1
                 Temp. linearity (ppm/ºC)                            <100       <100      40-80     40-80     40-80
                  1s Matching (% µm)                                  1.7        1.7       1.7       1.7       1.7
                 Sheet resistance, Rs (Ohm/sq)                      200–300    200–300   200–300   200–300   200–300
             RF
               Metal-Insulator-Metal Capacitor
                                2
                 Density (fF/µm ) [2]                                    2        4         4         5         5
                 Voltage linearity (ppm/V²)                            <100     <100      <100      < 100     < 100
                 Leakage (A/cm²) [9]                                   <1e-8    <1e-8     <1e-8     <1e-8     <1e-8
                 s Matching (%·µm)                                      0.5      0.5       0.5       0.4       0.4
                 Q (5 GHz for 1pF)                                      >50      >50       >50       >50       >50
               MOM Capacitor
                 Density (fF/µm²)                                       3.7       5        5.3       6.2        7
                 Voltage linearity (ppm/V²)                            <100     <100      <100      <100      <100
                s Matching (% for 1pF)                                 <0.15    <0.15     <0.15     <0.15     <0.15
             Inductor
                 Q (5 GHz, 1nH) [3]                                     29       30        32        34        36
             MOS Varactor
                 Tuning Range [4]                                      >5.5     >5.5      >5.5      >5.5      >5.5
                 Q (5 GHz, 0 V)                                         35       35        40        40        45
             PA
               PA III-V Passives
                 Inductors Q (1GHz, 5nH) [5]                            15       25        25        25        25
                 Capacitor Q [6]                                       >100     >100      >100      >100      >100
                                            2
                RF capacitor density (fF/µm ) [7]                       1.2      1.2       1.2        2         2
               PA Silicon/SiGe Passives
                Inductors Q (1GHz, 5nH) [5]                             10       14        14        14        14
                Capacitor Q [6]                                        >100     >100      >100      >100      >100
                                            2
                 RF capacitor density (fF/µm ) [7]                      2        4         4         5         5

         Manufacturable solutions exist, and are being optimized
                           Manufacturable solutions are known
                                     Interim solutions are known   
                         Manufacturable solutions are NOT known
ments—Near and Long-term years
             2012      2013       2014      2015      2016      2017      2018      2019      2020      2021



              11        11         11        11        11        11        11        13        13        13
             <2e-6     <2e-6      <2e-6     <2e-6     <2e-6     <2e-6     <2e-6     <2e-5     <2e-5     <2e-5



              0.05     0.08       0.08      0.08      0.08      0.08      0.08      0.08      0.08      0.08
             40-80      30         30        30        30        30        30        20        20        20
              0.15     0.1        0.1       0.1       0.1       0.1       0.1       0.08      0.08      0.08
               50       50         50        50        50        50        50        50        50        50

              0.1       0.1        0.1       0.1       0.1       0.1       0.1       0.1       0.1       0.1
             40-80       30         30        30        30        30        30        30        30        20
              1.7        1          1         1         1         1         1        0.08      0.08      0.08
            200–300   200–300    200–300   200–300   200–300   200–300   200–300   200–300   200–300   200–300



               5         7          7         7        10        10        10        12        12        12
             < 100     < 100      < 100     < 100     < 100     < 100     < 100     < 100     < 100     < 100
             <1e-8     <1e-8      <1e-8     <1e-8     <1e-8     <1e-8     <1e-8     <1e-8     <1e-8     <1e-8
              0.4       0.3        0.3       0.3       0.2       0.2       0.2       0.2       0.2       0.2
              >50       >50        >50       >50       >50       >50       >50       >50       >50       >50

              6.5       7.5        8.6       9.9      11.4      13.1      15.1       17.4      20        23
             <100      <100       <100      <100      <100      <100      <100      <100      <100      <100
             <0.15     <0.1       <0.1      <0.1      <0.1      <0.1      <0.1      <0.08     <0.08     <0.08

              38        40         42        44        46        48        50        52        54        56

              >5.5     >5.5       >5.5      >5.5      >5.5      >5.5      >5.5      >5.5      >5.5      >5.5
               45       50         50        55        55        60        60        65        65        70



              30        30         30        30        30        30        30        30        30        30
             >100      >100       >100      >100      >100      >100      >100      >100      >100      >100
               2         2          2         2         2         2         2         2         2         2

              18        18         18        18        18        18        18        18        18        18
             >100      >100       >100      >100      >100      >100      >100      >100      >100      >100
               5        7          7         7         10        10        10        10        12        12
 2022



  13
 <2e-5



 0.08
  20
 0.08
  50

  0.1
   20
  0.08
200–300



  12
 < 100
 <1e-8
  0.2
  >50

  26.4
 <100
 <0.08

  58

 >5.5
  70



  30
 >100
   2

  18
 >100
  12
INDEX LINK   Table RFAMS4                                                     Embedded Passives Technology Requirements—Nearand Long-t
             Year of Production                                                   2007   2008     2009     2010     2011
             Resistor [1]
                 Max Sheet resistance, Rs (Ohm/sq)                                 1K     1K       1K       10K     100K
                 Tolerance (%) [2]                                                <10%   <10%     <5%      <10%     <10%
                 Temp. linearity (ppm/ºC)                                         <500   <300     <300     <500     <300
                 Min Sheet resistance, Rs (Ohm/sq)                                 100    100     100       100      10
                 Tolerance (%) [2]                                                <10%   <5%      <3%      <1%      <10%
                 Temp. linearity (ppm/ºC)                                         <300   <200     <200     <200     <300
             Capacitor [3]
                 Density (nF/cm²)                                                >2       >2       >5       >5        >5
                 Tolerance (%) [2]                                             <10%      <7%     <10%      <7%       <7%
                 TCC (ppm)                                                      <500     <300     <500     <400      <400
                 Breakdown Voltage (V)                                         >500V     >1KV    >300V    >500V     >700V
                max Q [4]                                                       >25       >30     >25      >30       >30
                Self Resonance Freq (GHz) [5]                                   >0.5     >0.5     >0.1     >0.1      >0.2
             Inductor [3]
                 Density (nH/mm2)                                                  0.4    0.4      0.8      0.8      0.8
                 Tolerance (%) [2]                                                <5%    <5%      <5%      <5%      <5%
                 max Q [6]                                                        >40    >40      >40      >40      >40
                Self Resonance Freq (GHz) [7]                                     >10    >10      >10      >10      >10



                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                              Interim solutions are known     
                                  Manufacturable solutions are NOT known
rements—Nearand Long-term years
              2012     2013       2014    2015   2016     2017     2018    2019     2020     2021

             100K     500K        500K    500K   500K     500K     500K    500K     500K     500K
             <5%      <10%        <10%    <5%    <5%      <5%      <5%     <5%      <5%      <3%
             <300     <500        <300    <300   <300     <300     <300    <300     <300     <200
              10       10          10       5      5        5        5       1        1        1
             <5%      <3%         <1%     <10%   <5%      <3%      <1%     <10%     <5%      <3%
             <200     <200        <200    <300   <200     <200     <200    <300     <200     <200

              >5       >10         >10     >10    >100     >100     >100   >1000    >1000    >1000
             <5%      <10%         <7%    <5%    <10%      <7%      <5%    <10%     <10%      <7%
             <300      <500        <300   <300    <300     <300     <200    <300     <200     <200
             >1KV     >500V       >700V   >1KV   >500V    >500V    >700V   >500V    >500V    >700V
              >30      >25         >25     >30    >15      >20      >25     >10      >15      >20
             >0.2     >0.05        >0.1   >0.1   >0.001   >0.005   >0.01   >0.001   >0.001   >0.001

               0.8      2          2       2       2        4       4        4        4        8
              <5%      <5%        <5%     <3%     <3%      <3%     <3%      <3%      <3%      <3%
              >40      >40        >40     >40     >45      >45     >45      >45      >45      >45
              >10      >10        >10     >10     >10      >10     >10      >10      >10      >10
2022

500K
<1%
<200
  1
<1%
<200

>1000
 <5%
 <200
>1KV
 >25
>0.001

  8
 <3%
 >45
 >10
INDEX LINK   Table RFAMS5                                              Power Amplifier Technology Requirements—Near and Long-term y
             Year of Production                                        2007           2008         2009    2010      2011
             Nominal battery voltage                                                         3.2                                        2.
             End-of-life battery voltage                               2.85                         2.4                                 1.
             PA product solutions                                                                            Radio/Baseband SIP [2]
             PA frequency (GHz)                                                                                      0.8-6
             III-V HBT transistor
             F max (at V cc ) (GHz)                                            45                           55
             BV CBO (V)                                                        25                                                18
             Linear efficiency (%) [1]                                         52                                                55
             Area (mm 2 ) [2]                                                  2.5                                               2.2
             Cost/mm 2 (US$) [3]                                       0.32           0.3                  0.28
             III-V HBT integration
             Bias Control                                                                                          MESFET
             Power management [4]                                                                                    N/A
             Switch [5] (by-pass)                                                                                   HEMT
             Filter [6]                                                                                              N/A
             III-V PHEMT transistor
             F max (at V dd ) (GHz)                                            45                                                75
             BV DGO (V)                                                        20                                                16
             Linear efficiency (%) [1]                                         55                                                58
             PA Area (mm 2 ) [2]                                       4               4                                         3.5
             Cost/mm 2 (US$) [3]                                       0.28           0.25                 0.24
             III-V PHEMT integration
             Power management [4]                                                                                     N/A
             Switch [7] logic integration                                                                         E/D pHEMT
             Filter [6]                                                                                               N/A
             Silicon MOSFET transistor
             T ox (PA) (Å) [8]                                                 60                                                 35
             F max (at V dd )                                                  45                                                 60
             BV DSS (V)                                                        12                                                 10
             Linear efficiency (%) [1]                                                                                45
             PA Area (mm 2 ) [2]                                               6                                                 4.5
             Cost/mm 2 (US$) [3]                                              0.08                         0.06
             Silicon MOSFET integration
             Power management [4]                                                                                    Yes
             MEMS switch [5]                                                   NO                  Stack     Above IC
             MEMS filter [6]                                                  Stack                        WLP
             SiGe HBT transistor [9]
             F max (GHz)                                                       60                                                 80
             BV CBO (V)                                                        18                                                 16
             Linear efficiency (%) [1]                                         50                                                 52
             PA Area (mm 2 ) [2]                                              2.5                                                2.2
             Cost/mm 2 (US$) [3]                                              0.12                                               0.11
             SiGe integration
             Power management                                                                                        Yes
             MEMS switch [5]                                                   NO                  Stack     Above IC
             MEMS filter [6]                                                  Stack                        WLP

             Manufacturable solutions exist, and are being optimized
             Manufacturable solutions are known
             Interim solutions are known                               
             Manufacturable solutions are NOT known
ents—Near and Long-term years
                 2012    2013          2014   2015   2016   2017      2018        2019          2020   2021
                          2.4                                                      2.4
                          1.6                                                      1.6
dio/Baseband SIP [2]                                          Radio/Baseband SIP [2]
      0.8-6

                                65                                                 65
                  18                                                               18
                  55                                                               55
                  2.2                                2.2                                    2
                                0.25                                              0.25

    MESFET                                                                      MESFET
      N/A                                                                         N/A
     HEMT                                                                        HEMT
      N/A                                                                         N/A

                  75                                                               75
                  16                                                               16
                  58                                                               58
                  3.5                                                             3.5
                         0.22                 0.15                                0.15

       N/A                                                                        N/A
   E/D pHEMT                                                                  E/D pHEMT
       N/A                                                                        N/A

                   35                                                              35
                   60                                                              60
                   10                                                              10
       45                                                                          45
                  4.5                                                             4.5
                                0.05                                              0.05

      Yes                                                                          Yes
                            Integrated                                         Integrated
                             Above IC                                           Above IC

                   80                                                              80
                   16                                                              16
                   52                                                              52
                  2.2                                2.2                                    2
                  0.11                                                            0.11

      Yes                                                                          Yes
                            Integrated                                         Integrated
                             Above IC                                           Above IC
2022
INDEX LINK   Table RFAMS6                                                 Base Station Devices Technology Requirements—Near and Long-te
             Year of Production                                             2007            2008      2009            2010      2011
             Application frequency (GHz) [1]                               0.8–3.5         0.8–3.5   0.8–3.5         0.8–5     0.8–5
              Cost ($$/Watt)                                                 0.3             0.2       0.2            0.15      0.15
             Packaging (C-Ceramic, P-Plastic)                                C, P            C, P      C, P          Plastic   Plastic
             Si LDMOS
                Operating voltage (V)                                               32, 48           32, 48                                    32, 48
                Saturated power (Watt)                                        240            300      400                                       500
                Saturated power density (W/mm)                                       1.8              1.8                                       1.8
                Saturated PAE (%)                                              55             57       60              55        57
                Linear power (Watt)                                           120            150      200                                       250
                Linear PAE (%)                                                 39             40       42              39        40
             GaAs FET
                Operating voltage (V)                                                         28                                          28
                Saturated power (Watt)                                                       240                                         240
                Saturated power density (W/mm)                                               1.5                                         1.8
                Saturated PAE (%)                                             65              67       70              65        67
                Linear power (Watt)                                                          120                                         120
                Linear PAE (%)                                                46              47       50              46        47
             GaN FET
                Operating voltage (V)                                                 48                                         48
                Saturated power (Watt)                                               200                       300                       400
                Saturated power density (W/mm)                                        4                                          5
                Saturated PAE (%)                                             60             62        65              60        62

                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                         Interim solutions are known      
                             Manufacturable solutions are NOT known
irements—Near and Long-term years
                 2012            2013           2014            2015     2016   2017   2018    2019          2020   2021
                0.8–5           0.8–5          0.8–8           0.8–8                          0.8–8
                 0.15             0.1            0.1             0.1                            0.1
                Plastic         Plastic        Plastic         Plastic                        Plastic

                      32, 48                                                                  32, 48
                       500                                                                     500
                       1.8                                                                     1.8
                                          60                                                    60
                          250                                                                  250
                                          42                                                    42

           28                                             28                                    28
          240                                            240                                   240
          1.8                                            1.8                                   1.8
                          70                              70              70                            72
          120                                            120                                   120
                          50                              50              50                            51

     48                                                   48                                    48
          400                    500                     500                                   500
      5                                                   5                                     5
                          65                              65                                    65
2022
INDEX LINK   Table RFAMS7                                     Millimeter Wave 10 GHz–100 GHz Technology Requirements
             Year of Production                                 2007          2008          2009         2010         2011
             Device Technology—FET
               GaAs PHEMT (low noise)
                 Gate length (nm)                                                    100
                 Ft (GHz)                                                            150
                 Breakdown (volts)                                                    12
                 Imax (mA/mm)                                                        700
                 Gm (S/mm)                                                           0.55
                 NFmin (dB) at 26 GHz                                                0.8
                 Associated Gain at 26 GHz                                           10.8
                 NFmin (dB) at 94 GHz                                                2.5
                 Associated Gain at 94 GHz                                           3.6
               GaAs PHEMT (power)
                 Gate length (nm)                                      150                                                   100
                 Fmax (GHz)                                            150                                                   200
                 Breakdown (volts)                                      12                                                    9
                 Imax (ma/mm)                                          700                                                   800
                 Gm (S/mm)                                             0.5                                                   0.7
                 Pout at 24 GHz and peak efficiency (mW/mm)            650                                                   650
                 Peak efficiency at 24 GHz (%)                          45                                                    50
                 Gain at 24 GHz, at P1dB (dB)                           11                                                    13
               GaAs PHEMT (power)
                 Gate length (nm)                                      100                                70
                 Fmax (GHz)                                            200                               250
                 Breakdown (volts)                                      8                                 8
                 Imax (ma/mm)                                          800                               850
                 Gm (S/mm)                                             0.65                 0.75                0.8
                 Pout at 60 GHz and peak efficiency (mW/mm)                                 550
                 Peak efficiency at 60 GHz (%)                          30                   35                  40
                 Gain at 60 GHz, at P1dB (dB)                           7                    8                   9
                 Pout at 94 GHz and peak efficiency (mW/mm)            350                  350                 350
                 Peak efficiency at 94 GHz (%)                          20                   25                  30
                 Gain at 94 GHz, at P1dB (dB)                           5                    6                   7
               InP HEMT (low noise)
                 Gate length (nm)                               100                   70                        50
                 Ft (GHz)                                       200                  250                        350
                 Breakdown (volts)                               4                    3                         2.5
                 Imax (ma/mm)                                   500                  600                        550
                 Gm (S/mm)                                      1.1                  1.5                        1.8
                 Fmin (dB) at 24 GHz                             0.5                 0.4                        0.3
                 Associated Gain (dB) at 24 GHz                  15                   16                        17
                 Fmin (dB) at 60 GHz                              1                  0.8                        0.6
                 Associated Gain (dB) at 60 GHz                  11                   12                        13
                 Fmin (dB) at 94 GHz                             1.5                 1.3                        1.1
                 Associated Gain (dB) at 94 GHz                   8                   9                         11
               InP HEMT (power)
                 Gate length (nm)                                      100                                70
                 Fmax (GHz)                                            250                               400
                 Breakdown (volts)                                      4                                 3
                 Imax (ma/mm)                                          500                               600
                 Gm (S/mm)                                             1.1                               1.5
                 Pout at 24 GHz and peak efficiency (mW/mm)            450
                 Peak efficiency at 24 GHz (%)                          50
                 Gain at 24 GHz, at P1dB (dB)                           14
                 Pout at 60 GHz and peak efficiency (mW/mm)            300                         400
  Peak efficiency at 60 GHz (%)                40           45            50
  Gain at 60 GHz, at P1dB (dB)                       10                   14
  Pout at 94 GHz and peak efficiency (mW/mm)   150          160          200
  Peak efficiency at 94 GHz (%)                30           35            40
  Gain at 94 GHz, at P1dB (dB)                        7                   10
GaAs MHEMT (low noise)—Ka through W-Band
  Gate length (nm)                                   100                        70
  Ft (GHz)                                           200                       250
  Channel In content (%)                              60                                            70
  Offstate Breakdown (volts)                          6                         4
  Imax (ma/mm)                                       900                       900
  Gm (S/mm)                                          1.2                       1.4
  Fmin (dB) at 24 GHz                                0.5                       0.4
  Associated Gain (dB) at 24GHz                       15                        16
  Fmin (dB) at 60 GHz                                 1                        0.7
  Associated Gain (dB) at 60GHz                       10                        12
  Fmin (dB) at 94 GHz                                1.5                       1.2
  Associated Gain (dB) at 94GHz                       8                         10
GaAs MHEMT (Power) -Ka band
  Gate length (nm)                                   150                       100
  Channel In content (%)                                                                     35
  Fmax (GHz)                                         200                       250
 Offstate Breakdown (volts)                           8                         10
  Imax (ma/mm)                                       760                       850
  Gm (S/mm)                                          0.85                       1
  Pout at 24 GHz and peak efficiency (mW/mm)         800                       850
  Peak efficiency at 24 GHz (%)                       45                        50
  Gain at 24 GHz, at P1dB (dB)                        12                        14
GaAs MHEMT (Power)
  Gate length (nm)                                   100                        70
  Channel In content (%)                              53                        43
  Fmax (GHz)                                         300                       300
 Offstate Breakdown (volts)                           7                                                  9
  Imax (ma/mm)                                       900                       900
  Gm (S/mm)                                          1.2                       1.4
  Pout at 60 GHz and peak efficiency (mW/mm)         500                       550
  Peak efficiency at 60 GHz (%)                       40                        45
  Gain at 60 GHz, at P1dB (dB)                        8                         9
  Pout at 94 GHz and peak efficiency (mW/mm)         225                       300
  Peak efficiency at 94 GHz (%)                       30                        35
  Gain at 94 GHz, at P1dB (dB)                        6                         7
GaN HEMT (low noise)
 Gate Length (nm)                                                 150                 100
  Ft (GHz)                                                        120                 160
  Breakdown (volts)                                                40                  35
  Imax (ma/mm)                                                    1000         1200          1300
  Gm (S/mm)                                                        0.4          0.5          0.55
  Fmin (dB) at 24 GHz                                             1.2                 1
  Associated Gain at 24 GHz                                       10                  12
GaN HEMT (power)
 Gate Length (nm)                                                                                            150
  Ft (GHz)                                                                                                   150
  Breakdown (volts)                                                             60
  Imax (ma/mm)                                                                        1200
                                                                                       0.5
  Gm (S/mm)                                                                            0.5
    Pout at 24 GHz and peak efficiency (mW/mm)                                               5000          6000
    Peak efficiency at 24 GHz (%)                                                             35            40
    Gain at 24 GHz, at P1dB (dB)                                                                    10
  GaN HEMT (power)
    Gate length (nm)                                                                                100
    Fmax (GHz)                                                                                      200
    Breakdown (volts)                                                                        40            60
    Imax (ma/mm)                                                                                    1200
    Gm (S/mm)                                                                                       0.55
    Pout at 60 GHz and peak efficiency (mW/mm)                                               4000          4500
    Peak efficiency at 60 GHz (%)                                                                   30
    Gain at 60 GHz, at P1dB (dB)                                                              8             8.5
    Pout at 94 GHz and peak efficiency (mW/mm)                                               2500          3000
    Peak efficiency at 94 GHz (%)                                                             20            25
    Gain at 94 GHz, at P1dB (dB)                                                              6             6.5
Device Technology—RF CMOS
 CMOS NFET [1 HP CMOS lag 2 yrs]
   Vdd: Power Supply Voltage (V)                                          1.1                               1
EOT: Equivalent Oxide Thickness (Å) [13]                             12         11            9            7.5
    Lg: Physical Lgate for High Performance logic (nm)               32    28          25     22            20
    Peak Ft (GHz)                                                   280   320         360    400           440
    Peak Fmax (GHz)                                                 340   390         440    510           560
    NFmin (dB) at 24GHz                                              2    1.8         1.6    1.4           1.3
    NFmin (dB) at 60GHz                                             5.1   4.5          4     3.6           3.3

Device Technology—HBT
  InP HBT
    Emitter width (nm)                                               1    0.5         0.5                  0.25
    Peak Ft (GHz)                                                   150         320                        400
    Peak Fmax (GHz)                                                 200         320                        560
    BVceo                                                            8           5                          4
    Jc at Peak Ft (mA/µm2)                                          1            5                         10
  SiGe HBT
    Emitter width (nm)                                              130   120                100
    Peak Ft (GHz) [Vbc=1V]                                          250   275         300    320           340
    Peak Fmax (GHz)                                                 280   305         330    350           370
    Nfmin (dB) at 60GHz                                              3    2.5         2.2    1.9           1.7
    BVceo                                                           1.8   1.7         1.65   1.6           1.55
    Jc at Peak Ft (mA/µm2)                                           13    15          17     18            19

      Manufacturable solutions exist, and are being optimized
                        Manufacturable solutions are known
                                Interim solutions are known     
                    Manufacturable solutions are NOT known
chnology Requirements
              2012         2013         2014          2015




               100
               200
                9
               800
               0.7
               650
                50
                13




                      35                        25
                     420                       500
                      2                        1.5
                                  500
                      2                        2.2
                     0.3                       0.25
                     18                         20
                     0.6                       0.5
                     14                         16
                      1                        0.9
                     12                         14

                                   50
                                  450
                                  2.5
                                  600
                                  1.7
                     50                  35
                    350                 420
     70                                  70
                     3                  2.5
                    950                 950
                    1.5                 1.8
                    0.3                 0.2
                     17                  18
                    0.6                 0.4
                     14                  15
                     1                  0.8
                     12                  13

                          70
35
                          300
                           9
                          900
                          1.2
                          900
                           55
                           15

                           50
                           35
                          325
          9
                          950
                          1.5
                          600
                           55
                           10
                          350
                           45
                           8

               70                 50
              200                240
               30                 25
                          1400
              0.6                0.65
              0.8                0.6
              13                  14

              150
              150
                    80
                          1400

                          0.6
       7000                 8000
       42.5                  45
                     12

               70                   50
              240                  280
       40      60           60      40
                     1500
                     0.65
              5000                 4500
               35                   40
        9             9.5           10
       3500          4000          3500
              30                    35
        7            7.5            8



 1            0.95          0.9    0.9
       6.5    5.5            5      6
        18     16            14     13
       490    550           630    670
       630    710           820    880
       1.2    1.1            1     0.9
        3     2.7           2.4    2.3




0.25                        0.13
400                         560
560                         800
 4                           3
10                           20

               90                   80
       360    380           395    415
       390    410           425    445
       1.5    1.4           1.3    1.2
       1.5    1.45          1.4    1.35
        21     22            23     24
INDEX LINK   Table RFAMS8                  RF and Analog Mixed-Signal RFMEMS
             Year of Production                   2007                       2008                   2009
             Design Tools
             BAW                            (0) Separate tools      (1) IRFM, (2) CM                             (3) DF
             Resonator                      (0) Separate tools      (1) IRFM, (2) CM                             (3) DF
             Switch—capacitive contact                 (0) Separate tools,                         (1) IRFM

                                                               (2) CM
             Switch—metal contact                        (0) Separate tools,                       (1) IRFM
                                                               (2) CM
             All MEMS devices                                         (4) MEMS TCAD            (4) MEMS TCAD



             Packaging
             BAW                              Die stacking.                                Wafer level package.
                                                                                           Micro cavity package.
             Resonator                                                               Stacked die
             Switch—capacitive contact                                                     Above IC integration
             Switch—metal contact                                                          Above IC integration



             Performance Driver
             BAW                           F= 900MHz to 2.5GHz.                  F= 900MHz to 5GHz.
                                               Size and cost;

                                                  TCF=                          Testability improved.
                                           -20 ppm/K; K2*Q=100                 TCF= -5ppm; K2*Q=150
             Resonator                                    Real time clock                                Clock oscillator
                                                             (32 kHz)                           (10–100MHz) multi-frequency per die.

             Switch—capacitive contact t                                                 Cellular frontend (tuning):
                                                                                       20:1 tuning ratio, 40V actuation


             Switch—metal contact                                           Cellular frontend (tuning, T/R): insertion loss <0.3dB,

                                                                                            lifetime >1e10 cycles


             Cost Driver
             BAW                                                                              Die size / package
             Resonator                              MEMS processing cost                          Packaging
             Switch—capacitive contact                                                        Processing cost.

                                                                                    Die size / microcavity package. Test.

             Switch—metal contact                                                                 Process cost.
                                                                                Reliability / size / microcavity package. Test.
                           2010                  2011                   2012                    2013

                (3) DF                                            DF + MEMS TCAD
                (3) DF
                          (3) DF



                          (3) DF




 level package.                                                 Above IC integration
cavity package.
                                                Embedded integration with IC
 IC integration                                          Embedded integration with IC
 IC integration                                          Embedded integration with IC




                    Coupled Resonator Filter (CRF) ≥ increase      F= 900MHz to 10GHz. Built In Self Test
                      functionality (e.g., impedance match).          (BIST) structure. Tunable filter?

                                                                           TCF= -1ppm; K2*Q=200

      Clock oscillator                          Nano resonator for filter function (800MHz–2.5GHz)
–100MHz) multi-frequency per die.

rontend (tuning):                                             Cellular frontend (tuning):
ratio, 40V actuation                                               30:1 tuning ratio,
                                                                low-voltage actuation
ng, T/R): insertion loss <0.3dB,                Cellular frontend (tuning, T/R): insertion loss <0.2dB,

e >1e10 cycles                                                  lifetime >1e11 cycles



ize / package                                            Integration with semiconductor die
                                             Integration with semiconductor die
cessing cost.                                            Integration with semiconductor die

ocavity package. Test.

ocess cost.                                              Integration with semiconductor die
microcavity package. Test.
INDEX LINK   Table PIDS1          Process Integration Difficult Challenges—Near and Long-term Years

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table PIDS2                                            High-performance Logic Technology Requirements—Near and Long-ter

             Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or doub
             beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion).
             Year of Production                                          2007          2008         2009           2010          2011
             L g : Physical Lgate for High Performance logic (nm)
             [1]                                                          25             22           20             18            16
             EOT: Equivalent Oxide Thickness [2]
               Extended planar bulk (Å)                                   11              9          7.5            6.5           5.5
               UTB FD (Å)                                                                                             7             6
               DG (Å)                                                                                                               8
             Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3]
               Extended Planar Bulk (Å)                                   7.4           3.1          2.9            2.8           2.7
               UTB FD (Å)                                                                                             4             4
               DG (Å)                                                                                                               4
             EOT elec : Electrical Equivalent Oxide Thickness in inversion [4]
              Extended Planar Bulk (Å)                                   18.4        12.1          10.4           9.3           8.2
              UTB FD (Å)                                                                                          11            10
              DG (Å)                                                                                                            12
             J g,limit : Maximum gate leakage current density [5]
                                           2
              Extended Planar Bulk (A/cm )                           8.00E+02      9.09E+02     1.00E+03      1.11E+03      1.25E+03
                              2
              UTB FD (A/cm )                                                                                  1.11E+03      1.25E+03
                         2
              DG (A/cm )                                                                                                    1.25E+03
             V dd : Power Supply Voltage (V) [6]
              Extended Planar Bulk (V)                                   1.1           1             1             1           0.95
              UTB FD and DG (V)                                                                                    1            1
             V t,sat : Saturation Threshold Voltage [7]
              Extended Planar Bulk (mV)                                 134           94            94           103           101
              UTB FD (mV)                                                                                        103            89
              DG (mV)                                                                                                          115
             I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8]
                Extended Planar Bulk (µA/µm)                             0.34        0.71           0.7          0.64          0.74
                UTB FD (µA/µm)                                                                                   0.33          0.52
                DG (µA/µm)                                                                                                     0.2
             I d,sat : NMOS Drive Current [9]
              Extended Planar Bulk (µA/µm)                              1211         1513          1639          1807          1824
              UTB FD (µA/µm)                                                                                     1948          2000
              DG (µA/µm)                                                                                                       1917
             Mobility enhancement factor due to strain [10]              1.8          1.8           1.8           1.8           1.8
             I d,sat enhancement factor due to strain [11]
               Extended Planar Bulk                                     1.09         1.08          1.08          1.08          1.09
               UTB FD                                                                                            1.07          1.06
               DG                                                                                                              1.04
             Effective Ballistic Enhancement Factor , Kbal [12]
               Extended Planar Bulk                                       1            1             1            1             1
               UTB FD                                                                                            1.05          1.1
               DG                                                                                                              1.17
             R sd : Effective Parasitic series source/drain resistance [13]
               Extended Planar Bulk (Ω-µm)                                200         200          200           180           180
               UTB FD (Ω-µm)                                                                                     180           180
               DG (Ω-µm)                                                                                                       180
             C g,ideal : Ideal NMOS Device Gate Capacitance [14]
               Extended Planar Bulk (F/µm)                       4. 70E-16         6.30E-16      6.63E-16     6.70E-16      6.71E-16
               UTB FD (F/µm)                                                                                  5.65E-16      5.52E-16
   DG (F/µm)                                                                                                      4.60E-16
 C g,total : Total gate capacitance for calculation of CV/I [15]
   Extended Planar Bulk (F/µm)                              7.10E-16    8.40E-16      8.43E-16      8.40E-16      8.35E-16
   UTB FD (F/µm)                                                                                    8.08E-16      7.22E-16
   DG (F/µm)                                                                                                      6.50E-16
 τ =CV/I: NMOSFET intrinsic delay (ps) [16]
   Extended Planar Bulk (ps)                                   0.64        0.55          0.51          0.46          0.43
   UTB FD (ps)                                                                                         0.41          0.36
   DG (ps)                                                                                                           0.34
 1/τ: NMOSFET intrinsic switching speed (GHz) [17]
   Extended Planar Bulk (GHz)                                 1563        1818          1961           2174          2326
   UTB FD (GHz)                                                                                        2439          2778
   DG (GHz)                                                                                                          2941

Manufacturable solutions exist, and are being optimized
                  Manufacturable solutions are known
                         Interim solutions are known      
             Manufacturable solutions are NOT known




                  Table PIDS2b High-performance Logic Technology Requirements—Long-term Years
 Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double-
 gate (DG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for
 further discussion).
 Year of Production                                           2016           2017         2018           2019          2020
 MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)                 22             20           18             16             14
 MPU Physical Gate Length (nm)                                  9             8             7             6.3            5.6
 L g : Physical Lgate for High Performance logic (nm)
 [1]                                                            9             8             7              6             5.5
 EOT: Equivalent Oxide Thickness [2]
  Extended planar bulk (Å)
  UTB FD (Å)
  DG (Å)                                                   5.5             5.5           5.5             5             5
 Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3]
  Extended Planar Bulk (Å)
  UTB FD (Å)
  DG (Å)                                                    4               4              4             4             4
 EOT elec : Electrical Equivalent Oxide Thickness in inversion [4]
  Extended Planar Bulk (Å)
  UTB FD (Å)
  DG (Å)                                                      9.5          9.5           9.5             9             9
 J g,limit : Maximum gate leakage current density [5]
                               2
   Extended Planar Bulk (A/cm )
                  2
   UTB FD (A/cm )
             2
   DG (A/cm )                                             2.22E+03      2.50E+03      2.86E+03      3.33E+03      3.64E+03
 V dd : Power Supply Voltage (V) [6]
   Extended Planar Bulk (V)
   UTB FD and DG (V)                                          0.8          0.7           0.7            0.7          0.65
 V t,sat : Saturation Threshold Voltage [7]
   Extended Planar Bulk (mV)
   UTB FD (mV)
   DG (mV)                                                    110        109        114        119        123
 I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8]
    Extended Planar Bulk (µA/µm)
    UTB FD (µA/µm)
    DG (µA/µm)                                               0.44        0.48       0.45       0.47       0.43
 I d,sat : NMOS Drive Current [9]
    Extended Planar Bulk (µA/µm)
    UTB FD (µA/µm)
    DG (µA/µm)                                                2627      2533       2804       2768       2677
 Mobility enhancement factor due to strain [10]                1.8       1.8        1.8        1.8        1.8
  I d,sat enhancement factor due to strain [11]
    Extended Planar Bulk
    UTB FD
    DG                                                        1.03       1.03       1.02       1.02       1.02
 Effective Ballistic Enhancement Factor , Kbal [12]
   Extended Planar Bulk
   UTB FD
   DG                                                         1.67       1.87       1.99       1.97       2.11
 R sd : Effective Parasitic series source/drain resistance [13]
   Extended Planar Bulk (Ω-µm)
   UTB FD (Ω-µm)
   DG (Ω-µm)                                                  155        150        145        145        145
 C g,ideal : Ideal NMOS Device Gate Capacitance [14]
   Extended Planar Bulk (F/µm)
   UTB FD (F/µm)
   DG (F/µm)                                         3.27E-16          2.91E-16   2.68E-16   2.30E-16   2.11E-16
 C g,total : Total gate capacitance for calculation of CV/I [15]
   Extended Planar Bulk (F/µm)
   UTB FD (F/µm)
   DG (F/µm)                                                5.07E-16   4.81E-16   4.58E-16   4.10E-16   3.91E-16
 τ=CV/I: NMOSFET intrinsic delay (ps) [16]
   Extended Planar Bulk (ps)
   UTB FD (ps)
   DG (ps)                                                     0.15      0.13       0.11       0.1        0.09
 1/τ: NMOSFET intrinsic switching speed (GHz) [17]
   Extended Planar Bulk (GHz)
   UTB FD (GHz)
   DG (GHz)                                                   6667      7692       9091      1.00E+04   1.11E+04


Manufacturable solutions exist, and are being optimized
                  Manufacturable solutions are known
                         Interim solutions are known      
             Manufacturable solutions are NOT known
Requirements—Near and Long-term Years

n body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or
 the table notes for further discussion).
                       2012           2013     2014       2015        2016       2017       2018       2019       2020       2021

                    14           13           11           10           9          8          7          6         5.5         5

                     5
                    5.5           5            5           5
                     7            6            6           6           5.5        5.5        5.5         5          5          5

                    2.6
                     4            4            4           4
                     4            4            4           4            4          4          4          4          4          4


                    7.6
                    9.5          9            9            9
                    11           10           10           10          9.5        9.5        9.5         9          9          9


                 1.43E+03
                 1.43E+03     1.54E+03     1.82E+03    2.00E+03
                 1.43E+03     1.54E+03     1.82E+03    2.00E+03      2.22E+03   2.50E+03   2.86E+03   3.33E+03   3.64E+03   4.00E+03


                    0.9
                    0.9          0.9          0.9         0.8          0.8        0.7        0.7        0.7        0.65       0.65


                    112
                     87           93          99           99
                    105          103         108          111          110        109        114        119        123        115


                    0.68
                    0.62        0.56         0.55         0.6
                    0.34        0.37         0.38         0.38         0.44       0.48       0.45       0.47       0.43       0.62


                   1762
                   1944         2109         2245         2030
                   1943         2204         2365         2295        2627       2533       2804       2768       2677       2799
                    1.8          1.8          1.8          1.8         1.8        1.8        1.8        1.8        1.8        1.8


                    1.08
                    1.06        1.06         1.05         1.05
                    1.04        1.04         1.03         1.03         1.03       1.03       1.02       1.02       1.02       1.02

                     1
                    1.16        1.2          1.24         1.28
                    1.25        1.31         1.37         1.53         1.67       1.87       1.99       1.97       2.11       2.11


                    180
                    180          170         160          160
                    180          170         160          160          155        150        145        145        145        135


                 6.33E-16
                 5.08E-16     4.98E-16     4.22E-16     3.83E-16
                    4.39E-16      4.48E-16        3.80E-16   3.45E-16   3.27E-16   2.91E-16   2.68E-16   2.30E-16   2.11E-16   1.92E-16


                    7.93E-16
                    6.78E-16      6.58E-16        5.82E-16   5.43E-16
                    6.29E-16      6.28E-16        5.59E-16   5.25E-16   5.07E-16   4.81E-16   4.58E-16   4.10E-16   3.91E-16   3.62E-16

                      0.4
                      0.31           0.28           0.23       0.21
                      0.29           0.26           0.21       0.18       0.15       0.13       0.11       0.1        0.09       0.08

                      2500
                      3226           3571          4348       4762
                      3448           3846          4762       5556       6667       7692       9091      1.00E+04   1.11E+04   1.25E+04




s—Long-term Years
body fully depleted (UTB FD) SOI or double-
l scaling (see the text and the table notes for

                      2021           2022
                       13             11
                        5             4.5


                        5             4.5




                        5              5




                        4              4




                        9              9




                   4.00E+03       4.44E+03



                      0.65           0.65
  115        118




  0.62       0.6




 2799       2786
  1.8        1.8




  1.02       1.02




  2.11       2.11




  135        135




1.92E-16   1.72E-16




3.62E-16   3.42E-16




  0.08       0.08




1.25E+04   1.25E+04
 2022

  4.5




   5




   4




   9




4.44E+03



  0.65




  118




  0.6




 2786
  1.8




  1.02




  2.11




  135
1.72E-16




3.42E-16




  0.08




1.25E+04
INDEX LINK   Table PIDS3a and b                                                  Low Standby Power Technology Requirements—Near and Long

             Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double
             planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion).
             Year in Production                                                      2007         2008           2009           2010
             L g : Physical gate length for LSTP [1]
              Extended Planar Bulk and DG (nm)                                      45             37            32            28
              UTB FD (nm)
             EOT: Equivalent Oxide Thickness [2]
              Extended planar bulk (Å)                                              19             16            15            14
              UTB FD (Å)
              DG (Å)
             Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3]
              Extended planar bulk (Å)                                              6.2           3.3           3.4           3.3
              UTB FD (Å)
              DG (Å)
             EOT elec : Electrical Equivalent Oxide Thickness in inversion [4]
              Extended planar bulk (Å)                                              25.2         19.3           18.4          17.3
              UTB FD (Å)
              DG (Å)
             J g,limit : Maximum gate leakage current density [5]
                                           2
              Extended Planar Bulk (A/cm )                                        6.67E-02     8.11E-02      9.38E-02      1.07E-01
                              2
              UTB FD (A/cm )
                         2
              DG (A/cm )
             V dd : Power Supply Voltage (V) [6]
              Extended Planar Bulk (V)                                              1.1           1.1            1             1
              UTB FD (V)
              DG (V)
             V t,sat : Saturation Threshold Voltage [7]
              Extended Planar Bulk (mV)                                             534           567           535           535
              UTB FD (mV)
              DG (mV)
             I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8]
                Extended Planar Bulk (µA/µm)                                     3.03E-05      3.03E-05      3.05E-05      3.07E-05
                UTB FD (µA/µm)
                DG (µA/µm)
             I d,sat : NMOS Drive Current [9]
              Extended Planar Bulk (µA/µm)                                          465           569           501           528
              UTB FD (µA/µm)
              DG (µA/µm)
             Mobility enhancement factor due to strain [10]
              Extended Planar Bulk                                                  1.8           1.8           1.8           1.8
              UTB FD and DG
             I d,sat enhancement factor due to strain [11]
               Extended Planar Bulk                                                 1.19         1.17           1.16          1.17
               UTB FD
               DG
             Effective Ballistic Enhancement Factor [12]
               Extended Planar Bulk                                                  1             1             1             1
               UTB FD
               DG
             R sd : Effective Parasitic series source/drain resistance [13]
              Extended Planar Bulk (Ω-µm)                                           180           180           180           180
              UTB FD (Ω-µm)
 DG (Ω-µm)
C g,ideal : Ideal NMOS Device Gate Capacitance [14]
 Extended Planar Bulk (F/µm)                                       6.17E-16   6.62E-16   6.01E-16   5.58E-16
 UTB FD (F/µm)
 DG (F/µm)
C g,total : Total gate capacitance for calculation of CV/I [15]
  Extended Planar Bulk (F/µm)                                      8.57E-16   9.02E-16   8.21E-16   7.68E-16
  UTB FD (F/µm)
  DG (F/µm)
τ =CV/I: NMOSFET intrinsic delay (ps) [16]
  Extended Planar Bulk (ps)                                            2.03     1.74       1.64       1.46
  UTB FD (ps)
  DG (ps)
1/τ: NMOSFET intrinsic switching speed (GHz) [17]
  Extended Planar Bulk (GHz)                                           493      575        610        685
  UTB FD (GHz)
  DG (GHz)

         Manufacturable solutions exist, and are being optimized
                           Manufacturable solutions are known
                                   Interim solutions are known     
                       Manufacturable solutions are NOT known
ogy Requirements—Near and Long-term Years

hin body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond when
notes for further discussion).
                       2011        2012         2013        2014         2015       2016       2017       2018       2019       2020


                     25           22           20           18           16           14         13         12         11         10
                                  22           20           18           17           16         15

                     13           12           11
                                  13           12           11           10           9          8
                                  14           13           12           11           11         10         10         9          9

                     3.2          3.1          3.1
                                   4            4           4            4            4          4
                                   4            4           4            4            4          4          4          4          4


                    16.2         15.1         14.1
                                  17           16           15           14           13         12
                                  18           17           16           15           15         14         14         13         13


                  1.20E-01     1.36E-01     1.50E-01

                               1.36E-01     1.50E-01     1.67E-01    1.76E-01      1.88E-01   2.00E-01
                               1.36E-01     1.50E-01    1.67E-01     1.88E-01      2.14E-01   2.31E-01   2.50E-01   2.73E-01   3.00E-01


                      1           1           0.95
                                 0.9          0.9          0.9          0.85         0.8        0.8
                                 0.85         0.85         0.85         0.8          0.8        0.8        0.8        0.75       0.75


                     544         552          547
                                 395          399          401          404          404        405
                                 380          362          361          366          366        371        365        374        378


                  3.02E-05     3.02E-05     3.03E-05
                               3.14E-05     3.09E-05     3.17E-05    3.02E-05      3.10E-05   3.27E-05
                               1.15E-05     2.44E-05     2.82E-05    2.65E-05      2.97E-05   2.55E-05   3.38E-05   2.62E-05   2.39E-05


                     542         560          519
                                 608          669          744          786          771        838
                                 550          612          674          702          738        839        889        895        935

                     1.8          1.8          1.8
                                  1.4          1.8          1.8         1.8          1.8        1.8        1.8        1.8        1.8


                    1.17         1.16         1.17
                                 1.04         1.07         1.07         1.07         1.08       1.07
                                 1.03         1.05         1.05         1.05         1.04       1.04       1.04       1.04       1.04

                      1            1            1
                                   1            1           1           1.1          1.15       1.18
                                   1            1           1           1.1          1.15       1.22       1.27       1.4        1.45


                     180         180          180
                                 200          200          180          160          150        150
             210        210        200        200        200         180        180        170        160


5.32E-16   5.02E-16   4.90E-16
           4.46E-16   4.31E-16   4.14E-16   4.19E-16   4.25E-16   4.31E-16
           4.22E-16   4.06E-16   3.88E-16   3.68E-16   3.22E-16    3.20E-16   2.96E-16   2.92E-16   2.65E-16


7.32E-16   6.92E-16   6.70E-16
           6.86E-16   6.71E-16   6.54E-16   6.39E-16   6.25E-16   6.31E-16
           6.62E-16   6.46E-16   6.28E-16   6.08E-16   5.62E-16   5.60E-16    5.26E-16   5.02E-16   4.65E-16

  1.35       1.24       1.23
             1.02       0.9        0.79       0.69       0.65       0.6
             1.02       0.9        0.79       0.69       0.61       0.53        0.47       0.42       0.37

  741        806       813
             980       1111       1266       1449        1538       1667
             980       1111       1266       1449        1639       1887        2128       2381       2703
 2021       2022


   9          8




   8          8




   4          4




   12         12




3.33E-01   3.75E-01




  0.7        0.7




  369        376




3.38E-05   2.89E-05




  934        946



  1.8        1.8




  1.04       1.04




  1.5        1.55
  140        140




2.59E-16   2.30E-16




4.49E-16   4.20E-16




  0.34       0.31




  2941       3226
INDEX LINK   Table PIDS3c and d                                               Low Operating Power Technology Requirements—Near and Long-

             Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or doub
             when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion).
             Year in Production                                                  2007         2008          2009           2010          2011
             L g : Physical gate length for LOP (nm) [1]                    32               28            25            22            20
             EOT: Equivalent Oxide Thickness [2]
               Extended planar bulk (Å)                                     12               11            10             9             8
               UTB FD (Å)                                                                                                               9
               DG (Å)                                                                                                                   9
             Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3]
               Extended planar bulk (Å)                                     6.4              3.4           3.3           3.4           3.3
               UTB FD (Å)                                                                                                               4
               DG (Å)                                                                                                                   4
             EOT elec : Electrical Equivalent Oxide Thickness in inversion [4]
              Extended planar bulk (Å)                                        18.4          14.4          13.3          12.4          11.3
              UTB FD (Å)                                                                                                               13
              DG (Å)                                                                                                                   13
             J g,limit : Maximum gate leakage current density [5]
                                            2
              Extended Planar Bulk (A/ cm )                                      78          89           100           114           125
                               2
              UTB FD (A/ cm )                                                                                                         125
                         2
              DG (A/ cm )                                                                                                             125
             V dd : Power Supply Voltage (V) [6]
               Extended Planar Bulk (V)                                          0.8         0.8           0.8           0.7           0.7
               UTB FD (V)                                                                                                              0.7
               DG (V)                                                                                                                  0.7
             V t,sat : Saturation Threshold Voltage [7]
              Extended Planar Bulk (mV)                                          294        296           289           259           246
              UTB FD (mV)                                                                                                             218
              DG (mV)                                                                                                                 207
             I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8]
                Extended Planar Bulk (µA/µm)                                9.08E-03      7.35E-03      8.96E-03      1.83E-02      2.55E-02
                UTB FD (µA/µm)                                                                                                      8.32E-03
                DG (µA/µm)                                                                                                          5.84E-03
             I d,sat : NMOS Drive Current [9]
              Extended Planar Bulk (µA/µm)                                       563        705           760           682           754
              UTB FD (µA/µm)                                                                                                          766
              DG (µA/µm)                                                                                                              780
             Mobility enhancement factor due to strain [10]                      1.8         1.8           1.8           1.8          1.8
             I d,sat enhancement factor due to strain [11]
               Extended Planar Bulk                                              1.15       1.11          1.11          1.11          1.1
               UTB FD                                                                                                                 1.07
               DG                                                                                                                     1.05
             Effective Ballistic Enhancement Factor [12]
               Extended Planar Bulk                                               1           1             1             1             1
               UTB FD                                                                                                                   1
               DG                                                                                                                       1
             R sd : Effective Parasitic series source/drain resistance [13]
               Extended Planar Bulk (Ω-µm)                                       190        190           190           190           190
               UTB FD (Ω-µm)                                                                                                          190
               DG (Ω-µm)                                                                                                              190
             C g,ideal : Ideal NMOS Device Gate Capacitance [14]
              Extended Planar Bulk (F/µm)                                      6.01E-16   6.70E-16      6.48E-16      6.13E-16      6.12E-16
              UTB FD (F/µm)                                                                                                         5.31E-16
 DG (F/µm)                                                                                                  5.31E-16
C g,total : Total gate capacitance for calculation of CV/I [15]
  Extended Planar Bulk (F/µm)                                   8.41E-16   9.10E-16   8.78E-16   8.13E-16   8.12E-16
  UTB FD (F/µm)                                                                                             7.51E-16
  DG (F/µm)                                                                                                 7.71E-16
τ = CV/I: NMOSFET intrinsic delay (ps) [16]
  Extended Planar Bulk (ps)                                       1.19       1.03       0.92       0.83       0.75
  UTB FD (ps)                                                                                                 0.69
  DG (ps)                                                                                                     0.69
1/τ: NMOSFET intrinsic switching speed (GHz) [17]
  Extended Planar Bulk (GHz)                                       840       971       1087       1205       1333
  UTB FD (GHz)                                                                                               1449
  DG (GHz)                                                                                                   1449

    Manufacturable solutions exist, and are being optimized
                      Manufacturable solutions are known
                             Interim solutions are known      
                 Manufacturable solutions are NOT known
uirements—Near and Long-term Years

fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond
s for further discussion).
                       2012       2013        2014        2015        2016       2017       2018       2019       2020       2021
                    18           16           14           13          11         10          9          8          7         6.5

                     8
                     9            8            8           8            7
                     9            9            8           8            8          7          7          7          7          6

                    3.2
                     4            4            4           4            4
                     4            4            4           4            4          4          4          4          4          4


                   11.2
                    13           12           12           12          11
                    13           13           12           12          12         11         11         11         11         10


                    139

                    139          156         179          192          227

                    139          156         179          192          227        250        278        313        357        385


                    0.7
                    0.7          0.6          0.6         0.6          0.5
                    0.7          0.6          0.6         0.6          0.6        0.5        0.5        0.5        0.5        0.45


                    249
                    209          195         202          202          187
                    202          203         201          202          202        188        194        190        195        190


                 3.57E-02
                 1.19E-02     2.02E-02     1.86E-02    1.98E-02      3.71E-02
                 7.73E-03     8.61E-03     1.07E-02    1.10E-02      1.31E-02   2.23E-02   1.94E-02   2.55E-02   2.41E-02   3.26E-02


                    760
                    788          747         763          810          716
                    821          754         826          893          916        808        850        900        919        874
                    1.8          1.8         1.8          1.8          1.8        1.8        1.8        1.8        1.8        1.8


                   1.09
                   1.07         1.07         1.06         1.06         1.06
                   1.05         1.05         1.05         1.04         1.04       1.04       1.04       1.04       1.03       1.03

                     1
                     1          1.09         1.1          1.15         1.24
                     1          1.15         1.18         1.25         1.27       1.35       1.43       1.45       1.5        1.6


                    190
                    190          180         170          165          160
                    180          180         180          170          170        155        150        140        140        140


                 5.54E-16
                 4.78E-16     4.60E-16    4.02E-16     3.74E-16      3.14E-16
4.78E-16   4.25E-16   4.02E-16   3.74E-16   3.16E-16   3.14E-16   2.82E-16   2.51E-16   2.20E-16   2.24E-16


7.54E-16
6.88E-16   6.60E-16   6.02E-16   5.54E-16   5.15E-16
7.18E-16   6.65E-16   6.43E-16   6.14E-16   5.56E-16   5.24E-16   4.82E-16   4.41E-16   4.10E-16   4.14E-16

  0.69
  0.61       0.53       0.47       0.41       0.36
  0.61       0.53       0.47       0.41       0.36       0.32       0.28       0.24       0.22       0.21

 1449
 1639        1887       2128       2439      2778
 1639        1887       2128       2439      2778       3125       3571       4167       4545       4762
 2022
   6




   6




   4




  10




  417




  0.45




  201




2.40E-02




  876
  1.8




  1.03




  1.68




  140
2.07E-16




3.97E-16




  0.2




 5000
INDEX LINK   Table PIDS4                                                         DRAM Technology Requirements—Near and Long-term Year
             Year in Production                                                     2007      2008       2009       2010
                                  2
             DRAM cell size (µm ) [2]                                            0.0277      0.0202     0.015      0.0122
             DRAM storage node cell capacitor dielectric: equivalent oxide
             thickness EOT (nm) [3]                                                   1.2      0.9       0.8         0.6
             DRAM storage node cell capacitor voltage (V) [4]                        0.65     0.65       0.6         0.6
             Equivalent Electric field of capacitor dielectric, (MV/cm) [5]           5.7      7.2       7.5         10
             DRAM cell FET structure [6]                                            RCAT     RCAT       RCAT       FinFET
             DRAM cell FET dielectric: equivalent oxide thickness, EOT
             (nm) [7]                                                                 5        5         4.5         4
             Maximum Wordline (WL) level (V) [8]                                      3       2.8        2.7        2.7
             Negative Wordline (WL) use [9]                                          yes      yes        yes        yes
             Equivalent Electric field of cell FET device dielectric (MV/cm)
             [10]                                                                    6         5.6        6         6.75
             Cell Size Factor: a [11]                                                6          6         6           6
             Array Area Efficiency [12]                                             0.56      0.56       0.56       0.56
             Minimum DRAM retention time (ms) [13]                                   64        64         64         64
             DRAM soft error rate (fits) [14]                                       1000      1000       1000       1000
             V int (support FET voltage) [V] [15]                                    1.3      1.2        1.1        1.1
             Support nMOS EOT [nm] [16]                                            3.2          3         2.6        2.6
             Support PMOS Gate Electrode [17]                                   P+Poly/W    P+Poly/W   P+Poly/W   P+Poly/W
             Support Gate Oxide [18]                                              SiON        SiON       SiON       SiON
             Support min. L gate for NMOS FET, physical [nm] [19]                    100       90         75         75
             Support I sat-n [µA/µm] (25C, V g =V d =V int ) [20]                    500      465        470        450
             Support min. V tn (25C, G m,max , V d =55mV) [21]                       0.4      0.4        0.38       0.37
             Support I sat-p [µA/µm] (25C, Vg=V d =-V int ) [22]                     220      210        220        210
             Support min. V tp (25C, G m,max , V d =55mV) [23]                      -0.45     -0.4       -0.38      -0.38

                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                                  Interim solutions are known   
                                      Manufacturable solutions are NOT known
ements—Near and Long-term Years
             2011       2012       2013      2014     2015     2016     2017     2018     2019      2020
             0.0096    0.0078     0.0061    0.0054   0.0038   0.0029   0.0024   0.0019   0.00154   0.00118

              0.5        0.4        0.3       0.3      0.3      0.3      0.3      0.3      0.25      0.2
              0.55      0.55        0.5       0.5      0.45     0.45     0.4      0.4      0.35      0.35
               11        13.8       16.7      16.7      15       15      13.3     13.3      14       17.5
            FinFET     FinFET     FinFET    FinFET   FinFET   FinFET   FinFET   FinFET   FinFET    FinFET

               4         4          4         4        4       3.5      3.5      3.5      3.5       3.5
              2.7       2.7        2.6       2.6      2.4      2.3      2.3      2.3       2         2
              yes       yes        yes       yes      yes      yes      yes      yes      yes       yes

             6.75       6.75        6.5       6.5      6       6.57     6.57     6.57     5.71      5.71
               6          6          6         6       6         6        6        6        6         6
             0.56       0.56       0.56      0.56     0.56     0.56     0.56     0.56     0.56      0.56
              64         64         64        64       64       64       64       64       64        64
             1000       1000       1000      1000     1000     1000     1000     1000     1000      1000
              1.1       1.1        1.1        1       0.9      0.9      0.9      0.9       0.9       0.9
              2.5        2.2         2        1.8      1.6      1.5      1.4      1.4      1.3       1.3
           P+Poly/W   P+Poly/W   P+Poly/W     TiN      TiN      TiN      TiN      TiN      TiN       TiN
             SiON       SiON      HfSiON    HfSiON   HfSiON   HfSiON   HfSiON   HfSiON   HfSiON    HfSiON
              65         60         50        48       40       35       31       28       25        23
              410       430        450       445      440      480      550      550      550       550
              0.37      0.33       0.33      0.31     0.31     0.31     0.31     0.31     0.31      0.31
              165       170        175       170      190      215      215      215      215       215
             -0.38      -0.34      -0.34     -0.32    -0.32    -0.32    -0.32    -0.32    -0.32     -0.32
 2021      2022
0.00101   0.00086

  0.15      0.12
  0.35      0.35
  23.3      29.2
FinFET    FinFET

 3.5       3.5
  2         2
 yes       yes

 5.71      5.71
   6         6
 0.56      0.56
  64        64
 1000      1000
  0.7       0.7
  1.3       1.2
  TiN       TiN
HfSiON    HfSiON
  21        19
 550       550
 0.31      0.31
 215       215
 -0.32     -0.32
INDEX LINK   Table PIDS5                                                     Non-volatile Memory Technology Requirements—Near-term Year
             Year of Production                                                2007      2008       2009          2010        2011
             NAND Flash poly ½ Pitch (nm)                                       51        45         40            36          32
             NAND Flash
             NAND Flash technology – F (nm) [1]                                 51        45         40           36           32
             Number of word lines in one NAND string [2]                        32        32         64           64           64
             Cell type (FG, CT, 3D, etc.) [3]                                   FG        FG         FG          FG/CT         CT
             3D NAND number of memory layers                                     1         1          1            1            1
             A. Floating Gate NAND Flash
                                                        2
             Cell size – area factor a in multiples of F SLC/MLC [4]   4.0/2.0           4.0/2.0    4.0/1.3     4.0/1.0      4.0/1.0
             Tunnel oxide thickness (nm) [5]                            7-Jun             7-Jun      7-Jun       7-Jun        7-Jun
             Interpoly dielectric material [6]                          ONO               ONO        ONO         ONO          ONO
             Interpoly dielectric thickness (nm)                       13-Oct            13-Oct     13-Oct      13-Oct       13-Oct
             Gate coupling ratio (GCR) [7]                             0.6–0.7           0.6–0.7    0.6–0.7     0.6–0.7      0.6–0.7
             Control gate material [8]                                 n-Poly            n-Poly     n-Poly      n-Poly       n-Poly
             Highest W/E voltage (V) [9]                                17-19             17-19      15-17       15-17        15-17
             Endurance (erase/write cycles) [10]                     1.00E+05           1.00E+05   1.00E+05    1.00E+05     1.00E+05
             Nonvolatile data retention (years) [11]                   20-Oct            20-Oct     20-Oct      20-Oct       20-Oct
             Maximum number of bits per cell (MLC) [12]                   2                 2          3           4            4
             B. Charge trapping NAND Flash (MANOS or Barrier Engineering) [13]
                                                        2
             Cell size—area factor a in multiples of F SLC/MLC                                                   4.0/1.0     4.0/1.0
             Tunnel dielectric material [14]                                                                  SiO2 or ONO SiO2 or ONO
             Tunnel dielectric thickness EOT (nm)                                                                 4-Mar      4-Mar
             Blocking dielectric material [15]                                                                SiO2 or Al2OSiO2 or Al2O3
                                                                                                                          3
             Blocking dielectric thickness EOT (nm)                                                                6–8         6–8
             Charge trapping layer material [16]                                                                   SiN         SiN
             Charge trapping layer thickness (nm) [17]                                                             5–7         5–7
             Gate material [18]                                                                               p-Poly/Metalp-Poly/Metal
             Highest W/E voltage (V)                                                                              15-17       15-17
             Endurance (erase/write cycles) [19]                                                                1.00E+05 1.00E+05
             Nonvolatile data retention (years) [20]                                                             20-Oct      20-Oct
             Maximum number of bits per cell (MLC)                                                                  4           4
             NOR Flash
             NOR Flash technology – F (nm) [21]                                 65         57         50           45          40
             A. Floating gate NOR Flash
             Cell size—area factor a in multiples of F2 [22], [23], [24],
             [25]                                                             11-Sep    11-Sep     11-Sep       11-Sep       11-Sep
             Gate length Lg, physical (nm) [26]                                 130       120        100           90           80
             Tunnel oxide thickness (nm) [27]                                   8–9       8–9        8–9           8            8
             Interpoly dielectric material [28]                                ONO       ONO        ONO          ONO          ONO
             Interpoly dielectric thickness EOT (nm)                           13-15     13-15      13-15        13-15        13-15
             Gate coupling ratio [29]                                         0.6–0.7   0.6–0.7    0.6–0.7      0.6–0.7      0.6–0.7
             Highest W/E voltage (V) [30]                                      9-Jul     9-Jul      9-Jul        9-Jul        9-Jul
             Iread (µA) [31]                                                   25-34      23-31      21-27       20-26        19-25
             Endurance (erase/write cycles) [32]                             1.00E+05   1.00E+05   1.00E+05    1.00E+06     1.00E+06
             Nonvolatile data retention (years) [33]                           10–20      10–20      10–20       10–20        10–20
             Maximum number of bits per cell (MLC) [34]                          2          2          2           2            2
             Array architecture (with cell contact (CC) or virtual ground
             (VG))[ 35]                                                         CC        CC         CC           CC           CC
             B. Charge trapping NOR Flash (SONOS/NROM) [36]
             SONOS/NROM technology, F (nm)                                      65         57         50           45          40
                                                                         2
             SONOS/NROM cell size - area factor a in multiples of F            7-Jun     7-Jun      7-Jun        7-Jun        8-Jul
                                                                     2
             Cell size (per bit) – area factor a in multiples of F
             (SLC/MLC) [37]                                                   3.3/1.6    3.3/1.6    3.3/1.6      3.3/1.6     3.7/1.9
             Gate length Lg, physical (nm) [38]                                 140        130        120          110         110
             Tunnel oxide thickness (nm) [39]                                    5          5          5           4.5         4.5
Charge trapping layer thickness (nm) [40]                       7-May      7-May      7-May      6-Apr      6-Apr
Blocking (top) dielectric thickness EOT (nm) [41]                7–9        7–9        7–9        6–8        6–8
Highest W/E voltage (V)                                         9-Jul      9-Jul      9-Jul      8-Jun      8-Jun
Iread (µA) [31]                                               25-34         23-31      21-27      20-26      19-25
Endurance (erase/write cycles) [32]                         1.00E+05      1.00E+05   1.00E+05   1.00E+06   1.00E+06
Nonvolatile data retention (years) [33]                       10–20         10–20      10–20      10–20      10–20
Maximum number of bits per cell (physical 2-bit/cell + MLC)
[37]                                                            4            4          4          4          4
Non-charge-storage NVM
A. FeRAM (Ferroelectric RAM)
FeRAM technology – F (nm) [42]                                 180          180        180        130        130
FeRAM cell size – area factor a in
             2
multiples of F [43]                                              22         22         22         20         20
                      2
FeRAM cell size ( µm )                                          0.713      0.713      0.713       0.45       0.45
FeRAM cell structure [44]                                       2T2C       1T1C       1T1C       1T1C       1T1C
FeRAM capacitor structure [45]                                  stack      stack      stack      stack      stack
                                 2
FeRAM capacitor footprint (µm ) [46]                             0.33       0.33       0.33       0.2        0.2
                                     2
FeRAM capacitor active area (µm ) [47]                           0.33       0.33       0.33       0.2        0.2
FeRAM cap active area/footprint ratio [48]                        1          1          1          1          1
Ferro capacitor voltage (V) [49]                                 1.5        1.5        1.5        1.2        1.2
FeRAM minimum switching charge
                 2
density (µC/cm ) [50]                                             13.5       13.5       13.5       20         20
FeRAM endurance (read/write cycles) [51]                       1.00E+14   1.00E+14   1.00E+14   1.00E+14   1.00E+14
FeRAM nonvolatile data retention
(years)                                                        10 Years   10 Years   10 Years   10 Years   10 Years
B. MRAM (Magnetic RAM)
MRAM technology F (nm) [52]                                       90         65         65         45         45
MRAM cell size area factor a in multiples of F2                   20         22         19         20         18
                            2
MRAM typical cell size (µm )                                     0.16       0.09       0.08      0.041      0.036
MRAM switching field (Oe) [53]                                    35         35         35         35         35
MRAM write energy (pJ/bit) [54]                                   70         35         35         25         25
                                 2
MRAM active area per cell (µm ) [55]                             0.05      0.025      0.025      0.013      0.013
                                             2
MRAM resistance-area product (KOhm-(µm ) [56]                     2         1.1         1         0.8        0.8
MRAM magnetoresistance ratio (%) [57]                             70         70         70         70         70
MRAM nonvolatile data retention (years)                          >10        >10        >10        >10        >10
MRAM write endurance (read/write cycles)                        >3e16      >3e16      >3e16      >3e16      >3e16
MRAM endurance – tunnel junction reliability (years at bias)
[58]                                                             >10        >10        >10        >10        >10
C. PCRAM (Phase-Change RAM)
PCRAM technology F (nm) [58]                                      72         58         46         40         35
PCRAM cell size area factor a in multiples of F2 (BJT access
device) [59]                                                     4.8         4          4          4          4
                                                 2
PCRAM cell size area factor a in multiples of F (nMOSFET
access device) [60]                                               15         14         12         11         10
                             2
PCRAM typical cell size (nm ) (BJT access device) [61]          24883      13456      8464       6400       4900
                             2
PCRAM typical cell size (nm ) (nMOSFET access device)
[62]                                                            77760      47096      25392      17600      12250
PCRAM number of bits per cell (MLC) [63]                          1          1          2          2          2
                                         2
PCRAM typical cell area per bit size (µm ) (BJT access
device) [64]                                                    24883      13456      4232       3200       2450
                                         2
PCRAM typical cell area per bit size (µm ) (nMOSFET
access device) [65]                                             77760      47096      12696      8800       6125
PCRAM storage element CD (nm) [66]                               45       36         30         25         22
                                 3
PCRAM phase change volume (nm ) [67]                         373,000    195,000    112,000     64,000     43,000
PCRAM reset current (µA) [68]                                  235        170        130        100         80
PCRAM set resistance (KOhm) [69]                               3.54       4.57       5.68       7.08       8.29
                                 2
PCRAM BJT current density (A/cm ) [70]                       1.50E+07   1.50E+07   1.50E+07   1.50E+07   1.50E+07
                            2
PCRAM BJT emitter area (nm ) [71]                                4072    2642       1662       1257        962
PCRAM nMOSFET apparent current density for reset
(µA/nm) [72]                                                    1.5        1.5        1.8        1.8        1.8
PCRAM nMOSFET apparent device width (nm) [73]                   239        171        108         82         68
PCRAM nonvolatile data retention (years) [74]                   >10        >10        >10        >10        >10
PCRAM write endurance (read/write cycles) [75]               1.00E+08   1.00E+08   1.00E+10   1.00E+10   1.00E+10

   Manufacturable solutions exist, and are being optimized
                     Manufacturable solutions are known
                            Interim solutions are known      
                Manufacturable solutions are NOT known
uirements—Near-term Years
               2012        2013         2014        2015         2016        2017         2018        2019         2020        2021
                28          25           22          20           19          18           16          14           13          11

                28          25          22           20          19           18          16           14          13           11
                64          64          64           64          64           64          64           64          64           64
                CT         CT-3D       CT-3D        CT-3D       CT-3D        CT-3D       CT-3D        CT-3D       CT-3D        CT-3D
                 1           2           2            2           2            2           4            4           4            4


              4.0/1.0   4.0/1.0    4.0/1.0         4.0/1.0      4.0/1.0     4.0/1.0      4.0/1.0     4.0/1.0      4.0/1.0     4.0/1.0
               7-Jun     7-Jun      7-Jun           7-Jun          4           4            4           4            4           4
              High-κ    High-κ     High-κ          High-κ       High-κ      High-κ       High-κ      High-κ       High-κ      High-κ
              10-Sep    10-Sep     10-Sep          10-Sep       10-Sep      10-Sep       10-Sep      10-Sep       10-Sep      10-Sep
              0.6–0.7   0.6–0.7    0.6–0.7         0.6–0.7      0.6–0.7     0.6–0.7      0.6–0.7     0.6-0.7      0.6-0.7     0.6-0.7
            Poly/metal Poly/metal Poly/metal        Metal        Metal       Metal        Metal       Metal        Metal       Metal
               15-17     15-17      15-17           15-17        15-17       15-17        15-17       15-17        15-17       15-17
             1.00E+05 1.00E+05 1.00E+05           1.00E+05     1.00E+04    1.00E+04     1.00E+04    1.00E+04     1.00E+04    1.00E+04
              20-Oct    20-Oct     20-Oct          20-Oct       10-May      10-May       10-May      10-May       10-May      10-May
                 4         4          4               4            4           4            4           4            4           4


              4.0/1.0     4.0/1.0     4.0/1.0     4.0/1.0     4.0/1.0      4.0/1.0      4.0/1.0      4.0/1.0      4.0/1.0      4.0/1.0
           SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO  SiO2 or ONO  SiO2 or ONO  SiO2 or ONO  SiO2 or ONO  SiO2 or ONO
               4-Mar      4-Mar       4-Mar       4-Mar        4-Mar        4-Mar        4-Mar        4-Mar        4-Mar        4-Mar
           SiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2OSiO2 or Al2O3
                       3           3           3           3            3            3            3            3            3
                6–8         6–8         6–8         6–8         6–8          6–8          6–8          6–8          6–8          6–8
                SiN         SiN         SiN         SiN     SiN / High-κ SiN / High-κ SiN / High-κ SiN / High-κ SiN / High-κ SiN / High-κ
                5–7         5–7         5–7         4–6         4–6          4–6          4–6          4–6          4–6         4-Mar
           p-Poly/Metalp-Poly/Metalp-Poly/Metal   Metal        Metal        Metal        Metal        Metal        Metal        Metal
               15-17       15-17       15-17       15-17       15-17        15-17        15-17        15-17        15-17        15-17
             1.00E+05 1.00E+05 1.00E+05 1.00E+05 1.00E+04 1.00E+04 1.00E+04 1.00E+04 1.00E+04 1.00E+04
              20-Oct      20-Oct      20-Oct      20-Oct      10-May       10-May       10-May       10-May       10-May       10-May
                 4           4           4           4            4            4            4            4            4            4

                35           32          28           25          22           20          18           16          14           12


              11-Sep      11-Sep       11-Sep      11-Sep       13-Oct      13-Oct       13-Oct      13-Oct       13-Oct      13-Oct
                 70          64           56          50           44          40           36         32           28          24
                 8           8          8-Jul       8-Jul        8-Jul       8-Jul        8-Jul       8-Jul        8-Jul       8-Jul
               ONO        High-κ       High-κ      High-κ       High-κ      High-κ       High-κ      High-κ       High-κ      High-κ
               13-15      10-Aug       10-Aug      10-Aug       10-Aug      10-Aug        9-Jul      8-Jun        8-Jun       8-Jun
              0.6–0.7     0.6–0.7      0.6–0.7     0.6–0.7      0.6–0.7     0.6–0.7      0.6–0.7     0.6-0.7      0.6-0.7     0.6-0.7
               9-Jul       8-Jun        8-Jun       8-Jun        8-Jun       8-Jun        8-Jun      8-Jun        8-Jun       8-Jun
               17-22       15-20        14-19       13-18        12–17       11–16        10–15      14-Sep       13-Aug       12-Jul
             1.00E+06    1.00E+06     1.00E+06    1.00E+06     1.00E+07    1.00E+07     1.00E+07    1.00E+07     1.00E+07    1.00E+07
               10–20        20           20          20            20          20           20         20           20           20
                 2           2            2           2            2           2            2           2            2           2

                CC        CC/VG        CC/VG       CC/VG        CC/VG       CC/VG        CC/VG       CC/VG        CC/VG       CC/VG

                35           32          28           25          22           20          18           16          14           12
               8-Jul       8-Jul        8-Jul       9-Aug       9-Aug        9-Aug       9-Aug       10-Sep       10-Sep      10-Sep


              3.7/1.9     3.7/1.9      3.7/1.9     4.3/2.2      4.3/2.2     4.3/2.2      4.3/2.2     4.8/2.4      4.8/2.4     4.8/2.4
                100         100          90          90           80          80           70          70           70          60
                4.5          4            4           4            4           4            4          3.5          3.5         3.5
 6-Apr      6-Apr      6-Apr      5-Apr      5-Apr      5-Apr      5-Apr        4          4          4
  6–8        6–8        6–8        5–7        5–7        5–7        5–7        5–7        5–7        5–7
 8-Jun      8-Jun       5–7        5–7        5–7        5–7        5–7        5–7        5–7       6-Apr
  17-22      15-20      14-19      13-18      12–17      11–16      10–15     14-Sep     13-Aug      12-Jul
1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06   1.00E+06
  10–20      10–20      10–20      10–20      10–20      10–20      10–20      10–20      10–20      10–20

   4          4          4          6          6          6          6          6          6          6



  130        90         90         90         90         90         90         65         65         65


  20         16         16         16         14         14         14         12         12         12
  0.45       0.27       0.27       0.27      0.113      0.113      0.113      0.051      0.051      0.051
 1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C
 stack      stack      stack      stack       3D         3D         3D         3D         3D         3D
  0.2       0.106      0.106      0.106      0.041      0.041      0.041      0.016      0.016      0.016

  0.2       0.106      0.106      0.106       0.1        0.1        0.1       0.069      0.069      0.069
   1          1          1          1         2.46       2.46       2.46       4.25       4.25       4.25
  1.2        1.2        1.2        1.2         1          1          1         0.7        0.7        0.7


   20         34         34         34         30         30         30         30         30         30
1.00E+14   1.00E+15   1.00E+15   1.00E+15   >1.0E16    >1.0E16    >1.0E16    >1.0E16    >1.0E16    >1.0E16

10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years

   45         32         32         32         22         22         22         16         16         16
   18         19         17         17         18         16         16         17         16         17
 0.036      0.019      0.017      0.017      0.009      0.0077     0.0077     0.0044     0.0041     0.0044
   35         35         35         35         35         35         35         35         35         35
   25         20         20         20         20         20         20         20         20         20
 0.013      0.009      0.009      0.009      0.007      0.007      0.007      0.005      0.005      0.005

  0.8        0.6        0.6        0.6        0.6        0.6        0.6        0.6        0.6        0.6
   70         70         70         70         70         70         70         70         70         70
  >10        >10        >10        >10        >10        >10        >10        >10        >10        >10
 >3e16      >3e16      >3e16      >3e16      >3e16      >3e16      >3e16      >3e16      >3e16      >3e16

  >10        >10        >10        >10        >10        >10        >10        >10        >10        >10

   32         28         25         22         20         18         16         14         12         11

   4          4          4          4          4          4          4          4          4          4


  8.9        8.8        8.4        7.4        7.3        7.3         6          6          6         5.5
 4096       3136       2500       1936       1600       1296       1024        784        576        480


 9114       6899       5250       3582       2920       2365       1536       1176        864        650
  4          4          4          4          4          4          4          4           4          4


 1024        784        625        484        400        324        256        196        144        120


 2278       1725       1313        895        730        591        384        294        216        162
  20         18         16         14         13         12         10          9          8          8
 33,000     25,000     18,000     12,000     9,000      6,700      4,700      3,200      2,000      1,300
   70         62         52         43         37         32         27         22         18         15
  9.21       10.2      11.66      13.56      15.17      17.18      19.74      23.11      27.72        31
1.50E+07   1.50E+07   1.60E+07   1.70E+07   1.90E+07   2.00E+07   2.10E+07   2.20E+07   2.40E+07   2.50E+07

  804        616        491        380        314        254        201        154        113        91

   2.1        2.1        2.1        2.4        2.4        2.4        2.88       2.88       2.88       2.88
    51         43         36         26         23         21         16         14         12         10
   >10        >10        >10        >10        >10        >10        >10        >10        >10        >10
1.00E+12   1.00E+12   1.00E+12   1.00E+15   1.00E+15   1.00E+15   1.00E+15   1.00E+15   1.00E+15   1.00E+15
    2022
     10

    10
    64
   CT-3D
     4


  4.0/1.0
     4
  High-κ
  10-Sep
  0.6-0.7
   Metal
   15-17
 1.00E+04
  10-May
     4


   4.0/1.0
SiO2 or ONO
    4-Mar
SiO2 or Al2O3
     6–8
SiN / High-κ
    4-Mar
    Metal
    15-17
  1.00E+04
   10-May
      4

     10


   13-Oct
     20
    8-Jul
   High-κ
   8-Jun
   0.6-0.7
   8-Jun
  10-Jun
 1.00E+07
    20
     2

   CC/VG

     10
   10-Sep


   4.8/2.4
     60
     3.5
   4
  5–7
 6-Apr
 10-Jun
1.00E+06
  10–20

   6



  65


  12
 0.051
 1T1C
  3D
 0.016

 0.069
  4.25
  0.7


   30
>1.0E16

10 Years

   16
   16
 0.0041
   35
   20
 0.005

  0.6
   70
  >10
 >3e16

  >10

   9

   4


  5.5
  340


  450
   4


   85


  112
   7
  900
   13
   35
2.70E+07

  73

   2.88
    9
   >10
1.00E+15
INDEX LINK   Table PIDS6          Reliability Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table PIDS7                                                   Reliability Technology Requirements—Near and Long-term Year
             Year of Production                                              2007      2008      2009      2010      2011
             Early failures (ppm) (First 4000 operating hours) [1]         50–2000   50–2000   50–2000   50–2000   50–2000
             Long term reliability (FITS = failures in 1E9 hours) [2]      50–2000   50–2000   50–2000   50–2000   50–2000
             SRAM Soft error rate (FITs/MBit)                             1000-2000 1000-2000 1000-2000 1000-2000 1000-2000
             Relative failure rate per transistor (normalized to 2007
             value) [3]                                                       1       0.83      0.71      0.66       0.57
             Relative failure rate per m of interconnect (normalized to
             2007 value) [4]                                                  1        0.5       0.5       0.5       0.25

                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                           Interim solutions are known    
                               Manufacturable solutions are NOT known
—Near and Long-term Years
              2012      2013      2014      2015      2016      2017      2018      2019      2020      2021
            50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000
            50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000   50–2000
           1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000

             0.51      0.46       0.4      0.37      0.31      0.29      0.26      0.23       0.2      0.18

             0.25      0.25      0.12      0.12      0.12      0.06      0.06      0.06       0.03     0.03
   2022
 50–2000
 50–2000
1000-2000

  0.16

  0.03
INDEX LINK Tables ERD 1-10 are text tables. For ease of editing, please use the Word file found online at:
           http://www.itrs.net/ITWG/word_files.html
INDEX LINK Tables ERM 1-8 are text tables. For ease of editing, please use the Word file found online at:
           http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table FEP1          Front End Processes Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table FEP2                                                        Starting Materials Technology Requirements—Near and Long-t
             Year of Production                                                          2007                   2008                     2009
             DRAM Total Chip Area (mm 2 )                                                  93                    74                       59
             DRAM Active Transistor Area (mm 2 )                                         29.6                   23.1                     18.2
             MPU High-Performance Total Chip Area(mm 2 )                                  310                   246                       195
             MPU High-Performance Active Transistor Area(mm 2 )                          31.7                   25.1                      20
             General Characteristics * (99% Chip Yield)
             Maximum Substrate Diameter (mm)—High-volume
             Production (>20K wafer starts per month)**                                  300                    300                      300
             Edge exclusion (mm)                                                 2                       2                        2

             Front surface particle size (nm), latex sphere equivalent (A)       65                    65                      65
               Particles (cm–2)                                                 ≤0.32                  ≤0.30                    ≤0.30
               Particles (#/wf)                                                 ≤218                   ≤209                     ≤205
             Site flatness (nm), SFQR 26mm x 8 mm Site Size                      ≤65                    ≤57                      ≤50
             Nanotopography, p-v, 2 mm dia. analysis area (I)                    ≤16                    ≤14                      ≤13
             Epitaxial Wafer * (99% Chip Yield)
             Large structural epi defects (DRAM) (cm–2) (B)                    ≤0.011                 ≤ 0.014                  ≤ 0.017
             Large structural epi defects (MPU) (cm–2) (B)                     ≤0.003                 ≤ 0.004                  ≤ 0.005
             Small structural epi defects (DRAM) (cm-2) (C)                    ≤0.022                 ≤ 0.027                  ≤ 0.034
             Small structural epi defects (MPU) (cm-2) (C)                     ≤0.006                 ≤0.008                   ≤ 0.010
             Silicon-On-Insulator Wafer* (99% Chip Yield)
             Edge exclusion (mm) ***                                             2                       2                        2
             Starting silicon layer thickness
             (Partially Depleted) (tolerance ± 5%, 3s) (nm) (D)                48-83                   44-76                    40-60
             Starting silicon layer thickness
             (Fully Depleted) (tolerance ± 5%, 3s) (nm) (E)
             Buried oxide (BOX) thickness
             (Fully Depleted) (tolerance ± 5%, 3s) (nm) (F)
             DLASOI, Large area SOI wafer defects (DRAM) (cm–2) (G)            ≤ 0.011                ≤ 0.014                  ≤ 0.017
             DLASOI, Large area SOI wafer defects (MPU) (cm–2) (G)             ≤ 0.003                ≤ 0.004                  ≤ 0.005
             DSASOI, Small area SOI wafer defects (DRAM) (cm–2) (H)            ≤ 0.170                ≤ 0.218                  ≤ 0.276
             DSASOI, Small area SOI wafer defects (MPU) (cm–2) (H)             ≤ 0.159                ≤ 0.200                  ≤ 0.252



                                                                                  Meaning and Color Coding of Left Box           Meaning and Color Codi
                                                                              Technology Requirements Value and Supplier         Metrology Readiness Ca
                                                                             Manufacturable solutions exist, and are being   Manufacturable solutions exist,
                                                                             Manufacturable solutions are known              Manufacturable solutions are kn
                                                                             Interim solutions are known                     Interim solutions are known
                                                                             Manufacturable solutions are NOT known          Manufacturable solutions are N
rements—Near and Long-term Years
           2009                       2010                  2011             2012             2013             2014
            59                          93                   74                59               93              74
           18.2                       29.1                  23.1             18.3             29.1             23.1
            195                        310                   246              195              310              246
            20                        31.7                  25.1               20             31.7             25.1


            300                       300                   300              450              450              450
                               2                    2                1.5              1.5              1.5

                              65                  65              45              45              45
                             ≤ 0.15               ≤ 0.15           ≤ 0.32           ≤ 0.16           ≤ 0.16
                             ≤ 105                ≤ 105            ≤ 498            ≤ 249            ≤ 249
                              ≤45                  ≤40              ≤36              ≤32              ≤28
                              ≤11                  ≤10               ≤9               ≤8               ≤7

                            ≤ 0.011               ≤ 0.014          ≤ 0.017          ≤ 0.011          ≤ 0.014
                            ≤ 0.003               ≤ 0.004          ≤ 0.005          ≤ 0.003          ≤ 0.004
                            ≤ 0.022               ≤ 0.027          ≤ 0.034          ≤ 0.022          ≤ 0.027
                            ≤ 0.006               ≤ 0.008          ≤ 0.010          ≤ 0.006          ≤ 0.008

                               2                    2                1.5              1.5              1.5

                             37-55                34-50            31-45            29-42            27-38

                             15-28                14-17            14-16            13-16            13-14

                             26-44                 24-40            22-36            18-32            16-28
                            ≤ 0.011               ≤ 0.014          ≤ 0.017          ≤ 0.011          ≤ 0.014
                            ≤ 0.003               ≤ 0.004          ≤ 0.005          ≤ 0.003          ≤ 0.004
                            ≤ 0.173               ≤ 0.218          ≤ 0.274          ≤ 0.173          ≤ 0.218
                            ≤ 0.159               ≤ 0.200          ≤ 0.252          ≤ 0.159          ≤ 0.200



      Meaning and Color Coding of Right Box
      Metrology Readiness Capability by Color
  Manufacturable solutions exist, and are being
  Manufacturable solutions are known
  Interim solutions are known
  Manufacturable solutions are NOT known
2014             2015             2016             2017             2018             2019
 74                59              93                74               59              93
23.1             18.3             29.1             23.1             18.3             29.1
 246              195              310              246              195              310
25.1               20             31.7             25.1               20             31.7


450              450              450              450              450              450
         1.5              1.5              1.5              1.5              1.5

        32              32              32              ³22              ³22
       ≤ 0.31           ≤ 0.16           ≤ 0.16           ≤ 0.33           ≤ 0.17
       ≤ 492            ≤ 246            ≤ 246            ≤ 521            ≤ 260
        ≤25              ≤23              ≤20              ≤18              ≤16
         ≤6               ≤6               ≤5               ≤4               ≤4

       ≤ 0.017          ≤ 0.011          ≤ 0.014          ≤ 0.017          ≤ 0.011
       ≤ 0.005          ≤ 0.003          ≤ 0.004          ≤ 0.005          ≤ 0.003
       ≤ 0.034          ≤ 0.022          ≤ 0.027          ≤ 0.034          ≤ 0.022
       ≤ 0.010          ≤ 0.006          ≤ 0.008          ≤ 0.010          ≤ 0.006

         1.5              1.5              1.5              1.5              1.5

       25-35            23-32            22-30            21-28            19-26

       14-Dec           13-Dec           13-Dec           13-Dec           12-Nov

        16-26            14-22           20-Dec           18-Oct           16-Oct
       ≤ 0.017          ≤ 0.011          ≤ 0.014          ≤ 0.017          ≤ 0.011
       ≤ 0.005          ≤ 0.003          ≤ 0.004          ≤ 0.005          ≤ 0.003
       ≤ 0.274          ≤ 0.173          ≤ 0.218          ≤ 0.274          ≤ 0.173
       ≤ 0.252          ≤ 0.159          ≤ 0.200          ≤ 0.252          ≤ 0.159
2019             2020             2021             2022
 93                74              59                93
29.1             23.1             18.3             29.1
 310              246              195              310
31.7             25.1              20              31.7


450              450              450              450
         1.5              1.5              1.5

        ³22              ³16              ³16
       ≤ 0.17           ≤ 0.31           ≤ 0.16
       ≤ 260            ≤ 492            ≤ 246
        ≤14              ≤13              ≤11
         ≤4               ≤3               ≤3

       ≤ 0.014          ≤ 0.017          ≤ 0.011
       ≤ 0.004          ≤ 0.005          ≤ 0.003
       ≤ 0.027          ≤ 0.034          ≤ 0.022
       ≤ 0.008          ≤ 0.010          ≤ 0.006

         1.5              1.5              1.5

       18-24            18-23            17-21

       12-Nov           12-Nov           12-Nov

       14-Aug           12-Aug           12-Jun
       ≤ 0.014          ≤ 0.017          ≤ 0.011
       ≤ 0.004          ≤ 0.005          ≤ 0.003
       ≤ 0.218          ≤ 0.274          ≤ 0.173
       ≤ 0.200          ≤ 0.252          ≤ 0.159
INDEX LINK   Table FEP3                                                      Front End Surface Preparation Technology Requirements—Ne
             Year of Production                                                  2007   2008    2009     2010     2011
             Wafer diameter (mm)                                                  300    300     300      300      300
             Wafer edge exclusion (mm)                                             2      2       2        2        2
             Front surface particles
             Killer defect density, DpRp (#/cm2) [A]                             0.11   0.14    0.17     0.11      0.14
             Critical particle diameter, dc (nm) [B]                             32.5   28.3     25      22.5       20
             Critical particle count, Dpw (#/wafer) [C]                          75.4   75.4    75.4     74.7      74.7
             Back surface particle diameter: lithography and measurement
             tools (µm) [D]                                                      0.12   0.12     0.1      0.1      0.1
             Back surface particles: lithography and measurement tools
             (#/wafer) [E]                                                       200    200     200      200       200
             Back surface particle diameter: all other tools (µm) [D]            0.16   0.16    0.14     0.14      0.14
             Back surface particles: all other tools (#/wafer) [E]               200    200     200      200       200
             Critical GOI surface metals (1010 atoms/cm2) [F]                    0.5    0.5     0.5      0.5       0.5
             Critical other surface metals (1010 atoms/cm2) [F]                   1      1       1        1         1
             Mobile ions (1010 atoms/cm2) [G]                                     2      2       2        2         2
             Surface carbon (1013 atoms/cm2) [H]                                 1.2     1      0.9      0.9       0.9
             Surface oxygen (1013 atoms/cm2) [I]                                 0.1    0.1     0.1      0.1       0.1
             Surface roughness LVGX, RMS (Å) [J]                                  4      4       4        2         2
             Silicon and oxide loss (Å) on polysilicon blanket test wafers
             per LDD clean step—DRAM [K]                                         1.5    1.2     1.2       0.9     0.9

             Silicon and oxide loss (Å) on polysilicon blanket test wafers
             per LDD clean step—Microprocessor/SoC/Analog [L]                    0.5    0.4     0.4       0.3     0.3

                  Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                             Interim solutions are known     
                                 Manufacturable solutions are NOT known
nology Requirements—Near and Long-term Years
              2012     2013     2014     2015    2016    2017    2018    2019    2020    2021
               450      450      450      450     450     450     450     450     450     450
               1.5      1.5      1.5      1.5     1.5     1.5     1.5     1.5     1.5     1.5

              0.17      0.11     0.14     0.17    0.11    0.14    0.17    0.11    0.14    0.17
              17.9      15.9     14.2     12.6    11.3     10     8.9      8      7.1     6.3
             270.6     170.5    170.5    170.5   170.5   170.5   170.5   170.5   170.5   170.5

              0.1       NA       NA       NA      NA      NA      NA      NA      NA      NA

              200       NA       NA       NA      NA      NA      NA      NA      NA      NA
              0.14      NA       NA       NA      NA      NA      NA      NA      NA      NA
              200       NA       NA       NA      NA      NA      NA      NA      NA      NA
              0.5       0.5      0.5      0.5     0.5     0.5     0.5     0.5     0.5     0.5
               1         1        1        1       1       1       1       1       1       1
               2         2        2        2       2       2       2       2       2       2
              0.9       0.9      0.9      0.9     0.9     0.9     0.9     0.9     0.9     0.9
              0.1       0.1      0.1      0.1     0.1     0.1     0.1     0.1     0.1     0.1
               2         2        2        2       2       2       2       2       2       2

              0.9     0.6     0.6     0.6    0.6    0.6    0.6    0.6    0.6    0.6


              0.3     0.2     0.2     0.2    0.2    0.2    0.2    0.2    0.2    0.2
2022    Driver
 450    D ½, M
 1.5    D ½, M

 0.11    D½
 5.6     D½
170.5    D½

 NA      D½

 NA     D½
 NA     D½
 NA     D½
 0.5    MPU
  1     MPU
  2     MPU
 0.9
 0.1    D ½, M
  2

0.6      M


0.2      M
INDEX LINK   Table FEP4a                                                    Thermal, Thin Film, Doping and Etching Technology Requireme
             Grey cells indicate the requirements projected only for intermediate, or long-term years. Near-term line items are not included.
             Year of Production                                                   2007          2008          2009           2010          2011
             Equivalent physical oxide thickness for bulk MPU/ASIC T ox
             (nm) for 1E20-doped poly-Si [A, A1, A2]                                1
             Equivalent physical oxide thickness for bulk MPU/ASIC T ox
             (nm) for 1.5E20-doped poly-Si [A, A1, A2]                             1.1           0.5
             Equivalent physical oxide thickness for bulk MPU/ASIC T ox
             (nm) for 3E20-doped poly-Si [A, A1, A2]                               1.2           0.71          0.54          0.41
             Equivalent physical oxide thickness for bulk MPU/ASIC T ox
             (nm) for metal gate [A, A1, A2]                                                     0.9           0.75          0.65          0.55
             Gate dielectric leakage at 100 °C (A/cm 2 ) bulk high-
             performance [B, B1, B2]                                           8.00E+02 8.70E+02 1.00E+03 1.10E+03 1.30E+03
             Metal gate work function for bulk MPU/ASIC |E c,v – f m |
             (eV) [C]                                                                           <0.2          <0.2           <0.2          <0.2
             Channel doping concentration (cm ‑3 ), for bulk design [D]        4.80E+18 3.70E+18 4.10E+18 5.40E+18 6.60E+18
             Bulk/FDSOI/DG – Long channel electron mobility
             enhancement factor due to strain for MPU/ASIC [E]                     1.8           1.8           1.8            1.8           1.8
             Drain extension X j (nm) for bulk MPU/ASIC [F]                       12.5            11            10             9             8
             Maximum allowable parasitic series resistance for bulk NMOS
             MPU/ASIC × width (( W-m m) from PIDS [G]                              200           200           200            180           180
             Maximum drain extension sheet resistance for bulk MPU/ASIC
             (NMOS) ( W /sq) [G]                                                   650           740           810            900          1015
             Extension lateral abruptness for bulk MPU/ASIC (nm/decade)
             [H]                                                                   2.5           2.3            2             1.8           1.6
             Contact X j (nm) for bulk MPU/ASIC [I]                               27.5           25.3           22           19.8          17.6
             Allowable junction leakage for bulk MPU/ASIC ( m A/ m m)             0.34           0.71          0.7           0.64          0.74
             Sidewall spacer thickness (nm) for bulk MPU/ASIC [J]                 27.5           25.3           22           19.8          17.6

             Maximum silicon consumption for bulk MPU/ASIC (nm) [K]             13.8          12.7          11           9.9           8.8
             Silicide thickness for bulk MPU/ASIC (nm) [L]                       17            15           13            12            11
             Contact silicide sheet R s for bulk MPU/ASIC ( W /sq) [M]          9.6           10.5         12.1          13.5          15.1
             Contact maximum resistivity for bulk MPU/ASIC (W -cm 2 )
             [N]                                                             1.20E-07      1.00E-07      9.20E-08      7.00E-08     6.20E-08
             STI depth bulk (nm) [O]                                            353           339           335           331          323
             Trench width at top (nm) [P]                                        65            57            50            45           40
             Trench sidewall angle (degrees) [Q}                               >87.4         >87.6         >87.9         >88.1        >88.2
             Trench fill aspect ratio – bulk [R]                                 6            6.5           7.2           7.9          8.6
             Equivalent physical oxide thickness for FDSOI MPU/ASIC T ox
             (nm) for metal gate [A, A1, A2]                                                                              0.7           0.6
             Gate dielectric leakage at 100°C (A/cm 2 ) FDSOI high-
             performance [B, B1, B2]                                                                                  1.10E+03      1.30E+03
             Metal gate work function for FDSOI MPU/ASIC f m – E i
             (eV) NMOS/PMOS [S]
             Saturation velocity enhancement factor MPU/ASIC [T]                 1            1.1           1.1           1.1           1*
             Si thickness FDSOI (nm) from PIDS [T]                                                                        5.5           5.2
             Maximum allowable parasitic series resistance for FDSOI
             NMOS MPU/ASIC × width (( W-m m) [G]                                                                         180           180
             Maximum drain extension sheet resistance for FDSOI
             MPU/ASIC (NMOS) ( W /sq) [G]                                                                                730           770
             Spacer thickness, FDSOI elevated contact [J]                                                                9.9           8.8
             Thickness of FDSOI elevated junction (nm) [U}                                                                18            16
             Maximum silicon consumption for FDSOI MPU/ASIC (nm)
             [K]                                                                                                          18            16
             Silicide thickness for FDSOI MPU/ASIC (nm) [L]                                                               22            19
             Contact silicide sheet R s for FDSOI MPU/ASIC ( W /sq) [M]                                                   7.4           8.3
             Contact maximum resistivity for FDSOI MPU/ASIC (W -cm 2 )
             [N]                                                                                                       7.20E-08     6.50E-08
Trench fill aspect ratio – FDSOI [V]                                                                0.6        0.6
Equivalent physical oxide thickness for multi-gate MPU/ASIC
T ox (nm) for metal gate [A, A1, A2]                                                                           0.8
Gate dielectric leakage at 100°C (nA/µm) muti-gate high-
performance [B, B1, B2]                                                                                      1.25E+03
Metal gate work function for multi-gate MPU/ASIC [S]                                                          midgap
Si thickness for multi-gate (nm) from PIDS [U]                                                                 9.5
Maximum allowable parasitic series resistance for multi-gate
NMOS MPU/ASIC × width (( W-m m) [G]                                                                            180
Maximum drain extension sheet resistance for multi-gate
MPU/ASIC (NMOS) ( W /sq) [G]                                                                                   425
Spacer thickness, multi-gate elevated contact [J]                                                              8.8
Thickness of multi-gate elevated junction (nm) [T]                                                              16
Maximum silicon consumption for multi-gate MPU/ASIC (nm)
[K]                                                                                                            16
Silicide thickness for multi-gate MPU/ASIC (nm) [L]                                                            19
Contact silicide sheet R s for multi-gate MPU/ASIC ( W /sq)
[M]                                                                                                            8.3
Contact maximum resistivity for multi-gate MPU/ASIC (W -
cm 2 ) [N]                                                                                                   6.60E-08
Physical gate length low operating power (LOP) (nm)                32         28         25         23          20
Equivalent physical oxide thickness for bulk low operating
power T ox (nm) for 1.5E20-doped poly-Si [A, A1, A2]               1.2        0.8        0.7        0.6        0.5
Equivalent physical oxide thickness for bulk low operating
power T ox (nm) for metal gate [A, A1, A2]                                    1.1         1         0.9        0.8
Gate dielectric leakage at 100°C for bulk (A/cm 2 ) LOP [B,
B1, B2]                                                          7.80E+01   8.90E+01   1.00E+02   1.10E+02   1.30E+02
Metal gate work function for bulk low operating power |E c,v –
f m | (eV) [S]                                                                <0.2       <0.2       <0.2       <0.2
Allowable junction leakage for bulk LSTP (pA/ m m)                 10          10         10         10         16
Equivalent physical oxide thickness for FDSOI low operating
power T ox (nm) for metal gate [A, A1, A2]                                                                     0.9
Gate dielectric leakage at 100°C for FDSOI (A/cm 2 ) LOP [B,
B1, B2]                                                                                                      1.30E+02

Metal gate work function for FDSOI and multi-gate LOP [S]                                                     midgap
Equivalent physical oxide thickness for multi-gate low
operating power T ox (nm) for metal gate [A, A1, A2]                                                           0.9
Gate dielectric leakage at 100°C for multi-gate (A/cm 2 ) LOP
[B, B1, B2]                                                                                                  1.30E+02
Physical gate length low standby power (LSTP) (nm)                 45         37         32         28          25
Equivalent physical oxide thickness for bulk low standby
power T ox (nm) for 1.5E20-doped poly-Si [A, A1, A2]               1.9        1.2        1.1         1         0.9
Equivalent physical oxide thickness for bulk low standby
power T ox (nm) for metal gate [A, A1, A2]                                    1.6        1.5        1.4        1.3
Gate dielectric leakage at 100°C for bulk (A/cm 2 ) LSTP [B,
B1, B2]                                                          6.70E-02   8.10E-02   9.40E-02   1.10E-01   1.20E-01

Metal gate work function for bulk LSTP |E c,v – f m | (eV) [S]                <0.2       <0.2       <0.2       <0.2
Equivalent physical oxide thickness for FDSOI low standby
power T ox (nm) for metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for FDSOI (A/cm 2 ) LSTP [B,
B1, B2]
Metal gate work function for FDSOI and multi-gate LSTP f m
– E i (eV) NMOS/PMOS [S]
Equivalent physical oxide thickness for multi-gate low standby
power T ox (nm) for metal gate [A, A1, A2]
Gate dielectric leakage at 100°C for multi-gate (A/cm 2 ) LSTP
[B, B1, B2]
Thickness control EOT (% 3 s ) [W]                                    <±4      <±4        <±4        <±4        <±4
Poly-Si or metal gate electrode thickness (approximate) (nm)
[X]                                                                   50        46        40          36         32
Gate etch bias (nm) [Y]                                               17        15        14          12         11
L gate 3 s variation (nm) [Z]                                         3        2.76       2.4        2.16       1.92
Total maximum allowable lithography 3 s (nm) [AA]                     2.6      2.39       2.08       1.87       1.66
Total maximum allowable etch 3 s (nm), including photoresist
trim and gate etch [AA]                                               1.5      1.38       1.2        1.08       0.96
Resist trim maximum allowable 3 s (nm) [AB]                           0.87     0.8        0.69       0.62       0.55
Gate etch maximum allowable 3 s (nm) [AB]                             1.22     1.13       0.98       0.88       0.78
CD bias between dense and isolated lines [AC]                                 ≤15%       ≤15%       ≤15%       ≤15%
Minimum measurable gate dielectric remaining (post gate etch
clean) [AD]                                                           >0       >0         >0         >0         >0
Profile control (side wall angle) [AE]                                90       90         90         90         90
Allowable threshold voltage variation from charge in
dielectric (mV) [AF]                                                  11       9.5        10         10         10

Allowable interfacial charge in high- k gate stack (cm -2 )[AG]              1.54E+11   1.54E+11   1.41E+11   1.62E+11
Allowable bulk charge in high- k gate stack (cm -3 ) [AH]                    5.50E+17   5.50E+17   5.42E+17   6.74E+17
Allowable bulk charge in high- k gate stack (ppm) [AH]                          25         25         24.7       30.6
Allowable critical metal impurity level in high- k dielectric
(ppm) [AI]                                                                     2.5        2.5        2.5        3.1
Allowable critical metal impurity level in high- k dielectric
(ppm) [AJ]                                                            2.2      2.5        2.5        2.5        3.1

      Manufacturable solutions exist, and are being optimized
                        Manufacturable solutions are known
                                Interim solutions are known       
                    Manufacturable solutions are NOT known
ng Technology Requirements—Near-term Years
included.
              2012      2013       2014       2015




              0.5

            1.40E+03

               <0.2
            8.40E+18

              1.8        1.8        1.8        1.8
               7

              180

              1160

              1.4
              15.4
              0.68
              15.4

              7.7
               9
              17.3

            5.60E-08
               316
                35
              >88.4
               9.5

              0.55       0.5        0.5        0.5

            1.40E+03   1.50E+03   1.80E+03   2.00E+03



              1*          1*        1*         1*
              4.5         4         3.5        3.2

              180        170        160        160

              890       1000       1150       1250
              7.7        7.2        6.1        5.5
               14        13         11         10

              14          13         11         10
              17          16         13         12
              9.5        10.2       12.1       13.3

            5.80E-08   4.80E-08   4.00E-08   3.50E-08
  0.6        0.6        0.6        0.6

  0.7        0.6        0.6        0.6

1.43E+03   1.54E+03   1.82E+03   2.00E+03
 midgap     midgap     midgap     midgap
  8.5        7.5        6.5         6

  180        170        160        160

  475        535        615        670
  7.7        7.2        6.1        5.5
   14         13         11         10

  14         13         11         10
  17         16         13         12

  9.5        10.2       12.1       13.3

6.10E-08   5.10E-08   4.20E-08   3.80E-08
   18         16         14         13

  0.5

  0.8

1.40E+02

  <0.2
   21

  0.9        0.8        0.8        0.8

1.40E+02   1.60E+02   1.80E+02   1.90E+02

 midgap     midgap     midgap     midgap


  0.9        0.9        0.8        0.8

1.40E+02   1.60E+02   1.80E+02   1.90E+02
   23         20         18         16

  0.8        0.7

  1.2        1.1

1.30E-01   1.50E-01

  <0.2       <0.2

  1.3        1.2        1.1        1.1

1.30E-01   1.50E-01   1.70E-01   1.90E-01

 ± 0.1      ± 0.1

  1.4        1.3        1.2        1.1

1.30E-01   1.50E-01   1.70E-01   1.90E-01
  <±4        <±4        <±4        <±4

   28         26         22        20
   10          8          8         7
  1.68       1.56       1.32       1.2
  1.45       1.35       1.14       1.04

  0.84       0.78       0.66       0.6
  0.48       0.45       0.38       0.35
  0.69       0.64       0.54       0.49
 ≤15%       ≤15%       ≤15%       ≤15%

  >0         >0         >0         >0
  90         90         90         90

   9          9          9         8.5

1.76E+11   1.67E+11   2.00E+11   2.00E+11
8.02E+17   7.58E+17   8.90E+17   8.90E+17
   36.5       34.4       40.5       40.5

  3.6        3.4        4.1        4.1

  3.6        3.4        4.1        4.1
INDEX LINK   Table FEP4b                                                        Thermal, Thin Film, Doping and Etching Technology Requirem
             Grey cells indicate the requirements projected only for intermediate, or long-term years. Near-term line items are not included.
             Year of Production                                                     2015          2016         2017           2018
             Bulk/FDSOI/DG – Long channel electron mobility enhancement
             factor for MPU/ASIC [E]                                                 1.8           1.8          1.8            1.8
             Equivalent physical oxide thickness for multi-gate MPU/ASIC
             T ox (nm) for metal gate [A, A1, A2]                                    0.6          0.55          0.55          0.55
             Gate dielectric leakage at 100°C (nA/µm) muti-gate High-
             performance [B, B1, B2]                                             2.00E+03 2.20E+03 2.50E+03 2.90E+03

             Metal gate work function for multi-gate MPU/ASIC [S]                 midgap        midgap        midgap         midgap
             Si thickness for multi-gate (nm) [T]                                    6            5.4           4.5            4.2
             Maximum allowable parasitic series resistance for multi-gate
             NMOS MPU/ASIC × width (( W-m m) from PIDS [G]                          160           155           150           145
             Maximum drain extension sheet resistance for multi-gate
             MPU/ASIC (NMOS) ( W /sq) [G]                                           670           745           890           960

             Spacer thickness, multi-gate elevated contact [J]                      5.5            5            4.4            3.9

             Thickness of multi-gate elevated junction (nm) [U]                     10             9              8             7

             Maximum silicon consumption for multi-gate mpu/asic (nm) [K]           10             9              8             7

             Silicide thickness for multi-gate MPU/ASIC (nm) [L]                    12             11            10             8

             Contact silicide sheet R s for multi-gate MPU/ASIC ( W /sq) [M]       13.3           14.8          16.7           19
             Contact maximum resistivity for multi-gate MPU/ASIC (W -
             cm 2 ) [N]                                                          3.80E-08      3.30E-08      2.80E-08      2.40E-08
             Physical gate length low operating power (LOP) (nm)                    13            11            10             9
             Equivalent physical oxide thickness for FDSOI low operating
             power T ox (nm) for metal gate [A, A1, A2]                             0.8           0.7
             Gate dielectric leakage at 100 °C for FDSOI (A/cm 2 ) LOP [B,
             B1, B2]                                                             1.90E+02      2.30E+02
             Metal gate work function for FDSOI and multi-gate LOP [S]            midgap        midgap        midgap         midgap
             Equivalent physical oxide thickness for multi-gate low operating
             power T ox (nm) for metal gate[A, A1, A2]                              0.8           0.8            0.7           0.7
             Gate dielectric leakage at 100°C for multi-gate (A/cm 2 ) LOP
             [B, B1, B2]                                                         1.90E+02      2.30E+02      2.50E+02      2.80E+02
             Physical gate length low standby power (LSTP) (nm)                     16            14            13            11
             Equivalent physical oxide thickness for FDSOI low standby
             power T ox (nm) for metal gate [A, A1, A2]                              1            0.9            0.8
             Gate dielectric leakage at 100°C for FDSOI (A/cm 2 ) LSTP [B,
             B1, B2]                                                             1.90E-01      2.10E-01      2.30E-01
             Metal gate work function for FDSOI and multi-gate LSTP | Ei –
             f m | (eV)| NMOS/PMOS [S]                                             ±0.1           ±0.1          ±0.1          ±0.1
             Equivalent physical oxide thickness for multi-gate low standby
             power T ox (nm) for metal gate [A, A1, A2]                             1.1           1.1             1             1
             Gate dielectric leakage at 100°C for multi-gate (A/cm 2 ) LSTP
             [B, B1, B2]                                                         1.90E-01      2.10E-01      2.30E-01       2.70E-01
             Thickness control EOT (% 3 s ) [W]                                     <±4           <±4           <±4            <±4
             Poly-Si or Metal Gate electrode thickness (approximate) (nm)
             [X]                                                                    20             18            16            14
             Gate etch bias (nm) [Y]                                                 7             6             5             5
             L gate 3 s variation (nm) [Z]                                          1.2           1.08          0.96          0.84
             Total maximum allowable lithography 3 s (nm) [AA]                     1.04           0.94          0.83          0.73
             Total maximum allowable etch 3 s (nm), including photoresist
             trim and gate etch [AA]                                               0.6            0.54          0.48          0.42
             Resist trim maximum allowable 3 s (nm) [AB]                           0.35           0.31          0.28          0.24
Gate etch maximum allowable 3 s (nm) [AB]                              0.49     0.44       0.39       0.34
CD bias between dense and isolated lines [AC]                         ≤15%     ≤15%       ≤15%       ≤15%
Minimum measurable gate dielectric remaining (post gate etch
clean) [AD]                                                            >0       >0         >0         >0
Profile control (side wall angle- degrees) [AE]                        90       90         90         90
Allowable threshold voltage variation from charge in dielectric
(mV) [AF]                                                              8.5       8          8          8

Allowable interfacial charge in high- k gate stack (cm -2 )[AG]   1.80E+11    1.90E+11   2.20E+11   1.70E+11
Allowable bulk charge in high- k gate stack (cm -3 ) [AH]         9.20E+17    1.10E+18   1.30E+18   8.60E+17
Allowable bulk charge in high- k gate stack (ppm) [AH]               41.7        48.4       61.3       39.2
Allowable critical metal impurity level in high- k dielectric
(ppm) [AI]                                                             4.2      4.8        6.1        3.9



        Manufacturable solutions exist, and are being optimized
                          Manufacturable solutions are known
                                  Interim solutions are known     
                      Manufacturable solutions are NOT known
and Etching Technology Requirements—Long-term Years
tems are not included.
                     2019     2020       2021       2022    Driver

                     1.8       1.8        1.8        1.8    MPU/ASIC
                                                            MPU/ASIC
                     0.5       0.5        0.5         0.5   Multigate
                                                            MPU/ASIC
                 3.30E+03    3.30E+03   4.00E+03   4.40E+03 Multigate
                                                            MPU/ASIC
                   midgap     midgap     midgap     midgap  Multigate
                     3.8       3.5        3.2           3   Multigate
                                                            MPU/ASIC
                    145        145        135         135   Multigate
                                                            MPU/ASIC
                    1060      1150       1250        1340   Multigate
                                                            MPU/ASIC
                     3.5       3.1        2.8         2.5   Multigate
                                                            MPU/ASIC
                     6.3       5.6         5          4.5   Multigate
                                                            MPU/ASIC
                     6.3       5.6         5          4.5   Multigate
                                                            MPU/ASIC
                     7.6       6.7         6          5.4   Multigate
                                                            MPU/ASIC
                    21.1       23.8       26.6        29.6  Multigate
                                                            MPU/ASIC
                  2.20E-08   1.90E-08   1.60E-08   1.40E-08 Multigate
                      8          7         6.3         5.6  LOP
                                                            LOP
                                                            FDSOI
                                                            LOP
                                                            FDSOI
                   midgap     midgap     midgap     midgap  LOP
                                                            LOP
                     0.7       0.7        0.6          0.6  Multigate
                                                            LOP
                 3.10E+02    3.60E+02   4.20E+02   4.20E+02 Multigate
                    10           9          8           7   LSTP
                                                            LSTP
                                                            FDSOI
                                                            LSTP
                                                            FDSOI

                    ±0.1       ±0.1       ±0.1       ±0.1   LSTP
                                                            LSTP
                     0.9       0.9        0.8         0.8   Multigate
                                                            LSTP
                  3.00E-01   3.30E-01   3.80E-01   4.30E-01 Multigate
                     <±4        <±4        <±4        <±4   MPU/ASIC

                    12.6       11.2       10          9     MPU/ASIC
                    4.7        3.4         3         3.5    MPU/ASIC
                    0.76       0.67       0.6        0.54
                    0.65       0.58       0.52       0.47   MPU/ASIC

                    0.38       0.34       0.3        0.27   MPU/ASIC
                    0.22       0.19       0.17       0.16   MPU/ASIC
  0.31       0.27       0.24       0.22   MPU/ASIC
 ≤15%       ≤15%       ≤15%       ≤15%    MPU/ASIC

  >0         >0         >0         >0     MPU/ASIC
  90         90         90         90     MPU/ASIC

  7.5        7.5         7          7     LSTP

1.80E+11   1.80E+11   1.90E+11   1.90E+11 LSTP
1.00E+18   1.00E+18   1.20E+18   1.20E+18 LSTP
   45.4       45.4       53.6       53.6  LSTP

  4.5        4.5        5.4        5.4    LSTP
INDEX LINK   Table FEP5                                            DRAM Stacked Capacitor Technology Requirements—Near and Long-te
             Year of Production                                      2007           2008            2009            2010            2011
             Cell size factor a [B]                                    6              6               6               6               6
                                                                      0.025          0.019           0.015           0.012          0.0096

             Cell size ( m m ) [C]
                            2
                                                                 =0.13x0.195      =0.11x0.17      =0.10x0.15     =0.090x0.14     =0.080x0.12

                                                                     0.00845        0.0064          0.0051          0.0041          0.0032

             Storage node size (µm 2 ) [D]                       =0.065x0.13     =0.057x0.11     =0.051x0.10     =0.045x0.090    =0.040x0.080

                                                                    Cylinder        Cylinder        Cylinder        Cylinder        Cylinder
             Capacitor structure                                 /Pedestal MIM   /Pedestal MIM   /Pedestal MIM   /Pedestal MIM   /Pedestal MIM

             t eq at 25fF (nm) [G]                                    1.15           0.9             0.8             0.6             0.5
             Dielectric constant                                       40             43              49              65              78
             SN height (µm)                                           1.4            1.3             1.9             1.6             1.5
             Cylinder factor [E]                                      1.5            1.5              1               1               1
             Roughness factor                                           1             1               1               1               1
             Total capacitor area (µm 2 )                             0.83           0.65            0.58            0.43            0.36
             Structural coefficient [F]                               33.3           34.3            38.6            36.2            37.7
             t phy . at 25fF (nm) [H]                                 11.8            10              10              10              10
             A/R of SN [I]                                            21.6            22             38.3            35.4            37.4
             A/R of SN (OUT) for cell plate deposition [I]            33.8           33.8            63.8            63.8            74.7
             HAC diameter (µm) [J]                                    0.08           0.07            0.06            0.05            0.05
             Total interlevel insulator and metal thickness
             except SN (µm) [K]                                       0.78           0.75            0.73            0.7             0.68
             HAC depth (µm) [L]                                       2.2             2              2.6             2.3             2.2
             HAC A/R                                                   28            29.3            44.1            42.5            43.5
             V capacitor (Volts)                                      1.3            1.2             1.1             1.1             1.1
             Retention time (ms) [M]                                  64             64               64              64             64
             Leak current (fA/cell) [N]                              0.76            0.7             0.64            0.64           0.64
             Leak current density (nA/cm 2 )                         91.5           107.9           111.3           148.4           178
             Deposition temperature (degree C)                       ~500           ~500            ~500            ~500            ~500
             Film anneal temperature (degree C)                      ~750           ~750            <750            <750            ~650
             Word line R s (Ohm/sq.)                                   2              2               2               2               2

       Manufacturable solutions exist, and are being optimized
                         Manufacturable solutions are known
                                Interim solutions are known      
                    Manufacturable solutions are NOT known
y Requirements—Near and Long-term Years
              2012            2013           2014           2015           2016           2017           2018           2019           2020           2021
                6               6              6              6              6              6              6              6              6              6
              0.0077          0.0061         0.0048         0.0048         0.003          0.0024         0.0019         0.0015         0.012           0.01

            =0.071x0.11    =0.064x0.96    =0.057x0.085   =0.051x0.076   =0.045x0.068   =0.040x0.060   =0.036x0.054   =0.032x0.048   =0.028x0.043   =0.026x0.039

              0.0026          0.002          0.0016         0.0013         0.001          0.0008        0.00064        0.00051         0.0004         0.0003

           =0.036x0.071    =0.032x0.064   =0.032x0.064   =0.025x0.051   =0.023x0.045   =0.020x0.040   =0.018x0.036   =0.016x0.032   =0.014x0.028   =0.013x0.026
                            Pedestal       Pedestal       Pedestal       Pedestal       Pedestal       Pedestal       Pedestal       Pedestal       Pedestal
              Cylinder
           /Pedestal MIM       MIM            MIM            MIM            MIM            MIM            MIM            MIM            MIM            MIM

               0.4             0.3            0.3            0.3            0.3            0.3            0.3           0.25            0.2           0.15
                98            130            130             98             91             78             78             70             80             91
               1.3            1.1            1.3            1.4            1.6            1.8             2             1.9            1.7            1.4
                1              1              1              1              1              1              1              1              1              1
                1              1              1              1              1              1              1              1              1              1
               0.29           0.22           0.22           0.22           0.22           0.22           0.22           0.18           0.14           0.11
               37.6           35.6           45.2           45.2           72.4           90.5          114.3          120.7          120.7          120.7
                10             10             10            7.5             7              6              6             4.5            4.1            3.5
               36.9            35            45.8           57.6           74.5           90.2          111.4          117.5          122.8          106.8
                83            93.4          160.4           144           204.8          225.4          334.2          267.6          296.7          231.3
               0.04           0.04           0.03           0.03           0.03           0.02           0.02           0.02           0.02           0.02

               0.66           0.63           0.61           0.59           0.57           0.55           0.53           0.51           0.49           0.47
                2             1.8            1.9             2             2.2            2.4            2.5            2.4            2.2            1.9
               49.7           43.8           63.1           67.7           73.6          117.7          126.8          119.5          110.5           92.9
               1.1            1.1             1             0.9            0.7            0.6            0.6            0.6            0.6            0.5
                64             64             64             64             64             64             64             64             64             64
               0.64           0.64           0.59           0.53           0.41           0.35           0.35           0.35           0.35           0.29
              222.6          296.7          269.8          242.8          188.8          161.9          161.9          194.2          242.8          269.8
              ~500           ~500           ~500           ~500           ~500           ~500           ~500           ~500           ~500           ~500
              ~650           ~650           <650           <650           <650           <650           <650           <650           <650           <650
                2               2              2              2              2              2              2              2              2              2
   2022
     6
   0.007

=0.022x0.033

   0.0002

=0.011x0.022
 Pedestal
    MIM

    0.1
    98
   1.1
    1
    1
   0.07
  120.7
   2.5
   99.4
  182.2
   0.01

   0.45
   1.5
  154.3
   0.5
    64
   0.29
  404.7
  ~500
  <650
     2
INDEX LINK   Table FEP6                                                         DRAM Trench Capacitor Technology Requirements—Near a
             Year of Production                                                     2007    2008      2009      2010
             DRAM ½ pitch ―F‖ (nm)                                                   65      57        50        45
             Cell size factor ―a‖ [A]                                                 8       8         8         8
                          2
             Cell size (µm ) [B]                                                 0.045      0.028     0.018     0.016
             Trench structure                                                   bottled    bottled   bottled   bottled
             Trench bottle circumference (nm) [C]                                 549        483       399       374
             Trench etch depth (µm) [D]                                           6.8         6        5.8       5.6
             Bottled trench depth (µm) [E]                                         6         5.3       5.1       4.9
                                   2
             Storage node size (µm ) [F]                                            3.3     2.6        2        1.8
             Trench surface area enhancement factor (HSG) [G]                       1.2      1         1         1
             Cell capacitance (fF) [H]                                               35      30        25        25
             teq at Cs (nm) [I]                                                     3.9     3.5       2.8       2.5
             Trench top opening (nm) [J]                                             98      81        70        63
             Trench etch aspect ratio [K]                                            70      74        83        89
                                                                                    Cup     Cup       Cup       Cup
             Capacitor structure                                                    SIS     MIS       MIS       MIM



                      Manufacturable solutions exist, and are being optimized
                                        Manufacturable solutions are known
                                               Interim solutions are known      
                                   Manufacturable solutions are NOT known
Technology Requirements—Near and Long-term Years
              2011      2012      2013      2014      2015      2016      2017      2018      2019      2020
               40        36        32        28        25        22        20        18        16        14
                8         8         8         8         8         8         8         8         8         8
             0.0128    0.0104    0.0082    0.0063     0.005    0.0039    0.0032    0.0026     0.002    0.0016
             bottled   bottled   bottled   bottled   bottled   bottled   bottled   bottled   bottled   bottled
              333       300       266       233        208      183       166       150        133      116
                5        4.5        4        3.7       3.4        3        2.8       2.6       2.4       2.3
               4.3       3.8       3.3       3.1       2.8       2.5       2.3       2.1       1.9       1.8
              1.4       1.1       0.9       0.7       0.6       0.5       0.4       0.3       0.3       0.2
               1         1         1         1         1         1         1         1         1         1
               25        25        25        25        25        25        25        25        25        25
               2        1.6       1.2        1        0.8       0.6       0.5       0.4       0.3       0.3
               56        50        45        39        35        31        28        25        22        20
               89        89        89        94        97        97       100       103       107       117
              Cup       Cup       Cup       Cup       Cup       Cup       Cup       Cup       Cup       Cup
              MIM       MIM       MIM       MIM       MIM       MIM       MIM       MIM       MIM       MIM
 2021      2022
  13        11
   8         8
0.0014     0.001
bottled   bottled
 108         92
  2.2       2.1
  1.7       1.6
 0.2       0.1
  1         1
  25        25
 0.3       0.2
  18        15
 121       136
 Cup       Cup
 MIM       MIM
INDEX LINK   Table FEP7                                                            FLASH Non-volatile Memory Technology Requirements
             Year of Production                                                        2007     2008      2009      2010
             NAND Flash poly ½ Pitch (nm) [A]                                           51       45        40        36
             NOR Flash –F (nm) [A]                                                      65       57        50        45
             Flash NOR tunnel oxide thickness
             (EOT-nm) [B]                                                          8.5-9.5     8.5-9.5   8.5-9.5    9-Aug

             Flash NOR tunnel dielectric material [C]                                  Oxide    Oxide     Oxide     Oxide
             Flash NAND tunnel oxide thickness (EOT-nm) [B]                         8-Jul       8-Jul      6–7       6–7
             Flash program/erase window minimum DVT SLC/MLC (V) [D]                1.5/2.4     1.5/2.4   1.5/2.4   1.5/2.4

             Flash erase/program time degradation t max /t 0 at constant V [E]          <2       <2        <2        <2
             Flash NOR interpoly dielectric thickness (EOT-nm) [F]                     13–15    13–15     13–15    6–13
             Flash NAND interpoly dielectric thickness (EOT-nm) [F]                    10–13    10–13    5–12    5–12
                                                                                                          ONO/      ONO/
             Flash NAND Interpoly Dielectric Material [G]                              ONO      ONO       High-κ    High-κ
             Flash interpoly dielectric thickness control EOT (% 3s) [H]             <±5         <±5       <±5       <±5
             Flash interpoly dielectric T max of formation t >5 ' /<5 ' (ºC) [I]   750/900     750/900   750/900   650/800
             Flash interpoly dielectric conformality on floating gate
             EOT min /EOT max [J]                                                      >0.98    >0.98     >0.98     >0.98
             Tunnel / Interpoly max leakage current (A) at 2 V for 10 years
             data retention [K]                                                    5 E-25      5 E-25    5 E-25    2.50E-25
             Flash NAND STI Filling Aspect Ratio(min-max) [L]                      6.3-7.9     6.8-8.8   7.5-9.9   8.1-10.9
             Flash NAND STI Filling Technology [M]                                 HDP/CVD     HDP/SOD   HDP/SOD   HDP/SOD
             Flash NOR STI Filling Aspect Ratio(min-max) [L]                       3.6-4.3     3.9-4.9   4.3-5.6   4.6-6.2

                        Manufacturable solutions exist, and are being optimized
                                          Manufacturable solutions are known
                                                  Interim solutions are known      
                                      Manufacturable solutions are NOT known
ory Technology Requirements
              2011       2012        2013        2014        2015        2016        2017
               32         28          25          22          20          19          18
               40         35          32          28          25          22          20

              9-Aug      9-Aug       8-Jul       7–8         7–8         7–8         7–8
                                     Ox /        Ox /        Ox /        Ox /        Ox /
              Oxide      Oxide      High-κ      High-κ      High-κ      High-κ      High-κ
                6–7       6–7         6–7         6–7         6–7         6–7         6–7
              1.5/2.4   1.5/2.4     1.5/2.4     1.5/2.4     1.5/2.4     1.5/2.4     1.5/2.4

               <2         <2         <2          <2          <2          <2          <2
             6–13     6–13       4–6         4–6         4–6         3–5         3–5
              4–6        4–6         4–6         3–5         3–5         3–5         3–5

              High-κ     High-κ     High-κ      High-κ      High-κ      High-κ      High-κ
               <±5        <±5        <±5         <±5         <±5         <±5         <±5
             650/800    650/800    600/700     600/700     600/700     600/700     600/700

              >0.98      >0.98      >0.98       >0.98       >0.98       >0.98       >0.98

             2.50E-25   2.50E-25   1.30E-25    1.30E-25    1.30E-25    6.00E-26    6.00E-26
              9-12.3     10-14.1   11.5-16.4   12.4-17.9   12.9-18.8   13.5-19.8   14.2-21.0
               SOD        SOD        SOD         SOD         SOD         SOD         SOD
              5.0-7.0   5.4-7.8     5.8-8.7    6.5-10.0    7.3-11.6    7.8-12.7    8.1-13.4
INDEX LINK   Table FEP8                                                                       Phase Change Memory (PCM) Technology Requirem
             Grey cells indicate the requirements projected for years before it reaches volume production.
             Year of Production                                                                    2007          2008       2009       2010
             PCM ½ Pitch (nm) (contacted)                                                        65            57         50         45
             Phase change material min. conformality (%) [A]                                     30            60         70         70

             PCRAM phase change material minimum operating temperature (°C) [B]                 85            100        100        100

             Heater max resistivity change during reset cycle and after 1E12 cycles (%)          5              5          5          2
             Maximum Reset Current Density (A/ m m 2 )                                        0.3-0.8        0.3-0.8    0.3-0.8    0.4-1.0



                                 Manufacturable solutions exist, and are being optimized
                                                   Manufacturable solutions are known
                                                           Interim solutions are known     
                                               Manufacturable solutions are NOT known
CM) Technology Requirements—Near and Long-term Years

                 2011       2012       2013       2014       2015       2016       2017       2018       2019       2020
               40         35         32         28         25         22         20         18         16         14
               90         90         90         90         90         90         90         90         90         90

              125        125        125        125        125        125        125        125        125        125

                2          2          1          1          1          1          1          1          1          1
             0.4-1.0    0.4-1.0    0.5-1.3    0.5-1.3    0.5-1.3    0.5-1.3    0.5-1.3    0.5-1.3    0.5-1.3    0.5-1.3
    2021       2022
  12         10
  90         90

 125        125

   1          1
0.5-1.3    0,5-1.3
INDEX LINK   Table FEP9                                                       FeRAM Technology Requirements—Near and Long-term Year
             Year of Production                                                   2007     2008       2009       2010
             FeRAM technology – F (nm) [A]                                         180      180        180        150
             FeRAM cell size – area factor a
             in multiples of F2 [B]                                                22       22         22         20
                                  2
             FeRAM cell size ( µm ) [C]                                           0.713    0.713      0.713       0.45
             FeRAM cell structure [D]                                             2T2C     1T1C       1T1C       1T1C
             FeRAM capacitor structure [E]                                        stack    stack      stack      stack
                                             2
             FeRAM capacitor footprint (µm ) [F]                                  0.33      0.33       0.33      0.199
                                                 2
             FeRAM capacitor active area (µm ) [G]                                0.33      0.33       0.33      0.199
             FeRAM cap active area/footprint ratio                                  1        1          1          1
             Ferro capacitor voltage (V) [I]                                       1.5      1.5        1.5        1.2
                                                              2
             FeRAM minimum switching charge density (µC/cm ) [J]                  13.5      13.5       13.5       19.9
             FeRAM endurance (read/write cycles) [K]                          1.00E+14    1.00E+14   1.00E+14   1.00E+14
             FeRAM nonvolatile data retention
             (years) [L]                                                      10 Years    10 Years   10 Years   10 Years

                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                              Interim solutions are known     
                                  Manufacturable solutions are NOT known
rements—Near and Long-term Years
             2011       2012       2013       2014       2015       2016       2017       2018       2019       2020
              150        150        130        130        130        90         90         90         65         65

              20         20         16         16         16         14         14         14         12         12
              0.45       0.45       0.27       0.27       0.27      0.113      0.113      0.113      0.051      0.051
             1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C       1T1C
             stack      stack      stack      stack      stack       3D         3D         3D         3D         3D
             0.199      0.199      0.106      0.106      0.106      0.041      0.041      0.041      0.016      0.016

             0.199      0.199      0.106      0.106      0.106       0.1        0.1        0.1       0.069      0.069
               1          1          1          1          1         2.46       2.46       2.46       4.25       4.25
              1.2        1.2        1.2        1.2        1.2         1          1          1         0.7        0.7
              19.9       19.9       34         34         34         30         30         30         30         30
            1.00E+14   1.00E+14   1.00E+15   1.00E+15   1.00E+15   >1.0E16    >1.0E16    >1.0E16    >1.0E16    >1.0E16

            10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years   10 Years
 2021       2022
  65         65

  12         12
 0.051      0.051
 1T1C       1T1C
  3D         3D
 0.016      0.016

 0.069      0.069
  4.25       4.25
  0.7        0.7
  30         30
>1.0E16    >1.0E16

10 Years   10 Years
INDEX LINK   Table LITH1        Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection L

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
d Overlay with Optical Projection Lithography
INDEX LINK   Table LITH2        Lithography Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table LITH3                                                        Lithography Technology Requirements—Near and Long-term
             Year of Production                                                     2007   2008    2009     2010
             DRAM and Flash
             DRAM ½ pitch (nm)                                                      65      57     50       45
             Flash ½ pitch (nm) (un-contacted poly)                                 54      45     40       36
             Contact in resist (nm)                                                 72      62     55       50
             Contact after etch (nm)                                                65      57     50       45
             Overlay [A] (3 sigma) (nm)                                             13     11.3    10        9
             CD control (3 sigma) (nm) [B]                                          5.6    4.7     4.2      3.7
             MPU
             MPU/ASIC Metal 1 (M1) ½ pitch (nm)                                     68     59      52       45
             MPU gate in resist (nm)                                                42     38      34       30
             MPU physical gate length (nm) *                                        25     23      20       18
             Contact in resist (nm)                                                 84     73      64       56
             Contact after etch (nm)                                                77     67      58       51
             Gate CD control (3 sigma) (nm) [B] **                                  2.6    2.3     2.1      1.9
             Chip size (mm 2 )
             Maximum exposure field height (mm)                                      26     26      26       26
             Maximum exposure field length (mm)                                      33     33      33       33
             Maximum field area printed by exposure tool (mm 2 )                    858    858     858      858
             Wafer site flatness at exposure step (nm) [C]                           63     54      50       45
             Number of mask levels MPU                                               33     35      35       35
             Number of mask levels DRAM                                              24     24      24       26
             Wafer size (diameter, mm)                                              300    300     300      300

             NA required for Flash (single exposure)                                1.01   1.2     1.35     1.52
             NA required for logic (single exposure)                                0.91   1.04    1.2      1.38
             NA required for double exposure (Flash)                                0.72   0.86    0.96     1.08
             NA required for double exposure (logic)                                0.62   0.72    0.82     0.95

                      Manufacturable solutions exist, and are being optimized
                                        Manufacturable solutions are known
                                               Interim solutions are known      
                                   Manufacturable solutions are NOT known
equirements—Near and Long-term Years
             2011     2012     2013    2014   2015   2016   2017   2018   2019   2020

              40       36       32     28     25     23     20     18     16     14
              32       28       25     23     20     18     16     14     13     11
              44       39       35     31     28     25     22     20     18     16
              40       36       32     28     25     23     20     18     16     14
               8       7.1      6.4    5.7    5.1    4.5     4     3.6    3.2    2.8
              3.3      2.9      2.6    2.3    2.1    1.9    1.7    1.5    1.3    1.2

              40       36       32     28      25    23     20     18     16     14
              27       24       21     19      17    15     13     12     11      9
              16       14       13     11      10     9      8      7      6      6
              50       44       39     35      31    28     25     22     20     18
              45       40       36     32      28    25     23     20     18     16
              1.7      1.5      1.3    1.2      1    0.9    0.8    0.7    0.7    0.6

               26       26       26     26     26     26     26     26     26     26
               33       33       33     33     33     33     33     33     33     33
              858      858      858    858    858    858    858    858    858    858
               40       32       29     22     17
               35       35       35     37     37     39     39     39     39     39
               26       26       26     26     26     26     26     26     26     26
              300      450      450    450    450    450    450    450    450    450

              1.7      1.91
              1.54     1.73     1.94
              1.22     1.36     1.53   1.72   1.93
              1.06     1.19     1.34   1.5    1.68
2021   2022

13     11
10      9
14     12
13     11
2.5    2.3
 1     0.9

13     11
 8      8
 5      4
16     14
14     13
0.5    0.5

 26     26
 33     33
858    858

 39     39
 26     26
450    450
INDEX LINK   Table LITH4a and b                                                   Resist Requirements—Near and Long-term Years
             Year of Production                                                       2007    2008     2009     2010
             MPU gate in resist length (nm)                                            42      38       34       30
             Resist Characteristics *
             Resist meets requirements for gate resolution and gate CD
             control (nm, 3 sigma) **†                                               2.6        2.3      2.1      1.9
             Resist thickness (nm, single layer) ***                              105-190     90-160   80-145   70-130
             PEB temperature sensitivity (nm/C)                                     1.75        1.5      1.5     1.5
             Backside particle density (particles/cm 2 )                            0.28       0.28     0.28     0.28
             Back surface particle diameter: lithography and measurement
             tools (nm)                                                               120      120      100      100
             Defects in spin-coated resist films (#/cm 2 ) †                          0.01     0.01     0.01     0.01
             Minimum defect size in spin-coated resist films (nm)                      40       35       30       30
             Defects in patterned resist films, gates, contacts, etc. (#/cm 2 )       0.04     0.03     0.03     0.03
             Minimum defect size in patterned resist (nm)                              40       35       30       30
             Low frequency line width roughness: (nm, 3 sigma) <8% of CD
             *****                                                                     3.4      3       2.7      2.4
             Defects in spin-coated resist films for double patterning
                   2
             (#/cm )                                                                  0.005   0.005    0.005    0.005
                                                                      2
             Backside particle density for double patterning (#/cm )                  0.14     0.14     0.14     0.14


                       Manufacturable solutions exist, and are being optimized
                                         Manufacturable solutions are known
                                                Interim solutions are known       
                                    Manufacturable solutions are NOT known
r and Long-term Years
              2011      2012     2013    2014    2015    2016    2017    2018    2019    2020
               27        24       21      19      17      15      13      12      11       9



               1.7        1.5      1.3     1.2      1      0.9     0.8     0.7     0.7     0.6
             60-115     55-100   50-90   45-80   40-75   35-65   30-60   25-50   25-45   20-40
              1.5         1.5      1       1       1       1       1        1      11      11
              0.28       0.28     0.28    0.28    0.28    0.28    0.28    0.28    0.28    0.28

              100        100      75      75      75      50      50      50      50      50
              0.01       0.01    0.01    0.01    0.01    0.01    0.01    0.01    0.01    0.01
               20         20      20      20      10      10      10      10      10      10
              0.02       0.02    0.02    0.02    0.01    0.01    0.01    0.01    0.01    0.01
               20         20      20      20      10      10      10      10      10      10

               2.1       1.9      1.7     1.5     1.3     1.2     1.1     1       0.8     0.8


              0.005     0.005    0.005   0.005   0.005   0.005   0.005   0.005   0.005   0.005

              0.14       0.14    0.14    0.14    0.14    0.14    0.14    0.14    0.14    0.14
2021    2022
  8       8



 0.5     0.5
20-40   15-35

0.28    0.28

 50      50
0.01    0.01
 10      10
0.01    0.01
 10      10

 0.7     0.6


0.005   0.005

0.14    0.14
INDEX LINK   Table LITH4c                                  Resist Sensitivities
                            Exposure Technology                  Sensitivity
                                                                               2
             248 nm                                           10–50 mJ/ cm
                                                                               2
             193 nm                                           20–50 mJ/ cm
                                                                               2
             Extreme Ultraviolet at 13.5 nm                    5–30 mJ/ cm
                                                                               2
             High Voltage Electron Beam (50–100 kV) ****       5–30 µC/ cm
                                                                               2
             Low Voltage Electron Beam (1–2 kV) ****          0.2–30 µC/ cm
             **** Linked with resolution
INDEX LINK   Table LITH5a and b                                               Optical Mask Requirements—Near and Long-term Years
             Year of Production                                                   2007   2008    2009     2010
             MPU gate in resist (nm)                                               42     38      34       30
             Gate CD control (3 sigma) (nm) [ A ]                                  2.6    2.3     2.1      1.9
             Overlay (3 sigma) (nm)                                                13     11      10        9
             Contact in resist (nm)                                                84     73      64       56
             Mask magnification [B]                                                 4      4       4        4
             Mask nominal image size (nm) [C]                                      170    151     135      120
             Mask minimum primary feature size [D]                                 119    106      94       84
             Mask sub-resolution feature size (nm) opaque [E]                       85     76      67       60
             Image placement (nm, multipoint) [F]                                  7.8    6.8      6       5.4
             CD uniformity allocation to mask (assumption)                         0.4    0.4     0.4      0.4

             MEEF isolated lines, binary or attenuated phase shift mask [G]       1.6    1.8      2       2.2
             CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary
             or attenuated phase shift mask [H] *                                 2.6    2.1     1.7      1.3

             MEEF dense lines, binary or attenuated phase shift mask [G]          2.2    2.2     2.2      2.2
             CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch),
             binary or attenuated phase shift mask [J]                             4     3.4      3       2.7
             MEEF contacts [G]                                                    3.5     4       4        4
             CD uniformity (nm, 3 sigma), contact/vias [K] *                      2.5    1.9     1.7      1.5
             Linearity (nm) [L]                                                   10.4   9.1      8       7.2
             CD mean to target (nm) [M]                                           5.2    4.5      4       3.6
             Defect size (nm) [N] *                                                52     45      40       36
             Blank flatness (nm, peak-valley) [O]                                 250    218     192      173
             Pellicle thickness uniformity [P]                                     5     4.6     4.2      3.8
             Data volume (GB) [Q]                                                 413    520     655      825
             Mask design grid (nm) [R]                                             2      2       2        1
             Attenuated PSM transmission mean deviation from target (± %
             of target) [S]                                                        4      4       4        4
             Attenuated PSM transmission uniformity (±% of target) [T]             4      4       4        4
             Attenuated PSM phase mean deviation from 180º (± degree)
             [U]                                                                   3      3       3        3
             Alternating PSM phase mean deviation from nominal phase
             angle target (± degree) [T]                                          1.5     1       1        1
             Alternating PSM phase uniformity (± degree) [U]                       1      1       1        1
             Image placement (nm, multipoint) for double patterning of
             independent layers [V]                                               5.5    4.8     4.2      3.8
             Difference in CD Mean-to-target for two masks used as a
             double patterning set (nm) [W]                                       2.6    2.3      2       1.8
             Double exposure: image placement for each mask used for
             exposing mutually dependent layers (nm) [X]                          1.9    1.6     1.4      1.2
             Double exposure: mask CD uniformity for each mask used for
             exposing mutually dependent layers (nm) [Y]                          1.9    1.6     1.4      1.2
             Double exposure: dual space, etch bias repeatability and
             uniformity [Z]                                                       1.2     1      0.9      0.8
             Mask materials and substrates


                                                                                                                                   Pell




                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                              Interim solutions are known     
                                  Manufacturable solutions are NOT known
s—Near and Long-term Years
             2011     2012         2013            2014            2015            2016            2017   2018   2019   2020
              27       24           21              19              17              15              13     12     11      9
              1.7      1.5          1.3             1.2              1              0.9             0.8    0.7    0.7    0.6
               8       7.1          6.4             5.7             5.1             4.5              4     3.6    3.2    2.8
              50       44           39              35              31              28              25     22     20     18
               4        4            4               4               4               4               4      4      4      4
              107      95           85              76              67              60              54     48     42     38
               75      67           59              53              47              42              37     33     30     26
               54      48           42              38              34              30              27     24     21     19
              4.8      4.3          3.8             3.4              3              2.7             2.4    2.1    1.9    1.7
              0.4      0.4          0.4             0.4             0.4             0.4             0.4    0.4    0.4    0.4

              2.2      2.2           2.2            2.2             2.2             2.2            2.2    2.2    2.2    2.2

              1.2      1.1            1             0.9             0.8             0.7            0.6    0.5    0.5    0.4

              2.2      2.2           2.2            2.2             2.2             2.2            2.2    2.2    2.2    2.2

              2.4      2.1           1.9            1.7             1.5             1.3             1.2    1.1     1     0.9
               4        4             4              4               4               4               4      4      4      4
              1.3      1.2            1             0.9             0.8             0.7             0.7    0.6    0.5    0.5
              6.4      5.7           5.1            4.5              4              3.6             3.2    2.9    2.5    2.3
              3.2      2.9           2.5            2.3              2              1.8             1.6    1.4    1.3    1.1
              32       29            25             23              20              18              16     14     13     11
             154      137           122            109              97              86              77     69     61     54
              3.5      3.3            3             2.8             2.6             2.4             2.2     2     1.9    1.7
             1040     1310          1651           2080            2621            3302            4161   5242   6605   8321
               1        1             1              1               1               1               1      1     0.5    0.5

              4        4              4               4              4               4              4      4      4      4
              4        4              4               4              4               4              4      4      4      4

              3        3              3               3              3               3              3      3      3      3

              1        1              1               1              1               1              1      1      1      1
              1        1              1               1              1               1              1      1      1      1

              3.4      3             2.7            2.4             2.1             1.9            1.7    1.5    1.4    1.2

              1.6      1.4           1.3            1.1              1              0.9            0.8    0.7    0.6    0.6

              1.1      1             0.9            0.8             0.7             0.6            0.6    0.5    0.4    0.4

              1.1      1             0.9            0.8             0.7             0.6            0.6    0.5    0.4    0.4

              0.7      0.7           0.6            0.5             0.5             0.4            0.4    0.3    0.3    0.3

                                             Absorber/attenuator on fused silica

                             Pellicle for optical masks for exposure wavelengths down to 193 nm,
                                             including masks for 193 nm immersion.
2021    2022
  8       8
 0.5     0.5
 2.5     2.3
 16      14
  4       4
 34      30
 24      21
 17      15
 1.5     1.4
 0.4     0.4

 2.2     2.2

 0.4     0.3

 2.2     2.2

 0.8     0.7
  4       4
 0.4     0.4
  2      1.8
  1      0.9
  10      9
  48      43
 1.6     1.5
10484   13209
 0.5     0.5

 4       4
 4       4

 3       3

 1       1
 1       1

 1.1     1

 0.5     0.5

 0.3     0.3

 0.3     0.3

 0.2     0.2
INDEX LINK   Table LITH5c and d                                             EUVL Mask Requirements—Near and Long-term Years
             Year of Production                                                 2008   2009    2010    2011
             DRAM/Flash CD control (3 sigma) (nm)                                4.7    4.2     3.7     3.3
             MPU gate in resist (nm)                                             38     34      30      27
             Gate CD control (3 sigma) (nm) [A]                                  2.3    2.1     1.9     1.7
             Overlay                                                            11.3    10       9       8
             Contact after etch (nm)                                             67     58      51      45
             Generic Mask Requirements
             Mask magnification [B]                                              4       4       4       4
             Mask nominal image size (nm) [C]                                   151     135     120     107
             Mask minimum primary feature size [D]                              106      94      84      75
             Image placement (nm, multipoint) [E]                               6.8      6      5.4     4.8
             CD uniformity (nm, 3 sigma) [F]
               Isolated lines (MPU gates)                                       3.4      3      2.7     2.4
               Dense lines DRAM (half pitch)                                    6.5     5.8     5.2     4.6
               Contact/vias                                                     6.2     5.6      4      3.5
             Linearity (nm) [G]                                                 8.6     7.6     6.8     6.1
             CD mean to target (nm) [H]                                         4.5      4      3.6     3.2
             Defect size (nm) [I]                                                45      40      36      32
             Data volume (GB) [J]                                               413     520     655     825
             Mask design grid (nm) [K]                                           2       2       2       2
             EUVL-specific Mask Requirements
             Substrate defect size (nm) [L]                                   38         36      35      33
             Mean peak reflectivity                                          65%        66%     66%     66%
             Peak reflectivity uniformity (% 3 sigma absolute)              0.69%      0.58%   0.47%   0.42%

             Reflected centroid wavelength uniformity (nm 3 sigma) [M]          0.08   0.07    0.06    0.05
             Absorber sidewall angle tolerance (± degrees) [P]                   1      1      0.75    0.69
             Absorber LER (3 sigma nm) [N]                                      3.2    2.8     2.5     2.2
             Mask substrate flatness (nm peak-to-valley) [O]                     65     57      51      46

                  Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                            Interim solutions are known     
                                Manufacturable solutions are NOT known
—Near and Long-term Years
             2012     2013    2014    2015    2016    2017    2018    2019    2020    2021
              2.9      2.6     2.3     2.1     1.9     1.7     1.5     1.3     1.2      1
              24       21      19      17      15      13      12      11       9       8
              1.5      1.3     1.2      1      0.9     0.8     0.7     0.7     0.6     0.5
              7.1      6.4     5.7     5.1     4.5      4      3.6     3.2     2.8     2.5
              40       36      32      28      25      23      20      18      16      14

               4        4       4      4        4       4       4       4       4       4
              95       85      76      67      60      54      48      42      38      34
              67       59      53      47      42      37      33      30      26      24
              4.3      3.8     3.4     3       2.7     2.4     2.1     1.9     1.7     1.5

              2.1      1.9     1.7     1.5     1.3     1.2     1.1      1      0.9     0.8
              4.1      3.7     3.3     2.9     2.6     2.3      2      1.8     1.6     1.4
              3.1      2.8     2.5     2.2      2      1.3     1.2      1      0.9     0.8
              5.4      4.8     4.3     3.8     3.4      3      2.7     2.4     2.2     1.9
              2.9      2.5     2.3      2      1.8     1.6     1.4     1.3     1.1      1
              29       25      23      20      18      16      14      13      11      10
             1040     1310    1651    2080    2621    3302    4160    5241    6604    8321
               2        2       2       2       2       1       1       1       1       1

               31       30      28      27      25      23      22      20      18      17
              67%      67%     67%     67%     67%     67%     67%     67%     67%     67%
             0.37%    0.33%   0.29%   0.26%   0.23%   0.21%   0.19%   0.17%   0.15%   0.13%

              0.05    0.05    0.04    0.04    0.04    0.03    0.03    0.03    0.02    0.02
              0.62    0.5     0.5     0.5     0.5     0.5     0.5     0.5     0.5     0.5
               2      1.8     1.6     1.4     1.3     1.1      1      0.9     0.8     0.7
               41      36      32      29      26      23      20      18      16      14
2022
 0.9
  8
 0.5
 2.3
 13

  4
 30
 21
 1.4

 0.7
 1.3
 0.7
 1.7
 0.9
  9
10483
  1

  15
 67%
0.12%

0.02
0.5
0.6
 13
INDEX LINK   Table LITH5e and f                                               Imprint Template Requirements—Near and Long-term Years
             Year of Production                                                   2008    2009      2010      2011      2012
             DRAM/Flash CD control (3 sigma) (nm)                                  4.7     4.2       3.7       3.3       2.9
             MPU gate in resist (nm)                                               38      34        30        27        24
             Overlay (3 sigma) (nm)                                               11.3     10         9         8        7.1
             Gate CD control (3 sigma) (nm) [A]                                    2.3     2.1       1.9       1.7       1.5
             Contact after etch (nm)                                               67      58        51        45        40
             Generic Mask Requirements
             Magnification [B]                                                     1        1         1         1         1
             Mask nominal image size (nm) [C]                                     38       34        30        27        24
             Image placement (nm, multipoint) [D]                                 6.5      5.8       5.2       4.6       4.1
             CD Uniformity (nm, 3 sigma) [E]
               Isolated lines (MPU gates)                                         2.2      2        1.7       1.6       1.4
               Dense lines DRAM/Flash (half pitch)                                5.6     4.9       4.4       3.9       3.5
               Contact/vias                                                       6.5     5.7        5        4.4       3.9
             Linearity (nm) [F]                                                   5.7      5        4.5        4        3.6
             CD mean to target (nm) [G]                                           1.1      1        0.9       0.8       0.7
             Data volume (GB) [H]                                                 295     372       469       591       745
             Mask design grid (nm) [I]                                            0.5     0.5       0.5       0.25      0.25
             UV-NIL-specific Mask Requirements
             Defect size impacting CD (nm) x, y [J]                             4.5         4         3.6       3.2       2.8
             Defect size impacting CD (nm) z [K]                                 9          8         7.1       6.4       5.7
             Mask substrate flatness (nm peak-to-valley) [L]                    298        252       192       180       153
             Trench depth, mean (nm) [M]                                      75–119     67–104     60–90     53–81     47–72
             Etch depth uniformity (nm) [N]                                   3.8–5.9    3.4–5.2   3.0–4.5   2.7–4.0   2.4–3.6
             Trench wall angle (degrees) [O]                                     87        87.3      87.6      87.9      88.1
             Trench width roughness (nm, 3 sigma) [P]                           3.4         3         2.7       2.4       2.1
             Corner radius, bottom of feature (nm) [Q]                          6.3        5.6         5        4.5        4
             Corner radius, top of feature (nm) [R]                             1.1         1         0.9       0.8       0.7
             Trench bottom surface roughness (nm, 3 sigma) [S]                  7.6        6.7         6        5.4       4.8
             Template absorption [T]                                           <2%        <2%        <2%       <2%       <2%
             Near surface defect (nm) [U]                                        51         45        41        36        32
             Defect size, patterned template (nm) [V]                            35         30        30        20        20
             Defect density (#/cm2) [W]                                         0.03       0.03      0.03      0.01      0.01
             Dual Damascene overlay: metal/via on template (nm, 3 sigma)
             [X]                                                                  11.3     10        9         8         7.1

                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                             Interim solutions are known      
                                 Manufacturable solutions are NOT known
ar and Long-term Years
              2013        2014      2015      2016      2017      2018      2019      2020     2021      2022
               2.6         2.3       2.1       1.9       1.7       1.5       1.3       1.2       1        0.9
               21          19        17        15        13        12        11         9        8         8
               6.4         5.7       5.1       4.5        4        3.6       3.2       2.8      2.5       2.3
               1.3         1.2        1        0.9       0.8       0.7       0.7       0.6      0.5       0.5
               36          32        28        25        23        20        18        16       14        13

                1           1         1         1         1         1         1         1        1         1
               21          19        17        15        13        12        11         9        8         8
               3.7         3.3       2.9       2.6       2.3       2.1       1.8       1.6      1.5       1.3

               1.2         1.1        1        0.9       0.8       0.7       0.6      0.6       0.5       0.4
               3.1         2.8       2.5       2.2        2        1.7       1.6      1.4       1.2       1.1
               3.5         3.1       2.8       2.5       2.2        2        1.8      1.6       1.4       1.2
               3.2         2.8       2.5       2.3        2        1.8       1.6      1.4       1.3       1.1
               0.6         0.6       0.5       0.5       0.4       0.4       0.3      0.3       0.3       0.2
               938        1182      1489      1876      2364      2978      3752     4728      5957      7505
               0.25       0.25      0.25      0.25      0.25      0.25      0.25     0.125     0.125     0.125

                2.5         2.3        2        1.8       1.6       1.4       1.3       1.1        1       0.9
                5.1         4.5        4        3.6       3.2       2.8       2.5       2.3        2       1.8
               126         110        88        72        56        45        36        29        24        21
              42–64       37–57     33–51     30–45     26–41     23–36     21–32     18–29     17-26     15-22
             2.1–3.2     1.9–2.8   1.7–2.5   1.5–2.3   1.3–2.0   1.2–1.8   1.1–1.6   0.9–1.4   0.9-1.3   0.8-1.1
               88.3        88.5      88.7      88.8      88.9      89.1      89.2      89.2      89.3      89.4
                1.9         1.7       1.5       1.3       1.2       1.1        1        0.8      0.8       0.7
                3.5         3.2       2.8       2.5       2.2        2        1.8       1.6      1.3       1.1
                0.6         0.6       0.5       0.5       0.4       0.4       0.3       0.3      0.3       0.2
                4.2         3.8       3.4        3        2.7       2.4       2.1       1.9      1.5       1.2
               <2%         <2%       <2%       <2%       <2%       <2%       <2%       <2%      <2%       <2%
                29          26        23        20        18        16        14        13        11        10
                20          20        10        10        10        10        10        10        10        10
               0.01        0.01      0.01      0.01      0.01      0.01      0.01      0.01      0.01      0.01

               6.4         5.7       5.1       4.5       4         3.6       3.2       2.8      2.5       2.3
INDEX LINK   Table LITH6                                                       Maskless Technology Requirements—Near and Long-term Y
             Year of Production                                                    2008   2009    2010     2011
             DRAM/Flash CD control (3 sigma) (nm)                                   4.7    4.2     3.7      3.3
             MPU gate in resist (nm)                                                38     34      30       27
             Gate CD control (3 sigma) (nm)                                         2.3    2.1     1.9      1.7
             Overlay (3 sigma) (nm)                                                11.3    10       9        8
             Contact after etch (nm)                                                67     58      51       45
             Data Volume (GB)                                                       260    328     413      520
             Grid Size (nm)                                                         0.5    0.5     0.5     0.25



                     Manufacturable solutions exist, and are being optimized
                                       Manufacturable solutions are known
                                              Interim solutions are known      
                                  Manufacturable solutions are NOT known
uirements—Near and Long-term Years
              2012     2013     2014   2015   2016   2017   2018   2019   2020    2021
               2.9      2.6      2.3    2.1    1.9    1.7    1.5    1.3    1.2      1
               24       21       19     17     15     13     12     11      9       8
               1.5      1.3      1.2     1     0.9    0.8    0.7    0.7    0.6     0.5
               7.1      6.4      5.7    5.1    4.5     4     3.6    3.2    2.8     2.5
               40       36       32     28     25     23     20     18     16      14
               655      826     1040   1311   1651   2080   2621   3302   4161    5242
              0.25     0.25     0.25   0.25   0.25   0.25   0.25   0.25   0.125   0.125
2022
 0.9
  8
 0.5
 2.3
 13
6605
0.125
INDEX LINK   Table INTC1        Interconnect Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table INTC2                                                                 MPU Interconnect Technology Requirements—Near and
             Year of Production                                                            2007       2008       2009       2010
             Number of metal levels (includes ground planes and passive devices)            11         12         12         12
                                             2
             Total interconnect length (m/cm ) – Metal 1 and five intermediate levels,
             active wiring only [1]                                                        1439       1712       2000       2222
                              2      -3
             FITs/m length/cm × 10 excluding global levels [2]                             3.5        2.9        2.5        2.3
             Interlevel metal insulator – effective dielectric constant (κ)              2.9–3.3    2.9–3.3    2.6–2.9    2.6–2.9
             Interlevel metal insulator – bulk dielectric constant (κ)                   2.5–2.9    2.5–2.9    2.3–2.7    2.3–2.7
             Copper diffusion barrier and etch stop – bulk dielectric constant (κ)       4.0–4.5    4.0–4.5    3.5–4.0    3.5–4.0
             Metal 1 wiring pitch (nm) *                                                   136        118        104         90
             Metal 1 A/R (for Cu)                                                          1.7        1.8        1.8        1.8
             Barrier/cladding thickness (for Cu Metal 1 wiring) (nm) [3]                   4.8        4.3        3.7        3.3
             Cu thinning at minimum pitch due to erosion (nm), 10% × height, 50%
             area density, 500 µm square array                                              12         11         9          8
             Conductor effective resistivity (µΩ‑cm) Cu Metal 1 wiring including
             effect of width-dependent scattering and a conformal barrier of thickness
             specified below                                                               3.51       3.63       3.8        4.08
             Capacitance per unit length for M1 wires (pF/cm) - assumed PMD κ eff =
             4.2 [6]                                                                     1.9–2.0    1.9–2.1    1.8–2.0    1.8–2.0
             Interconnect RC delay (ps) for a 1 mm Cu Metal 1 wire, assumes no
                                                                                           558        717        848        1132

             Interconnect RC delay (ps) for 1 mm Cu Metal 1 wire, assumes width-
             dependent scattering and a conformal barrier of thickness specified below     890        1183       1465       2100
             Line length (μm) where τ = RC delay (Metal 1 wire) no scattering               34         27         25         19
             Line length (μm) where 25% of switching voltage is induced on victim
             Metal 1 wire by crosstalk [4]                                                 104         89         89         82

             Total Metal 1 resistance variability due to CD erosion and scattering (%)       28         29         30         30
             Intermediate wiring pitch (nm)                                                 136        118        104         90
             Intermediate wiring dual damascene A/R (Cu wire/via)                         1.8/1.6    1.8/1.6    1.8/1.6    1.8/1.6
             Barrier/cladding thickness (for Cu intermediate wiring) (nm) [3]               5.2        4.3        3.7        3.3
             Semi-global wire pitch (nm) (ASIC only)                                        280        236        208        180
             Cu thinning at minimum intermediate pitch due to erosion (nm), 10% ×
             height, 50% area density, 500 µm square array                                  12         11         9          8
             Conductor effective resistivity (µΩ‑cm) Cu intermediate wiring including
             effect of width-dependent scattering and a conformal barrier of thickness
             specified below                                                               3.43       3.63        3.8       4.08
             Capacitance per unit length for intermediate wires (pF/cm) [6]               1.8-2.0    1.8-2.0    1.6-1.8    1.6-1.8
                        2
             Jmax (A/cm ) – intermediate wire (at 105ºC) [7] *                           9.95E+05   1.20E+06   1.37E+06   1.72E+06
             Interconnect RC delay (ps) for a 1 mm Cu intermediate wire, assumes no
             scattering and an effective ρ of 2.2 µΩ-cm                                    475        669        764        1020
             Interconnect RC delay (ps) for 1 mm Cu intermediate wire, assumes
             width-dependent scattering and a conformal barrier of thickness specified
             below                                                                         741        1104       1320       1892

             Line length (μm) where τ = RC delay (intermediate wire) no scattering          37         28         26         20
             Line length (μm) where 25% of switching voltage is induced on victim
             intermediate wire by crosstalk [4]                                             148        125        124        115
             Minimum global wiring pitch (nm)                                               210        177        156        135
             Ratio range (global wiring pitches/intermediate wiring pitch)                1.5–14     1.5–17     1.5–20     1.5–22
             Global wiring dual damascene A/R (Cu wire/via)                               2.3/2.1    2.3/2.1    2.4/2.2    2.4/2.2
             Barrier/cladding thickness (for min. pitch Cu global wiring) (nm) [3]          5.2        4.3        3.7        3.3
             Cu thinning of maximum width global wiring due to dishing and erosion
             (nm), 10% × height, 80% area density                                          230        230        240        240
             Cu thinning global wiring due to dishing (nm), 100 µm wide feature             24         20         19         16
Conductor effective resistivity (µΩ‑cm) minimum pitch Cu global wiring
including effect of width-dependent scattering and a conformal barrier of
thickness specified below                                                    2.73         2.85          2.94       3.1
Capacitance per unit length for global wires (pF/cm) [6]                    2.0-2.3      2.0-2.3       1.8-2.0   1.8-2.0
Interconnect RC delay (ps) for a 1 mm minimum pitch Cu global wire,
                                                                                183        258          288       385
Interconnect RC delay (ps) for 1 mm Cu min pitch global wire, assumes
width-dependent scattering and a conformal barrier of thickness specified
below                                                                           227        334          385       542
Line length (μm) where τ = RC delay (global wire at minimum pitch – no
scattering)                                                                     59         46            42        32
Line length (μm) where 25% of switching voltage is induced on victim
minimum global wire by crosstalk [4]                                            127        110          116       107
                         2
Power index (W/GHz-cm ) [5]                                                 1.4-1.6      1.4-1.6       1.4-1.6   1.6-1.8


* Refer to Executive Summary for definition of M1 pitch and on-chip local clock for J max estimation

                Manufacturable solutions exist, and are being optimized
                                  Manufacturable solutions are known
                                          Interim solutions are known       
                              Manufacturable solutions are NOT known
ogy Requirements—Near and Long-term Years
              2011       2012       2013       2014       2015       2016       2017       2018       2019       2020
               12         12         13         13         13         13         14         14         14         14


              2500       2857       3125       3571       4000       4545       5000       5555       6250       7143
                2        1.8        1.6        1.4        1.3        1.1         1         0.9        0.8        0.7
             2.6–2.9   2.4–2.8    2.4–2.8    2.4–2.8    2.1–2.5    2.1–2.5    2.1–2.5    2.0–2.3    2.0–2.3    2.0–2.3
             2.3–2.7   2.1–2.5    2.1–2.5    2.1–2.5    1.9–2.3    1.9–2.3    1.9–2.3    1.7–2.1    1.7–2.1    1.7–2.1
             3.5–4.0   3.0–3.5    3.0–3.5    3.0–3.5    2.6–3.0    2.6–3.0    2.6–3.0    2.4–2.6    2.4–2.6    2.4–2.6
                80        72         64         56         50         44         40         36         32         28
               1.8       1.8        1.9        1.9        1.9         2          2          2          2          2
               2.9       2.6        2.4        2.1        1.9        1.7        1.5        1.3        1.2        1.1

               7          6          6          5          5          4          4          4          3          3


               4.3       4.53       4.83       5.2        5.58       6.01       6.33       6.7        7.34       8.19

             1.8–2.0   1.7–1.9    1.7–1.9    1.7–1.8    1.5–1.7    1.6–1.8    1.6–1.8    1.6–1.7    1.6–1.7    1.6–1.7

              1433       1695       2075       2710       3128       3899       4718       5569       7048       9206


              2801       3491       4555       6405       7935      10652      13575      16960      23515      34271
               15         13         11         9          8          6          5          4          4          3

               78         64         57         49         46         39         35         32         27         23

                31         32         32         31         33        32         33         35         33         33
                80         72         64         56         50        44         40         36         32         28
             1.8/1.6    1.9/1.7    1.9/1.7    1.9/1.7    1.9/1.7    2.0/1.8    2.0/1.8    2.0/1.8    2.0/1.8    2.0/1.8
               2.9        2.6        2.4        2.1        1.9        1.7        1.5        1.3        1.2        1.1
               160        144        128        112        100        88         80         72         64         56

               7          7          6          5          5          4          4          4          3          3


               4.3       4.49       4.83        5.2       5.58       6.01       6.33        6.7       7.34       8.19
             1.6-1.8    1.5-1.8    1.5-1.8    1.5-1.8    1.3-1.6    1.3-1.6    1.3-1.6    1.3-1.5    1.3-1.5    1.3-1.5
            1.91E+06   1.85E+06   2.25E+06   2.57E+06   2.57E+06   3.06E+06   2.97E+06   3.23E+06   3.81E+06   4.25E+06

              1291       1455       1842       2406       2670       3341       4043       4665       5905       7712


              2524       2970       4044       5687       6771       9127      11632      14208      19700      28711

               16         14         12         9          8          7          6          5          4          3

               102         80        72         62         60         48         43         38         34         30
               120        108        96         84         75         66         60         54         48         42
             1.5–25     1.5–29     1.5–31     1.5–36     1.5–40     1.5–45     1.5–50     1.5–56     1.5–63     1.5–71
             2.4/2.2    2.5/2.3    2.5/2.3    2.5/2.3    2.6/2.4    2.6/2.4    2.6/2.4    2.8/2.5    2.8/2.5    2.8/2.5
               2.9        2.6        2.4        2.1        1.9        1.7        1.5        1.3        1.2        1.1

              240        250        250        250        260        260        260        280        280        280
               14         14         12         11         10         9          8          8          7          6
 3.22      3.34      3.52      3.73      3.93       4.2      4.38      4.58      4.92      5.38
1.8-2.0   1.7-2.0   1.7-2.0   1.7-2.0   1.5-1.8   1.5-1.8   1.5-1.8   1.5-1.8   1.5-1.8   1.5-1.8

 487       557       705       921       1004      1297      1569      1759      2226      2907


 713       846       1129      1562      1794      2476      3124      3661      4978      7110

  26        23        19        15        13        11        9         8         7         5

 112        86        81        71        68        62        56        53        45        41
1.8-2.0   1.6-1.8   1.7-2.0   2.0-2.3   1.5-1.8   1.8-2.1   1.5-1.8   1.6-1.8   1.8-2.1   2.1-2.4
  2021       2022
   15         15


  7692       9091
  0.7        0.5
1.7–2.0    1.7–2.0
1.5–1.9    1.5–1.9
2.1–2.4    2.1–2.4
   26         22
  2.1        2.1
   1         0.9

   3          2


  8.51       9.84

1.4–1.6    1.4–1.6

  9369      13085


 36239      58525
   3          2

   22         18

   32         33
   26         22
 2.1/1.9    2.1/1.9
    1         0.9
   52         44

   3          2


  8.51       9.84
 1.1-1.3    1.1-1.3
3.65E+06   4.47E+06

  7482      10450


 28942      46741

   3          3

   30         22
   39         33
 1.5-80     1.5-90
 2.9/2.6    2.9/2.6
    1         0.9

  300        290
   5          5
 5.59       6.3
1.3-1.5   1.3-1.5

 2860      3994


 7266     11437

  5         4

  39        31
1.6-1.9   1.9-2.3
INDEX LINK   Table INTC3                                                              DRAM Interconnect Technology Requirements—Near and
             Year of Production                                                           2007     2008       2009       2010
             Number of metal layers                                                         4        4          4          4
             Contact A/R – stacked capacitor                                                16       17         17       >20
             Metal 1 wiring pitch (nm)*                                                    130      114        100        90
             Specific contact resistance (Ω-cm2) for n+ Si                             2.00E-08   1.70E-08   1.40E-08   1.20E-08
             Specific contact resistance (Ω-cm2) for p+ Si                             3.20E-08   2.70E-08   2.20E-08   1.80E-08
             Specific via resistance (Ω-cm2)                                           5.00E-10   4.00E-10   3.50E-10   2.90E-10
             Conductor effective resistivity (µΩ-cm) assumes no scattering for Cu        2.2        2.2        2.2        2.2
             Interlevel metal insulator – effective dielectric constant (κ)            3.6–4.1    3.6–4.1    3.1–3.4    3.1-3.4


             * Refer to Executive Summary for the definition of Metal 1 pitch

                            Manufacturable solutions exist, and are being optimized
                                              Manufacturable solutions are known
                                                      Interim solutions are known     
                                          Manufacturable solutions are NOT known
ogy Requirements—Near and Long-term Years
             2011       2012       2013       2014       2015       2016       2017       2018       2019       2020
               4          4          4          4          4          4          4          4          4          4
             >20         >20        >20       >20         >20        >20        >20        >20        >20        >20
              80          72         64        56          50         44         40         36         32         28
            9.80E-09   8.20E-09   6.90E-09   5.80E-09   4.80E-09   4.00E-09   3.40E-09   2.80E-09   2.34E-09   1.96E-09
            1.50E-08   1.30E-08   1.10E-08   9.20E-09   7.40E-09   6.20E-09   5.10E-09   4.30E-09   3.60E-09   3.01E-09
            2.50E-10   2.10E-10   1.70E-10   1.40E-10   1.20E-10   1.00E-10   8.40E-11   7.00E-11   5.81E-10   4.82E-10
              2.2        2.2        2.2        2.2        2.2        2.2        2.2        2.2        2.2        2.2
            2.7–3.0    2.7–3.0    2.7–3.0    2.5–2.8    2.5–2.8    2.5–2.8    2.3–2.6    2.3–2.6    2.3–2.6    2.3–2.6
 2021       2022
   4          4
 >20         >20
  26          22
1.65E-09   1.37E-09
2.52E-09   2.11E-09
4.00E-10   3.32E-10
  2.2        2.2
2.3–2.6    2.3–2.6
INDEX LINK   Table INTC4                                                                          Interconnect Surface Preparation Technology Requir
             Year of Production                                                                       2007    2008      2009
             Wafer diameter (mm)                                                                       300     300       300
             Wafer edge exclusion (mm)                                                                  2       2         2
             Front surface particles
                                                    2
              Killer defect density, DpRp (#/cm ) [A]                                                 0.023   0.016     0.02
              Critical particle diameter, dc (nm) [B]                                                 32.5    28.5       25
              Critical particle density, Dpw (#/wafer) [C]                                             80      54        68
             Back surface particles
              Back surface critical particle diameter (nm) [D]                                        0.16    0.16      0.14
              Back surface critical particle density (#/wafer) [E]                                    200     200       200
             Edge bevel particles
              Edge bevel critical particle diameter (nm) [F]                                          130      114      100
                            –2
              Particles (cm ) (G)                                                                     TBD     TBD       TBD
              Particles (#/wafer) (G)                                                                 TBD     TBD       TBD
             Metallic Contamination
                                                    9              2
              Critical front surface metals (10         atoms/cm ) (H)                                 10      10        10
                                                          9            2
              Critical back surface metals (Cu) (10           atoms/cm ) (I)                          500     500       500
                                 10             2
              Mobile ions (10         atoms/cm ) [J]                                                   2.5     2.5      2.5
                                           13                  2
             Organic contamination (10      C atoms/cm ) [K]                                           1.2     1        0.9
             Cleaning Effects on Dielectric Material
             Maximum dielectric constant increase due to Etch, Strip + Clean [L]                    2.50%     2.50%    2.50%
             Maximum dielectric constant increase due to rework [L]                                 2.50%     2.50%    2.50%
             Maximum effect on dielectric critical dimension due to dry Strip [M]                     1%        1%       1%
             Maximum effect on dielectric critical dimension due to Strip + Clean [M]               1.50%     1.50%    1.50%

                                       Manufacturable solutions exist, and are being optimized
                                                         Manufacturable solutions are known
                                                                    Interim solutions are known   
                                                        Manufacturable solutions are NOT known
ace Preparation Technology Requirements—Near and Long-term Years
              2010     2011      2012     2013     2014      2015   2016    2017    2018    2019
               300      300       300      300      450       450    450     450     450     450
                2        2         2        2        2         2      2       2       2       2


              0.025    0.016     0.02     0.025    0.016     0.02   0.014   0.017   0.022   0.02
               22.5     20       17.5      16       14       12.5    11      10       9       9
               86      123.3     155       195     123.1     155     106    133.4    168     150

               0.14     0.14     0.14      NA       NA       NA      NA      NA      NA      NA
               200      200      200       NA       NA       NA      NA      NA      NA      NA

               90       80        70       64       56        50     44      40      36      32
              TBD       TBD      TBD      TBD      TBD       TBD    TBD     TBD     TBD     TBD
              TBD       TBD      TBD      TBD      TBD       TBD    TBD     TBD     TBD     TBD


               10       10        10       10       10        10     10      10      10      10
               250      250      250       100      100      100     100     100     100     100
               2.5      2.5      2.5       2.4      2.4      2.4     2.3     2.3     2.3     2.3
               0.9      0.9      0.9       0.9      0.9      0.9     0.9     0.9     0.9     0.9

              2.50%    2.50%    2.50%     2.50%    2.50%    2.50%   2.50%   2.50%   2.50%   2.50%
              2.50%    2.50%    2.50%     2.50%    2.50%    2.50%   2.50%   2.50%   2.50%   2.50%
                1%       1%       1%        1%       1%       1%      1%      1%      1%      1%
              1.50%    1.50%    1.50%     1.50%    1.50%    1.50%   1.50%   1.50%   1.50%   1.50%
2020    2021    2022    Driver
 450     450     450      D ½, M
  2       2       2       D ½, M


0.018   0.017   0.016      D½
  8       8       7        D½
 150     150     150       D½

 NA      NA      NA        D½
 NA      NA      NA        D½

 32      30      30         M
TBD     TBD     TBD         M
TBD     TBD     TBD         M


 10      10      10
 100     100     100
 2.3     2.3     2.3
 0.9     0.9     0.9

2.50%   2.50%   2.50%
2.50%   2.50%   2.50%
  1%      1%      1%
1.50%   1.50%   1.50%
INDEX LINK   Table INTC5        Options for Interconnects Beyond the Metal/Dielectric System

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table INTC6                                   High Density Through Silicon via Draft Specification
             Year of Production                              2007       2008       2009       2010       2011
             Minimum Interlayer HDTSV Contact Pitch (µm)
             High Density                                   3.2–5.0    2.9–4.4    2.6–3.8    2.2–3.4    2.0–3.0

             HDTSV Diameter (µm)
             High Density                                   1.6–2.5    1.4–2.2    1.3–1.9    1.1–1.7    1.0–1.5

             Maximum Via Density (cm 2 )
             High Density                                  9.77E+0.6   1.21E+07   1.53E+07   1.99E+07   2.31E+07

             Minimum Face-to-Face Pitch (µm)
             High Density                                      5         4.38       3.83       3.35       2.93

             Maximum Layer Thickness (µm)
             High Density                                    7–25       7–25       7–25       6–20       6–20
             Total Thickness Variation (µm)                   <1                              <0.75
t Specification
                   2012      2013       2014       2015

                  1.6–2.6   1.4–2.2    1.3–2.0    1.0–1.7



                  0.8–1.3   0.7–1.1    0.6–1.0    0.5–0.9



              3.91E+00      4.82E+07   6.10E+07   9.61E+07



                   2.56       2.24       1.96       1.72



                   6–20      5–15       5–15       5–15
                             <0.5
INDEX LINK   Table INTC7                M inimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivit

             Technology Year              2007     2008      2009     2010      2011     2012      2013
             Wire Pitch (nm)               136      118       104      90        80       72        64
             Cu Resistivity (µ W -cm)     3.51     3.63       3.8     4.08       4.3     4.53      4.83
                                   -2
             Minimum Density (nm )        0.204    0.197     0.188    0.175    0.166     0.158    0.148
inimum Cu Wire Conductivity

              2014     2015    2016    2017    2018    2019    2020    2021    2022
               56       50      44      40      36      32      28      26      22
               5.2     5.58    6.01    6.33     6.7    7.34    8.19    8.51    9.84
              0.138    0.128   0.119   0.113   0.107   0.097   0.087   0.084   0.073
INDEX LINK   Table FAC1            Factory Integration Difficult Challenges—Near and Long-term Years

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table FAC2            Key Focus Areas and Issues for FI Functional Areas Beyond 2007

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table FAC3                                                         Factory Operations Technology Requirements—Near and Lo
             Year of Production                                                     2007    2008       2009       2010
             Wafer Diameter (mm)                                                     300    300         300        300
             Non-hot lot (average of 94% lots)
               Cycle time per mask layer (days) 25 wafer lot                        1.5      1.5       1.4        1.4
               Cycle time per mask layer (days) 12 wafer lot                         1        1        0.84       0.84
               X-Factor [1]                                                         3.1      3.1       3.05       3.05
             Hot lot (average top 5% of lots)
               Cycle time per mask layer (days) 25 wafer lot                        0.55    0.55       0.51       0.51
               Cycle time per mask layer (days) 12 wafer lot                        0.5     0.5        0.42       0.42
               X-Factor [1]                                                         1.3     1.3        1.3        1.3
             Super hot lot (average top 1% of lots)
               Cycle time per mask layer (days)                                   0.32       0.32      0.31       0.31
             High-mix capacity degradation                                       8.33%      6.67%      5%         5%
             Bottleneck equipment [2] [3]
               Utilization                                                       92%        92%        94%        94%
               Availability                                                      94%        94%        96%        96%
             Wafer layers/day/head count                                          61         61         67         67
             Number of lots per carrier (high mix) [4]                          Multiple   Multiple   Multiple   Multiple
             Facilities cycle time (weeks)
               1st tool to 1st full loop wafer out                                   13      11         11         11
             Generation-to-generation
             change-over (weeks)                                                     12      12         11         11
             Floor space effectiveness                                               1×      1×         1×         1×
             Average number of wafers between reticle changes 25 wafer lot           30      25         20         20
             Average number of wafers between reticle changes 12 wafer lot           15      13         10         10

             New non-product wafers (NPW) as a % of wafer starts per week           <12%    <11%       <11%       <11%

                      Manufacturable solutions exist, and are being optimized
                                        Manufacturable solutions are known
                                                Interim solutions are known     
                                    Manufacturable solutions are NOT known
ology Requirements—Near and Long-term Years
              2011      2012       2013       2014       2015       2016       2017       2018       2019       2020
              300        450        450       450         450        450        450        450        450        450

              1.2       1.2        1.2        1.13       1.13       1.13       1.05       1.05       1.05       1.05
              0.72      0.72       0.72       0.68       0.68       0.68       0.63       0.63       0.63       0.63
              3.05      3.05       3.05       3.05       3.05       3.05        3          3          3          3

              0.47      0.47       0.47       0.44       0.44       0.44       0.39       0.39       0.39       0.39
              0.36      0.36       0.36       0.34       0.34       0.34       0.32       0.32       0.32       0.32
              1.2       1.2        1.2        1.2        1.2        1.2        1.1        1.1        1.1        1.1

              0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3        0.3
              5%         5%         5%         5%         5%         5%         5%         5%         5%         5%

             94%        94%        94%        94%        94%        94%        94%        94%        94%        94%
             96%        96%        96%        96%        96%        96%        96%        96%        96%        96%
              73         73         73         81         81         81         89         89         89         89
            Multiple   Multiple   Multiple   Multiple   Multiple   Multiple   Multiple   Multiple   Multiple   Multiple

               9          9          9          7          7          7          5          5          5          5

               10        10         10         9.5        9.5        9.5         9          9          9          9
               1×        1×         1×         1×         1×         1×         1×         1×         1×         1×
               20        20         20         15         15         15         13         13         13         13
               10        10         10          8          8          8          7          7          7          7

             <10%       <10%       <10%       <9%        <9%        <9%        <9%        <9%        <9%        <9%
 2021       2022
 450         450

 1.05       1.05
 0.63       0.63
  3          3

 0.39       0.39
 0.32       0.32
 1.1        1.1

  0.3        0.3
  5%         5%

 94%        94%
 96%        96%
  89         89
Multiple   Multiple

   5          5

   9          9
  1×         1×
  13         13
   7          7

 <9%        <9%
INDEX LINK   Table FAC4                                                         Production Equipment Technology Requirements—Near and
             Year of Production                                                 2007       2008    2009    2010
             Wafer Diameter (mm)                                                 300        300     300     300
             Overall NPW activities versus production wafers activities           7%        7%      5%      5%
             % capital equipment reused from previous node                      >90%       >90%    >90%    >90%
             Wafer edge exclusion                                                  2         2       2       2
             Lithography Equipment Qualification Duration                       4 wks      4 wks   4 wks   4 wks
             Process equipment availability (A80)                               >92%       >94%    >95%    >95%
             Metrology equipment availability (A80)                              96%       >96%    >97%    >98%
             Equipment-induced non-value added time as a % of total
             processing time (high mix)                                             10%    10%     8%       8%
             Ability to run different recipes and parameters for each wafer         Yes    Yes     Yes      Yes
             248 nm lithography scanner productivity (wafers outs per week
             per tool)                                                              7700   7700    8000    8000
             193 nm lithography scanner productivity (wafers outs per week
             per tool)                                                              5600   5600    6000    6000
             Maximum allowed electrostatic field on wafer and mask surfaces
             (V/cm)                                                                 70      63      55      50

                      Manufacturable solutions exist, and are being optimized
                                        Manufacturable solutions are known
                                               Interim solutions are known      
                                   Manufacturable solutions are NOT known
hnology Requirements—Near and Long-term Years
             2011      2012    2013      2014      2015    2016    2017    2018    2019    2020
              300       450     450       450       450     450     450     450     450     450
              5%        5%      5%        5%        5%      5%      5%      5%      5%      5%
             >90%      >90%   Limited   Limited    >70%    >70%    >70%    >70%    >70%    >70%
               2      1.5mm   1.5mm     1.5mm     1.5mm   1.5mm   1.5mm   1.5mm   1.5mm   1.5mm
             4 wks    4 wks    4 wks     4 wks    4 wks   4 wks   4 wks   4 wks   4 wks   4 wks
             >95%      >95%    >95%      >95%      >95%    >95%    >95%    >95%    >95%    >95%
             >98%      >98%    >98%      >98%      >98%    >98%    >98%    >98%    >98%    >98%

              8%       8%       8%       6%        6%      6%      6%      4%      4%      4%
              Yes      Yes      Yes      Yes       Yes     Yes     Yes     Yes     Yes     Yes

             8000     8000     8000      8000     8000    8000    8000    8000    8000    8000

             6000     6000     6300      6300     6500    6500    6500    6500    6500    6500

              44       38       35        31       28      25      22      20      18      15
 2021    2022
  450     450
  5%      5%
 >70%    >70%
1.5mm   1.5mm
4 wks   4 wks
 >95%    >95%
 >98%    >98%

 4%      4%
 Yes     Yes

8000    8000

6500    6500

 13      10
INDEX LINK   Table FAC5                                                        Material Handling Systems Technology Requirements—Near
             Year of Production                                                 2007       2008     2009     2010
             Wafer Diameter (mm)                                                 300        300      300      300
             Transport E-MTTR (minutes) per SEMI E10                              10         10       10       10
             Storage E-MTTR (minutes) per SEMI E10                                20         20       20       20
             Transport MMBF                                                    15,000     25,000   25,000   35,000
             Storage MCBF                                                      60,000     60,000   60,000   60,000
             Peak system throughput (40K WSPM)
               Interbay transport (moves/hour)                                     2538   2626     2713     2800
               Intrabay transport (moves/hour)
              — high throughput bay                                                277    288      300      311
               Transport (moves/hour)—unified system                               5512   5701     5891     6080
             Stocker cycle time (seconds) (100 bin capacity)                        12     12       12       12
             Average delivery time (minutes)                                        5      5        5        5
             Peak delivery time (minutes)                                           12     12       12       10
             Hot lot average delivery time (minutes)                                4      3        3        2
             AMHS lead time (weeks)                                                 12     12       12       <8
             AMHS install time (weeks)                                              24     24       24      <10
             Downtime to extend system capacity when previously planned
             (minutes)                                                             15      15       15       10
             Time required to integrate process tools to AMHS (minutes per
             LP)                                                                   15      12       12       10

                     Manufacturable solutions exist, and are being optimized
                                       Manufacturable solutions are known
                                               Interim solutions are known     
                                   Manufacturable solutions are NOT known
s Technology Requirements—Near and Long-term Years
              2011     2012     2013      2014        2015     2016     2017      2018      2019      2020
              300       450      450      450          450      450      450       450       450       450
               10        5        5         5           5        5        5         5         5         5
               20        20       20       20           15       15       15        10        10        10
             35,000   45,000   45,000    45,000      55,000   55,000   55,000    65,000    65,000    65,000
             60,000   70,000   70,000    70,000      80,000   80,000   80,000   100,000   100,000   100,000

              2891     2983     3074     3112        3150     3188     3285      3383      3480      3520

              324      337      350      365         379      394      410       427       443       449
              6220     6359     6499     6579        6659     6740     6879      7019      7159      7241
               12       10       10       10          10       10       10        10        10        10
               5        5        5        5           5        5        5         5         5         5
               10       10       10       10          10       10       10        10        10        10
               2        2        2        2           2        2        2         2         2         2
               <8       <8       <8       <8          <8       <8       <8        <8        <8        <8
              <10      <10      <10      <10         <10      <10      <10       <10       <10       <10

               10       10       10       10           5        5        5         5         5         0

               10       5         5        5           5        5        5         5         5         5
  2021      2022
  450        450
    5         5
   10         10
 65,000    65,000
100,000   100,000

 3560      3600

 455       461
 7323      7406
  10        10
  5         5
  10        10
  2         2
  <8        <8
 <10       <10

   0         0

   5         5
INDEX LINK   Table FAC6                                                                 Factory Information and Control Systems Technology
             Year of Production                                                           2007      2008      2009      2010
             Wafer Diameter (mm)                                                           300       300      300        300
             Availability of mission critical applications (% per year)                 >99.99%   >99.99%   >99.99%   >99.99%
             Downtime of mission critical applications (minutes per year)               <53 min   <53 min   <53 min   <53 min

             Unscheduled downtime of mission critical applications (minutes per year)   <15 min   <15 min   <15 min   <15 min
             Scheduled downtime of mission critical applications (minutes per year)     <40 min   <40 min   <40 min   <40 min
             MCS design to support peak number of AMHS transport moves
             (moves/hr)                                                                 14.7K      15K       15K        15K
             Wafer-level (within-lot) recipe / parameter adjustment                     Partial   Partial   Partial     Yes
                                                                                                                      Partial
             Within-wafer recipe / parameter adjustment                                     No      No        No      (Litho)

                              Manufacturable solutions exist, and are being optimized
                                                Manufacturable solutions are known
                                                        Interim solutions are known     
                                            Manufacturable solutions are NOT known
Control Systems Technology Requirements—Near and Long-term Years
               2011       2012      2013        2014        2015        2016        2017        2018        2019        2020
               300         300       450         450         450         450         450         450         450         450
             >99.99%    >99.99%   >99.995%    >99.995%    >99.995%    ≥99.999%    ≥99.999%    ≥99.999%    ≥99.999%    ≥99.999%
             <35 min    <35 min    <26 min     <26 min     <26 min     ≤5 min      ≤5 min      ≤5 min      ≤5 min      ≤5 min

             <15 min    <15 min    <10 min     <10 min     <10 min      ≤5 min      ≤5 min      ≤5 min      ≤5 min      ≤5 min
             <20 min    <20 min    <15 min     <15 min     <15 min       0 min       0 min       0 min       0 min       0 min

                15K       15K        15K         15K         15K         15K         15K         15K         15K         15K
                Yes       Yes        Yes         Yes         Yes         Yes         Yes         Yes         Yes         Yes
              Partial   Partial
              (Litho)   (Litho)   Yes (Litho) Yes (Litho) Yes (Litho) Yes (Litho) Yes (Litho) Yes (Litho) Yes (Litho) Yes (Litho)
  2021        2022
   450         450
≥99.999%    ≥99.999%
 ≤5 min      ≤5 min

  ≤5 min      ≤5 min
   0 min       0 min

   15K         15K
   Yes         Yes

Yes (Litho) Yes (Litho)
INDEX LINK   Table FAC7                                                                     Facilities Technology Requirements—Near and Long-te
             Year of Production                                                               2007         2008          2009         2010
             Wafer Diameter (mm)                                                               300          300           300          300
                                                                        2
             Manufacturing (cleanroom) area/wafer starts per month (m /WSPM) (low
             mix only)                                                                        0.6      0.625       0.65      0.675
             SubFab to Fab ratio (see definition)                                              1        0.75       0.75       0.75
             Facility service life (in three-year nodes)                                       3         3          3          3
                                                                                          Class 6 at Class 6 at Class 6 at Class 6 at
             Facility cleanliness level (ISO 14644) [1]                                      rest       rest       rest       rest

             Facility cleanliness level (Airborne molecular contamination AMC) - ppt                                             Discussed in Yield Enhancement C
             Facility critical vibration areas                                               6.25          6.25          6.25         6.25
             (lithography, metrology, other) (micrometers per second) [3]                   (VC D)        (VC D)        (VC D)       (VC D)
             Facility non-critical vibration areas                                            50            50            50           50
             (micrometers per second) [3]                                                   (VC A)        (VC A)        (VC A)       (VC A)
             Temperature and Humidity Specifications                                                                             Discussed in Yield Enhancement C
             Maximum allowable electrostatic field on facility surfaces (V/cm)                 70           63            55           50
             Gas, water, chemical purity                                                                                         Discussed in Yield Enhancement C
             Factory construction time from groundbreaking to first tool move-in
             (months)                                                                          12           11            11            10
             Production equipment install and qualification cost as a % of capital cost
             [4]                                                                              10%           9%            9%           8%
             Facility power, water, and chemical consumption                                                                            Discussed in ESH Chapter
                                                                       2
             Energy Consumption Total Fab Support System (kWh/cm per wafer
             out)                                                                                                                       Discussed in ESH Chapter
             Ratio of tool idle versus processing energy consumption (kWh)                    0.75         0.75           0.6          0.5



                              Manufacturable solutions exist, and are being optimized
                                                Manufacturable solutions are known
                                                         Interim solutions are known      
                                             Manufacturable solutions are NOT known




             Note: Facilities technology requires table make the following assumptions with respect to legends:
                                                                                       Current solutions provide cost effective trade off between facilities and equipm
                                                                                       Does not prevent manufacturing, but use of space is not optimized.
             
                                                                                          Does not prevent manufacturing, but impact on space, time to manufacturing,
uirements—Near and Long-term Years
                      2011          2012          2013         2014          2015     2016     2017         2018        2019        2020
                      300            450           450         450            450      450      450          450         450         450


                      0.7       0.725       0.75      0.775       0.8       0.825       0.85      0.875      0.9                   0.925
                     0.75        0.75       0.75       0.75       0.75       0.75       0.75       0.75      0.75                   0.75
                       3          3          3          3          3          3          3          3         3                      3
                  Class 6 at Class 7 at Class 7 at Class 7 at Class 7 at Class 7 at Class 7 at Class 7 at Class 8 at             Class 8 at
                     rest      rest [2]   rest [2]   rest [2]   rest [2]   rest [2]   rest [2]   rest [2]  rest [2]               rest [2]

  Discussed in Yield Enhancement Chapter                                                                Discussed in Yield Enhancement Chapter
                    6.25      6.25        6.25                 6.25           6.25     6.25     6.25         6.25         6.25      6.25
                   (VC D)    (VC D)      (VC D)               (VC D)         (VC D)   (VC D)   (VC D)       (VC D)       (VC D)    (VC D)
                     50        50          50                   50             50       50       50           50           50        50
                   (VC A)    (VC A)      (VC A)               (VC A)         (VC A)   (VC A)   (VC A)       (VC A)       (VC A)    (VC A)
  Discussed in Yield Enhancement Chapter                                                                Discussed in Yield Enhancement Chapter
                     44        38          35                   31            28       25       22            20           18        15
  Discussed in Yield Enhancement Chapter                                                                Discussed in Yield Enhancement Chapter

                       10             9             9            9             9        8        8            8           8           8

                     8%         8%                 8%           8%            7%       7%       6%           6%          5%         5%
          Discussed in ESH Chapter                                                                            Discussed in ESH Chapter

          Discussed in ESH Chapter                                                                            Discussed in ESH Chapter
                     0.5        0.5                0.5          0.5           0.5      0.5      0.5          0.5         0.5        0.5




 trade off between facilities and equipment installation
se of space is not optimized.


mpact on space, time to manufacturing, and cost of ownership is not known.
                  2021       2022
                  450         450


                 0.95        0.975
                 0.75         0.75
                  3            3
              Class 8 at   Class 8 at
               rest [2]     rest [2]

ncement Chapter
                   6.25      6.25
                  (VC D)    (VC D)
                    50        50
                  (VC A)    (VC A)
ncement Chapter
                   13         10
ncement Chapter

                    8          8

                   5%         5%
H Chapter

H Chapter
                   0.5        0.5
INDEX LINK   Table FAC8          Crosscut Issues Relating to Factory Integration

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table FAC9          List of Next Wafer Size Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP1       Assembly and Packaging Difficult Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP2                                                              Single-chip Packages Technology Requirements—Near
             Year of Production                                                     2007        2008        2009        2010
             Cost per Pin Minimum for Contract Assembly (Cents/Pin)
             Low-cost, hand-held and memory                                         .27-.50     .25-.48     .24-.46     .23-.44
             Cost-performance                                                      .69-1.19    .66-1.13    .63-1.70    .60-1.20
             High-performance                                                         1.83        1.73        1.64        1.56
             Harsh                                                                0.27–2.11   0.25–2.00   0.24–1.90   0.23–1.54
                           2
             Chip size (mm )
             Low-cost/hand held                                                     100         100         100          100
             Cost performance                                                       140         140         140          140
             High performance (FPGA)                                                662         695         729          766
             Harsh                                                                  100         100         100          100
                                          2
             Maximum Power (Watts/mm )
             Hand held and memory (Watts)                                            3           3            3          3
             Cost-performance (MPU)                                                 0.57        0.86         0.9        0.96
             High-performance (MPU)                                                 0.33        0.47        0.46        0.47
             Harsh                                                                  0.18        0.2         0.2         0.22
             Core Voltage (Volts)
             Low-cost                                                                0.9         0.8         0.7         0.6
             Hand-held and memory                                                    0.7         0.6         0.6         0.5
             Cost-performance                                                        0.9         0.8         0.8         0.6
             High-performance                                                        0.9         0.8         0.8         0.6
             Harsh                                                                   1.2         1.2         1.2         1.2
             Package Pin count Maximum
             Low-cost                                                             148–700     150–800     160–850     170–900

             Cost performance                                                     600–2140    600–2400    660–2801    660–2783
             High performance (FPGA)                                                4000        4400        4620        4851
             Harsh                                                                  386         405         425         447
             Minimum Overall Package Profile (mm)
             Low-cost, hand held and memory                                          0.4         0.3         0.3         0.3
             Cost-performance                                                        0.8        0.65        0.65        0.65
             High-performance                                                        1.4        1.4         1.4         1.2
             Harsh                                                                   0.8        0.8         0.8         0.8
             Performance: On-Chip (GHz)

             Low-cost/Hand held                                                   735/4676    808/5144    889/5660    978–6224
             Cost-performance                                                       4.7         5.06        5.45        5.88
             High-performance                                                       4.7         5.06      9827.14       5.88
             Harsh                                                                  106         117         128         141
             Performance: Chip-to-Board for Peripheral Buses (MHz)
             Low-cost Logic/Memory to MPU clock                                   100/667     100/800     100/800      125/800
             Cost-performance (for multi-drop nets)                                 733         800         800          800
             High-performance (for differential-pair point-to-point nets) (GHz)     4.88        6.1         7.63         9.54
             Harsh                                                                  106         106         115          125
             Maximum Junction Temperature
             Low-cost, Hand Held and Memory                                         125         125         125          125
             Cost performance                                                        95          95          90           90
             High-performance                                                        95          95          90           90
             Harsh**                                                                175         175         200          220
             Harsh-complex ICs                                                      175         175         175          175
             Operating Temperature Extreme: Ambient (°C)
             Low-cost, Hand Held and Memory                                           55         55         55            55
             Cost-performance                                                         45         45         45            45
             High-performance                                                         55         55         55            55
             Harsh                                                                -40 to 150 -40 to 150 -40 to 175    -40 to 200
             Harsh-complex ICs                                                    -40 to 150 -40 to 150 -40 to 150    -40 to 150
Manufacturable solutions exist, and are being optimized
                  Manufacturable solutions are known
                         Interim solutions are known      
             Manufacturable solutions are NOT known
hnology Requirements—Near and Long-term Years
              2011         2012         2013         2014         2015         2016         2017         2018         2019         2020

             .22-.42       .21-.40      .20-.38      .20-.36     .20 -.34      .20-.32      .20-.30      .2-.29       .2-.27       .2-.26
             .57-.97       .54-.92      .51-.87     .48 - .83    .46 - .79    .44 - .75    .42 - .71    .39 - .68    .37 - .64    .35 - .61
               1.48          1.41         1.34         1.27        1.21          1.15         1.09        1.04         0.99         0.94
            .22-1.81     .21 - 1.71   .20 - 1.63   .20 - 1.55   .20 - 1.47   .20 - 1.40   .20 - 1.33   .20 - 1.26   .20 - 1.20   .20 - 1.14


               100          100          100          100          100          100          100          100          100          100
               140          140          140          140          140          140          140          140          140          140
               804          750          750          750          750          750          750          750          750          750
               100          100          100          100          100          100          100          100          100          100


               3            3             3           3            3            3            3            3            3            3
              1.13         1.11          1.1         1.17         1.19         1.07         1.12         1.19         1.27         1.24
              0.52         0.51         0.48         0.49         0.46         0.42         0.42         0.44         0.43         0.42
              0.22         0.24         0.25         0.25         0.27         0.28         0.28         0.29         0.29         0.29

               0.6          0.6          0.5          0.5          0.4          0.4          0.4          0.4          0.4          0.4
               0.5          0.5          0.5          0.4          0.4          0.4          0.4          0.4          0.4          0.4
               0.6          0.6          0.6          0.5          0.5          0.5          0.5          0.5          0.5          0.5
               0.6          0.6          0.6          0.5          0.5          0.5          0.5          0.5          0.5          0.5
                1            1           0.9          0.9          0.9          0.9          0.8          0.8          0.8          0.8

            180–950      188–1000     198–1050     207 - 1100 218 - 1150 229 - 1200 240 - 1200 252 - 1250 265 - 1250 278 - 1250

            720- 3061    720–3367     800–3704     800-4075     880–4482     880–4930     960-5423     960–5966     1050-6562 1050 - 7218
              5094         5348         5616         5896         6191         6501         6826         7167         7525       7902
               469         492          517          543          570          599          629          660           693       728

               0.3          0.3          0.3          0.2          0.2          0.2          0.2          0.2          0.2         0.15
              0.65          0.5          0.5          0.5          0.5          0.4          0.4          0.4          0.4         0.4
              1.2            1            1            1            1           0.9          0.9          0.9          0.9         0.8
              0.7           0.7          0.7          0.7          0.7          0.6          0.6          0.6          0.6         0.5

                                                                                                        1586 -       1665 -       1748 -
           1076 - 6846 1183 - 7530 1243–7903 1305 - 8303 1370 - 8718 1438 - 9154 1510 - 9612            10092        10597        11127
              6.33        6.82        7.34      7.91        8.52        9.18        9.89                10.65        11.47        12.36
              6.33        6.82        7.34      7.91        8.52        9.18        9.89                10.65        11.47        12.36
              155         171         188       207         227         250         275                  302          333          366

             125/800     125/1000     125/1000     125/1000     125/1000     150/1200     150/1200     150/1200     150/1200     150/1200
               800         1000         1000         1000         1000         1200         1200         1200         1200         1200
              11.92        14.9        18.63        23.28         29.1        34.93         41.91       46.10        50.71        55.78
               125         125          125          125          150          150           150         150          150          150

               125          125          125          125          125          125          125          125          125          125
                90           90           90           90           90           90           90           90           90           90
                90           90           90           90           90           90           90           90           90           90
               220          220          220          220          220          220          220          220          220          220
               175          175          175          175          175          175          175          175          175          175

                55           55         55             55         55         55               55         55         55               55
                45           45         45             45         45         45               45         45         45               45
                55           55         55             55         55         55               55         55         55               55
            -40 to 200   -40 to 200 -40 to 200     -40 to 200 -40 to 200 -40 to 200       -40 to 200 -40 to 200 -40 to 200       -40 to 200
            -40 to 150   -40 to 150 -40 to 150     -40 to 150 -40 to 150 -40 to 150       -40 to 150 -40 to 150 -40 to 150       -40 to 150
  2021         2022

  .19-.25     .19-.25
  .33-.58    0.32-0.55
    0.89        0.85
 .19-1.08    .19-1.03


   100          100
   140          140
   750          750
   100          100


    3           3
   1.63        1.73
   0.43        0.43
   0.3         0.3

   0.4          0.4
   0.4          0.4
   0.5          0.5
   0.5          0.5
   0.8          0.8

 292-1300    306-1300

1155-7940 1155-8337
  8297      8712
   764       803

   0.15        0.15
   0.3         0.3
   0.8         0.8
   0.5         0.5


1835-11683 1927-12268
   13.32      14.34
   13.32      14.34
    403        443

 150/1200    150/1200
   1200        1200
  61.36       67.50
   150         150

   125          125
    90           90
    90           90
   220          220
   175          175

    55           55
    45           45
    55           55
-40 to 200   -40 to 200
-40 to 150   -40 to 150
INDEX LINK   Table AP3                                                           Chip-to-package Substrate Technology Requirements—Near a
             Year of Production                                                     2007          2008          2009          2010
             Wire bond—single in-line (micron)                                       40            35            35            35
             Two-row Staggered Pitch (micron)                                        55            50            45            45
             Three-tier Pitch (micron)                                               60            60            60            55
             Wire bond—Wedge pitch (micron)                                          25            25            20            20
             Tape-automated Bonding (TAB)                                            35            35            35            35
             Flying Lead (micron)                                                    35            35            35            35
             Flip Chip Area Array (both organic and ceramic substrate)(micron)
             (ASIC)                                                                  130           130           130           130
             Flip Chip Area Array (organic substrate)(micron) (CPU, GPU,
             Chipset)                                                                160           160           150           150
             Flip Chip on Tape or Film (micron)                                       25            15            10            10

             Notes for Table AP96a and b:
             For very fine pitch chip to package bonding, alternative technologies such as TSV and bumpless interconnect will be used as alternatives to technologies
             Finer pitch is technically possible for most categories but does not meet cost constraints.
echnology Requirements—Near and Long-term Years
                       2011           2012           2013         2014   2015   2016   2017   2018   2019   2020
                        30             30             30           30     25     25     25     25     25     25
                        45             40             40           40     40     35     35     35     35     35
                        55             50             45           45     45     45     45     45     45     45
                        20             20             20           20     20     20     20     20     20     20
                        35             35             35           35     35     35     15     15     15     15
                        35             35             35           35     35     35     35     35     35     35

                        120            110           110          100    100    100     95     95     95     90

                        150            130           130          130    110    110    110    110    100    100
                         10             10            10           10     10     10     10     10     10     10



ect will be used as alternatives to technologies in this table.
2021   2022
 25     25
 35     35
 45     45
 20     20
 15     15
 35     35

 90     90

100    100
 10     10
INDEX LINK   Table AP4                                              Substrate to Board Pitch—Near and Long-term Years
             Year of Production                                       2007      2008     2009     2010
             BGA Solder Ball Pitch (mm) Conventional system Board
             Low-cost and hand-held*                                  0.65      0.65     0.65      0.65
             Cost-performance                                         0.65      0.65     0.65      0.65
             High-performance                                         0.8       0.8      0.8       0.8
             Harsh                                                    0.8       0.65     0.65      0.65
             Small portable products
             Low-cost and hand-held                                   0.65      0.65     0.65      0.5
             Harsh                                                    0.65      0.65     0.65      0.65
             CSP area array pitch (mm)                                0.2       0.2      0.2       0.2
             QFP lead pitch (mm)                                      0.4       0.3      0.3       0.3
             SON land pitch (mm)                                      0.4       0.4      0.4       0.3
             QFN land pitch (mm)                                      0.4       0.3      0.3       0.3
             P-BGA ball pitch (mm)                                    0.8       0.8      0.8       0.65
             T-BGA ball pitch (mm)                                    0.65      0.65     0.65      0.5
             FBGA ball pitch (mm)                                     0.4       0.3      0.3       0.3
             FLGA land pitch (mm)                                     0.4       0.3      0.3       0.3
             * Minimum number driven by hand held applications
ear and Long-term Years
              2011        2012   2013   2014   2015   2016   2017   2018   2019   2020

              0.5         0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.5         0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.65        0.65   0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.65        0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5

              0.5         0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.5         0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.15        0.15   0.15   0.1    0.1    0.1    0.1    0.1    0.1    0.1
              0.3         0.3    0.3    0.3    0.2    0.2    0.2    0.2    0.2    0.2
              0.3         0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3
              0.3         0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3
              0.65        0.65   0.65   0.65   0.65   0.65   0.65   0.65   0.65   0.65
              0.5         0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5    0.5
              0.2         0.2    0.2    0.2    0.2    0.15   0.15   0.15   0.15   0.15
              0.3         0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3    0.3
2021   2022

0.5    0.5
0.5    0.5
0.5    0.5
0.5    0.5

0.5    0.5
0.5    0.5
0.1    0.1
0.2    0.2
0.3    0.3
0.3    0.3
0.65   0.65
0.5    0.5
0.15   0.15
0.3    0.3
INDEX LINK   Table AP5a and b                                                  Package Substrates—Near and Long-term Years
             Year of Production                                                    2007   2008     2009      2010
             Glass Transition Temperature (°C)
             Rigid Structure                                                       220     230      230      230
             Buildup with Reinforcement Material                                   220     230      230      230
             Buildup without Reinforcement Material                                200     210      210      210
             Tape Structure                                                        280     280      280      280
             Dielectric Constant (at 1GHz)
             Rigid Structure                                                       3.4     3.4      3.4       3
             Buildup with Reinforcement Material                                    3       3        3       2.8
             Buildup without Reinforcement Material                                 3       3        3       2.7
             Tape Structure                                                        3.5     3.5      3.5      3.5
             Ceramics Structure/Low Dielectric Material                             4       4        3        3
             Ceramics Structure/High Dielectric Material                           100     100      100      100
             Dielectric Loss (at 1GHz)
             Rigid Structure                                                    0.013     0.013    0.013    0.013
             Buildup with Reinforcement Material                                0.007     0.007    0.007    0.007
             Buildup without Reinforcement Material                             0.007     0.007    0.005    0.005
             Tape Structure                                                     0.005     0.005    0.005    0.005
             Ceramics Structure                                                 0.0005    0.0005   0.0005   0.0005
             Coefficient of Thermal Expansion: X-Y Direction (ppm/°C)
             Rigid Structure                                                       12       10       10       8
             Buildup with Reinforcement Material                                   12       10       10       10
             Buildup without Reinforcement Material                                40       20       20       20
             Tape Structure                                                        20       16       16       16
             Ceramics Structure                                                  3 – 12   4 – 12   4 – 12   4 – 12
             Coefficient of Thermal Expansion: Z Direction (ppm/°C)
             Rigid Structure                                                       30       25       25       25
             Buildup with Reinforcement Material                                   30       20       20       20
             Buildup without Reinforcement Material                                40       20       20       20
             Tape Structure                                                        20       20       20       20
             Ceramics Structure                                                  3 – 12   4 – 12   4 – 12   4 – 12
             Water Absorption at 23°C/24hrs Dipped (weight %)
             Rigid Structure                                                       0.2     0.2      0.2      0.1
             Buildup with Reinforcement Material                                   0.05    0.04     0.04     0.04
             Buildup without Reinforcement Material                                0.1     0.1      0.1      0.1
             Tape Structure                                                         1       1        1        1
             Young’s Modulus (GPa )
             Rigid Structure                                                      30        30       30       30
             Buildup with Reinforcement Material                                  26        26       26       26
             Buildup without Reinforcement Material                                5        5        5        5
             Tape Structure                                                        3        3        3        3
             Ceramics Structure                                                 100-400   50–500   50–500   50–500
             Peel Strength from Cu (kN/m)
             Rigid Structure                                                       1.1     1.1      1.1      1.2
             Buildup with Reinforcement Material                                   1.4     1.4      1.4      1.4
             Buildup without Reinforcement Material                                1.4     1.4      1.4      1.4
             Tape Structure                                                         1       1        1       0.8
             Notes for Table ESH98a and b:
             State of the art materials may not be compatible with cost
             requirements for volume production
             Water absorption test is: JIS C6481
             Peel strength test: IPC TM650 2.4.8

                     Manufacturable solutions exist, and are being optimized
                                       Manufacturable solutions are known
                                                Interim solutions are known    
Manufacturable solutions are NOT known
nd Long-term Years
              2011    2012     2013     2014     2015     2016     2017     2018     2019     2020

              230      230      230      230      230      230      230      230      230      230
              230      230      230      230      230      230      230      230      230      230
              210      210      210      210      210      210      210      210      210      210
              280      280      280      280      280      280      280      280      280      280

               3        3        3       2.7      2.7      2.7      2.7      2.7      2.7      2.7
              2.8      2.8      2.8      2.8      2.8      2.8      2.8      2.8      2.8      2.8
              2.7      2.7      2.7      2.7      2.7      2.7      2.7      2.7      2.7      2.7
              3.5      3.5      3.5      3.5      3.5      3.5      3.5      3.5      3.5      3.5
               3        3        3        3        3        3        3        3        3        3
              100      100      100      100      100      100      100      100      100      100

              0.01     0.01     0.01     0.01     0.01     0.01     0.01     0.01     0.01     0.01
             0.007    0.007    0.007    0.007    0.007    0.007    0.007    0.007    0.007    0.007
             0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005
             0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005    0.005
             0.0005   0.0005   0.0005   0.0005   0.0005   0.0005   0.0005   0.0005   0.0005   0.0005

               8        8        8        6        6        6        6        6        6        6
               10       10       10       10       10       10       10       10       10       10
               20       10       10       10       10       10       10       10       10       10
               16       16       16       16       16       16       16       16       16       16
             4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12

               25       20       20       20       20       20       20       20       20       20
               20       20       20       20       20       20       20       20       20       20
               10       10       10       10       10       10       10       10       10       10
               20       20       20       20       20       20       20       20       20       20
             4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12   4 – 12

              0.1      0.1      0.1      0.05     0.05     0.05     0.05     0.05     0.05     0.05
              0.04     0.04     0.04     0.04     0.04     0.04     0.04     0.04     0.04     0.04
              0.1      0.1      0.1      0.1      0.1      0.1      0.1      0.1      0.1      0.1
               1        1        1        1        1        1        1        1        1        1

               30       30       30       30       30       30       30       30       30       30
               26       26       26       26       26       26       26       26       26       26
               5        5        5        5        5        5        5        5        5        5
               3        3        3        3        3        3        3        3        3        3
             50–500   50–500   50–500   50–500   50–500   50–500   50–500   50–500   50–500   50–500

              1.2      1.2      1.2      1.2      1.2      1.2      1.2      1.2      1.2      1.2
              1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4
              1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4      1.4
              0.8      0.8      0.8      0.8      0.8      0.8      0.8      0.8      0.8      0.8
 2021    2022

 230      230
 230      230
 210      210
 280      280

 2.7      2.7
 2.8      2.8
 2.7      2.7
 3.5      3.5
  3        3
 100      100

 0.01     0.01
0.007    0.007
0.005    0.005
0.005    0.005
0.0005   0.0005

  6        6
  10       10
  10       10
  16       16
4 – 12   4 – 12

  20       20
  20       20
  10       10
  20       20
4 – 12   4 – 12

 0.05     0.05
 0.04     0.04
 0.1      0.1
  1        1

  30       30
  26       26
  5        5
  3        3
50–500   50–500

 1.2      1.2
 1.4      1.4
 1.4      1.4
 0.8      0.8
INDEX LINK   Table AP5c and d                              Package Substrate Design Parameters—Near and Long-term Y
             Year of Production                              2007     2008     2009      2010
             Substrate cross-section core thickness (µm)
             Handhelds                                        40        35       35       30
             High density interconnect substrates             50        40       40       35
             Build-up substrates (4 core layers)             200       150      130      100
             Coreless buildup layer                           40        40       35       35
             Blind via diameter (µm)
             Handhelds                                        50       40       40        35
             High density interconnect substrates             50       40       40        35
             Build-up substrates                              40       35       35        30
             Coreless                                         60       50       50        40
             Blind via stacks
             High density interconnect substrates             3         3        3        3
             Build-up substrates                              5         6        6        6
             Coreless                                         10        11       11       11
             PTH diameter (µm)                                75        70       60       50
             PTH land (µm)                                   180       160      140      120
             Bump pitch (µm)
             High density interconnect substrates            190       180      170      160
             Build-up substrates                             130       120      110      100
             Coreless                                        130       120      110      100
             Lines/space width (µm)
             Rigid Structure                                  35       30       30        25
             Build-up substrates (core layer)                 35       30       30        25
             Build-up substrate (build-up layer)              15       10       10        10
             Coreless                                         20       15       15        10
             Lines/space width tolerance (%)                  7        7        7         7
             Solder mask registration  (µm)
             Handhelds                                        20       15       15        15
             High density interconnect substrates             20       15       15        15
             Build-up substrates                              25       20       20        15
arameters—Near and Long-term Years
             2011     2012     2013   2014   2015   2016   2017   2018   2019   2020

              30       30       25     25     25     25     25     25     25     25
              35       30       30     30     30     30     30     30     30     30
              90       80       80     70     70     70     70     70     70     70
              30       30       30     30     30     30     30     30     30     30

              35       30       30     25     25     25     25     25     25     25
              35       30       30     25     25     25     25     25     25     25
              30       25       25     20     20     20     20     20     20     20
              40       35       35     30     30     30     30     30     30     30

               4        4        4     4      4      4      4      4      4      4
               6        6        6     6      6      6      6      6      6      6
               12       12       13    14     14     14     14     14     14     14
               50       45       45    40     40     40     40     40     40     40
              110      105      105   100    100    100    100    100    100    100

              150      140      140   130    130    130    130    130    130    130
              100       90       90    80     80     80     80     70     70     70
              100       90       90    80     80     80     80     70     70     70

              25       22       22    20     20      20    20     20      20    20
              25       22       22    20     20      20    20     20      20    20
              9        8        8     6.8    6.4     6     5.6    5.3     5     4.7
              9        8        8     6.8    6.4     6     5.6    5.3     5     4.7
              7        7        6      5      5      5      5      5      5      5

              12       12       11     10     10     10     10     10     10     10
              12       12       11     10     10     10     10     10     10     10
              12       12       11     10     10     10     10     10     10     10
2021   2022

 25     25
 30     30
 70     70
 30     30

 25     25
 25     25
 20     20
 30     30

 4      4
 6      6
 14     14
 40     40
100    100

130    130
 70     70
 70     70

20     20
20     20
4.4    4.1
4.4    4.1
 5      5

 10     10
 10     10
 10     10
INDEX LINK   Table AP6                                                   Wafer Level Packaging—Near and Long-term Years
             Year of Production                                               2007             2008              2009
             Cost per Ball Minimum/Maximum for Contract Assembly [1,2]
             (Cents/Pin)
             a. Standard Logic and Analog/Linear Min                           0.25             0.21             0.18
             b. Standard Logic and Analog/Linear Max                           0.55             0.47             0.4
             Chip size (mm 2 ) (Min/Max)
             a. Memory                                                       20 / 250         20 / 250         20 / 250
             b. Standard Logic and Analog/Linear                              0.85/9          0.75/10          0.55/11
             c. Wireless: Bluetooth, FM, GPS, WIFI                            .85/16           .75/25           .55/29
             Ball Metallurgy                                                   SAC              SAC              SAC
             Number of RDL Layers
             a. Memory                                                          1                2                2
             b. Standard Logic and Analog/Linear                                1                2                2
             c. Wireless: Bluetooth, FM, GPS, WIFI                              1                2                2
             UBM Thickness (µm)
             a. Memory                                                      1.5-10µm         1.5-50µm          1.5-50µm
             b. Standard Logic and Analog/Linear                            1.1-10µm         1.1-50µm          1.1-50µm
             c. Wireless: Bluetooth, FM, GPS, WIFI                          1.5-10µm         1.5-50µm          1.5-50µm
             UBM Metallurgy
                                                                           CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,
                                                                         TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu,
             a. Memory
                                                                             Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
                                                                           TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
                                                                           TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
                                                                             Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
             b. Standard Logic and Analog/Linear
                                                                             Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
                                                                          TiW/Cu, Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
                                                                           TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
                                                                             Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
             c. Wireless: Bluetooth, FM, GPS, WIFI
                                                                             Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
                                                                          TiW/Cu, Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
             RDL Thickness
             a. Memory                                                       2-10µm           2-12µm            2-15µm
             b. Standard Logic and Analog/Linear                             2-10µm           2-12µm            2-15µm
             c. Wireless: Bluetooth, FM, GPS, WIFI                           2-10µm           2-12µm            2-15µm
             RDL Metallurgy
             a. Memory                                                     Al;TiAlTi;Cu     Al;TiAlTi;Cu     Al;TiAlTi;Cu
             b. Standard Logic and Analog/Linear                           Al;TiAlTi;Cu     Al;TiAlTi;Cu     Al;TiAlTi;Cu
                                                                                                            Al; TiAlTi; Cu;
             c. Wireless: Bluetooth, FM, GPS, WIFI                         Al;TiAlTi;Cu     Al;TiAlTi;Cu
                                                                                                                 Al/Cu
             Wafer Saw Street Width (µm)
             a. Memory                                                        85µm             75µm             70µm
             b. Standard Logic and Analog/Linear                              50µm             50µm             40µm
             c. Wireless: Bluetooth, FM, GPS, WIFI                            85µm             75µm             70µm
             Package Pincount Maximµm
             a. Memory                                                         150              175              200
             b. Standard Logic and Analog/Linear                                36               64               64
             c. Wireless: Bluetooth, FM, GPS, WIFI                             100              150              150
             Embedded components thickness (µm) (Max/Min)
             a. Memory                                                         100              100              100
             b. Standard Logic and Analog/Linear                             250/100          225/100          200/100
             c. Wireless: Bluetooth, FM, GPS, WIFI                             100              100              100
             Type of WLP structure and metallurgy (bump, ball, column,
             solder, Cu, other)
             a. Memory                                                         Ball             Ball             Ball

             b. Standard Logic and Analog/Linear                                           2ML/2P/ Plated   2ML/2P/ Plated
                                                                          2ML/2P/ Plated
                                                                                             Cu/Solder        Cu/Solder
                                                                            Cu/Solder
                                                                                             Bump/Ball/       Bump/Ball/
                                                                            Bump/Ball
                                                                                            Copper Pillar    Copper Pillar
                                                                              2ML/2P/ Plated     2ML/2P/ Plated
                                                           2ML/2P/ Plated
                                                                                Cu/Solder          Cu/Solder
                                                             Cu/Solder
                                                                                Bump/Ball/         Bump/Ball/
(P= polymer)                                                 Bump/Ball
                                                                               Copper Pillar      Copper Pillar


c. Wireless: Bluetooth, FM, GPS, WIFI                                         2ML/2P/ Plated     2ML/2P/ Plated
                                                           2ML/2P/ Plated
                                                                                Cu/Solder          Cu/Solder
                                                             Cu/Solder
                                                                                Bump/Ball/         Bump/Ball/
(P=Polymer)                                                  Bump/Ball
                                                                               Copper Pillar      Copper Pillar

Stacked Die Wafer Level CSP (Max. dies)
a. Memory                                                         1                  1                  1
b. Standard Logic and Analog/Linear                               2                  2                  3
c. Wireless: Bluetooth, FM, GPS, WIFI                             2                  2                  3
Stacked Die Wafer Level CSP Interconnect method (Through
silicon vias, face to face, others)
                                                            Piggyback on       Piggyback on      Through Silicon
a. Memory
                                                              underside          underside             Vias
                                                                                                 Mix of wire bond
                                                            Piggyback on       Piggyback on
                                                                                                   and flip chip
                                                           underside. Std.    underside. Std.
b. Standard Logic and Analog/Linear                                                               stacked dies.
                                                           stacked die with   stacked die with
                                                                                                 Through Silicon
                                                              wire bond        wire bond, F2F
                                                                                                       Vias
                                                            Piggyback on       Piggyback on      Through Silicon
c. Wireless: Bluetooth, FM, GPS, WIFI
                                                              underside       underside, F2F           Vias
Long-term Years
                   2010             2011              2012              2013              2014              2015


                    0.15            0.13              0.12              0.12              0.11              0.11
                    0.34            0.29              0.27              0.26              0.25              0.23

                  20 / 250        20 / 250          20 / 250          20 / 250          20 / 250          20 / 250
                  0.50/12         0.45/13           0.40/14           0.35/15           0.30/15           0.25/16
                   .50/34         0.45/36           0.40/38           0.35/40           0.30/42           0.25/46
                    SAC            SAC               SAC               SAC               SAC               SAC

                     3               3                 3                 3                 3                 3
                     3               3                 3                 3                 3                 3
                     3               3                 3                 3                 3                 3

                  1.5-50µm       1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm
                  1.1-50µm       1.1-50µm          1.1-50µm          1.1-50µm          1.1-50µm          1.1-50µm
                  1.5-50µm       1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm

              CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,
            TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu,
                Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
              TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
              TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
                Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
                Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
              TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
              TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
                Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
                Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
              TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu

                  2-15µm          2-15µm            2-15µm            2-15µm            2-15µm            2-15µm
                  2-15µm          2-15µm            2-15µm            2-15µm            2-15µm            2-15µm
                  2-15µm          2-15µm            2-15µm            2-15µm            2-15µm            2-15µm

              Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu
              Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu
             Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;
                  Al/Cu             Al/Cu             Al/Cu             Al/Cu             Al/Cu             Al/Cu

                   65µm            60µm              60µm              55µm              50µm              45µm
                   40µm            35µm              35µm              35µm              30µm              30µm
                   60µm            55µm              55µm              50µm              45µm              40µm

                    200             225               250               275               275               275
                    144             151               159               167               175               184
                    150             165               165               165               180               180

                     75              75                75                75                70                70
                   175/75          175/75            175/75            175/75            150/70            150/70
                     75              75                75                75                70                70


                    Ball            Ball              Ball              Ball              Ball              Ball

             2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated
               Cu/Solder         Cu/Solder         Cu/Solder         Cu/Solder         Cu/Solder         Cu/Solder
               Bump/Ball/        Bump/Ball/        Bump/Ball/        Bump/Ball/        Bump/Ball/        Bump/Ball/
              Copper Pillar     Copper Pillar     Copper Pillar     Copper Pillar     Copper Pillar     Copper Pillar
2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated
  Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder
  Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/
 Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar

2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated
  Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder
  Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/
 Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar


       4                  4                  8                  8                  8                  8
       3                  3                  3                  3                  3                  3
       3                  3                  3                  3                  3                  3


Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond
  and flip chip      and flip chip      and flip chip      and flip chip      and flip chip      and flip chip
 stacked dies.      stacked dies.      stacked dies.      stacked dies.      stacked dies.      stacked dies.
Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
      2016              2017              2018              2019              2020              2021


      0.1               0.1               0.09              0.09              0.08              0.08
      0.22              0.21              0.2               0.19              0.18              0.17

    20 / 250          20 / 250          20 / 250          20 / 250          20 / 250          20 / 250
    0.20/16           0.18/17           0.16/17           0.14/18           0.12/19           0.11/20
    0.20/48           0.18/50           0.16/52           0.14/54           0.12/56           0.11/58
     SAC               SAC               SAC               SAC               SAC               SAC

       3                 3                 3                 3                 3                 3
       3                 3                 3                 3                 3                 3
       3                 3                 3                 3                 3                 3

   1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm
   1.1-50µm          1.1-50µm          1.1-50µm          1.1-50µm          1.1-50µm          1.1-50µm
   1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm          1.5-50µm

  CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,    CuNi, TiCuNi,
TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu, TiCu, Al/NiV/Cu,
    Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
  TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
  TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
    Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
    Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
  TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu
  TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,    TiCuNi, TiCu,
    Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,       Al/NiV/Cu,
    Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,       Ti/NiV/Cu,
  TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu     TiW/Cu,Cr-Cu

    2-15µm            2-15µm            2-15µm            2-15µm            2-15µm            2-15µm
    2-15µm            2-15µm            2-15µm            2-15µm            2-15µm            2-15µm
    2-15µm            2-15µm            2-15µm            2-15µm            2-15µm            2-15µm

  Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu
  Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu      Al;TiAlTi;Cu
 Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;   Al; TiAlTi; Cu;
      Al/Cu             Al/Cu             Al/Cu             Al/Cu             Al/Cu             Al/Cu

     45µm              40µm              40µm              40µm              35µm              35µm
     30µm              25µm              25µm              25µm              20µm              20µm
     40µm              35µm              35µm              35µm              30µm              30µm

      275               275               275               275               275               275
      193               203               213               223               235               246
      180               195               195               195               210               210

       70                65                65                65                60                60
     150/70            140/65            140/65            140/65            135/60            135/60
       70                65                65                65                60                60


      Ball              Ball              Ball              Ball              Ball              Ball

2ML/2P/ Plated     2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated    2ML/2P/ Plated
  Cu/Solder          Cu/Solder         Cu/Solder         Cu/Solder         Cu/Solder         Cu/Solder
  Bump/Ball/         Bump/Ball/        Bump/Ball/        Bump/Ball/        Bump/Ball/        Bump/Ball/
 Copper Pillar      Copper Pillar     Copper Pillar     Copper Pillar     Copper Pillar     Copper Pillar
2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated
  Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder
  Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/
 Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar

2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated     2ML/2P/ Plated
  Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder          Cu/Solder
  Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/         Bump/Ball/
 Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar      Copper Pillar


       8                  8                  8                 12                 12                 12
       3                  3                  3                 3                  3                  3
       3                  3                  3                 3                  3                  3


Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond   Mix of wire bond
  and flip chip      and flip chip      and flip chip      and flip chip      and flip chip      and flip chip
 stacked dies.      stacked dies.      stacked dies.      stacked dies.      stacked dies.      stacked dies.
Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon    Through Silicon
      Vias               Vias               Vias               Vias               Vias               Vias
      2022


      0.07
      0.16

    20 / 250
    0.10/20
    0.10/60
     SAC

       3
       3
       3

   1.5-50µm
   1.1-50µm
   1.5-50µm

  CuNi, TiCuNi,
TiCu, Al/NiV/Cu,
    Ti/NiV/Cu,
  TiW/Cu,Cr-Cu
  TiCuNi, TiCu,
    Al/NiV/Cu,
    Ti/NiV/Cu,
  TiW/Cu,Cr-Cu
  TiCuNi, TiCu,
    Al/NiV/Cu,
    Ti/NiV/Cu,
  TiW/Cu,Cr-Cu

    2-15µm
    2-15µm
    2-15µm

  Al;TiAlTi;Cu
  Al;TiAlTi;Cu
 Al; TiAlTi; Cu;
      Al/Cu

     35µm
     20µm
     30µm

      275
      259
      210

       60
     135/60
       60


      Ball

 2ML/2P/ Plated
   Cu/Solder
   Bump/Ball/
  Copper Pillar
2ML/2P/ Plated
  Cu/Solder
  Bump/Ball/
 Copper Pillar

2ML/2P/ Plated
  Cu/Solder
  Bump/Ball/
 Copper Pillar


      12
      3
      3


Through Silicon
      Vias
Mix of wire bond
  and flip chip
 stacked dies.
Through Silicon
      Vias
Through Silicon
      Vias
INDEX LINK   Table AP7                                                      Key Technical Parameters for Stacked Architectures Using TSV
             Year of Production                                                  2007          2008           2009   2010   2011
             Numbers of stacked die using TSV                                  3 – (8)           6              9     >9     >9
             Minimum TSV pitch                                                     10            8              6      5      4
             TSV maximum aspect ratio**                                            10           10              10    10     10
             TSV exit diameter(um)                                                  4            4               3    2.5     2
             TSV layer thickness for minimum pitch                                 50           20              15    15     10
             **This applies for small diameter vias. The larger diameter vias will have a smaller aspect ratio.

                  Manufacturable solutions exist, and are being optimized
                                    Manufacturable solutions are known
                                             Interim solutions are known     
                                 Manufacturable solutions are NOT known
Architectures Using TSV
              2012        2013
               >9          >9
               3.8         3.6
               10          10
               1.9         1.8
               10          10
INDEX LINK   Table AP8         Comparison of SoC and SiP Architecture

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP9        Package Level System Integration
                                                                   2008   2010    2012      2014      2016
                                                                                 High Performance / Low Cost, Handheld
                              Capacitor                            o/o    o/o      o/o       o/o       o/o
                               Resistor                            o/o    o/o      o/o       o/o       o/o
               Passives        Inductor   O for YES                o/o    o/o      o/o       o/o       o/o
                                Optical                            o/o    o/o      o/o       o/o       o/o
                              CCD/CMO
                              S Sensor                             -/o    -/o      -/o       -/o       o/o
                Actives         MEMS      o for YES                -/o    -/o      -/o       -/o       o/o
                               IC to IC                  Wire      -/o    -/o      -/o       -/o       o/o
                              Connectio   o for        Flip Chip   o/o    o/o      o/o       o/o       o/o
                                   n    Applicable     Via Hole    -/o    -/o      -/o       -/o       o/o
                                 IC to                   Wire      o/o    o/o      o/o       o/o       o/o
                              Substrate                Flip Chip   o/o    o/o      o/o       o/o       o/o
             Package Inner    Connectio    o for       Via/ TSV
               Structure           n     Applicable       Hole     -/o    -/o      -/o       -/o       o/o
                               IC- RDL
                               (carrier-
                                 less)                             -/o    -/o      o/o       o/o       o/o

                                                           IC      -/o    o/o      o/o       o/o       o/o
               Integrated /                            Capacitor   o/o    o/o      o/o       o/o       o/o
               Embedded                     o for      Resistor    o/o    o/o      o/o       o/o       o/o
              Components      Passives    Applicable   Inductor    o/o    o/o      o/o       o/o       o/o
                                                         Rigid     o/o    o/o      o/o       o/o       o/o
                               Organic                  Flexible   -/o    -/o      -/o       -/o       o/o
               Substrate                    o for      Ceramic     o/o    o/o      o/o       o/o       o/o
                Material      Inorganic   Applicable    Silicon    o/o    o/o      o/o       o/o       o/o
                2018     2020   2022
e / Low Cost, Handheld
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o

                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o

                o/o      o/o    o/o


                o/o      o/o    o/o

                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
                o/o      o/o    o/o
INDEX LINK   Table AP10      Processes for SiP

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP11                                                         System in Package Requirements—Near and Long-term Years
             Year of Production                                                     2007    2008      2009      2010
             Number of terminals—low cost handheld                                   700     800       800       800
             Number of terminals—high performance (digital)                         3050    3190      3350      3509
             Number of terminals—maximum RF                                          200     200       200       200
             Low cost handheld / die / stack                                           7       8         9        10
             High performance / die / stack                                            3       3         3         4
             Low cost handheld / die / SiP                                             8       8         9        11
             High performance / die / SiP                                             6       6         6          7
             Minimum TSV pitch                                                        10      8         6         5
             TSV maximum aspect ratio                                                 10      10        10        10
             TSV exit diameter(um)                                                    4       4         3        2.5
             TSV layer thickness for minimum pitch                                    50      20        15        15
             Minimum component size (micron)                                        1005   600×300   600×300   400×200
             Maximum reflow temperature (°C)                                         260     260       260       260

                      Manufacturable solutions exist, and are being optimized
                                        Manufacturable solutions are known
                                               Interim solutions are known      
                                   Manufacturable solutions are NOT known
ments—Near and Long-term Years
              2011      2012      2013      2014      2015      2016      2017      2018      2019      2020
               800       800       800       800       800       800       800       800       800       800
              3684      3860      4053      4246      4458      4670      4904      5138      5394      5651
               200       200       200       200       200       200       200       200       200       200
                11        12        13        14        14        15        15        16        16        17
                 4         4         5         5         5         6         6         6         7         7
                12        13        14        14        14        15        15        16        16        17
                 7         7         8         8         8        9          9        9         10        10
                4        3.8       3.6       3.4       3.3       3.1       2.9       2.8       2.7       2.5
                10        10        10        10        10        10        10        10        10        10
                2        1.9       1.8       1.7       1.6       1.5       1.5       1.4       1.3       1.3
                10        10        10        10        8         8         8         8         8         8
             400×200   400×200   200×100   200×100   200×100   200×100   200×100   200×100   200×100   200×100
               260       260       260       260       260       260       260       260       260       260
 2021      2022
  800       800
 5934      6231
  200       200
   17        18
    7         8
   17        18
   10        11
  2.4       2.3
   10        10
  1.2       1.1
   8         8
200×100   200×100
  260       260
INDEX LINK   Table AP12a and b                                                Thinned Silicon Wafer Thickness 200 mm/300 mm—Near and L
             Year of Production                                                   2007   2008     2009     2010
             Min. thickness of thinned wafer
             (general product)                                                     50     50       50       50
             Min. thickness of thinned wafer
             (For extreme thin package ex. Smart card)                             20     20       15       15



                    Manufacturable solutions exist, and are being optimized
                                      Manufacturable solutions are known
                                              Interim solutions are known     
                                  Manufacturable solutions are NOT known
ness 200 mm/300 mm—Near and Long-term Years
             2011     2012     2013    2014   2015   2016   2017   2018   2019   2020

              45       40       40      40     40     40     40     40     40     40

              10       10       10      10     8      8      8      8      8      8
2021   2022

 40     40

 8      8
INDEX LINK   Table AP12c      Challenges and Potential Solutions in Thinning Si Wafers

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP13      SiP Failure Modes

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP14        Some Common Optoelectronic Packages and Their Applications

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP15   Protocol with Distance

             Protocol       VSR        SR          SX     IR1      IR2      LR1      LR2
                                                        1310nm   1550nm   1310nm   1550nm
             Sonet/         <2km     10km                20km     20km     40km     80km
             SDH
             GigE           300m      2km      500m               10km     20km      X
LX     ER     ZX     ZR

        X             X

10km   40km   80km   80km
INDEX LINK   Table AP16      Optoelectronic Packaging Challenges and Potential Solutions

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP17         MEMS Packaging Methods

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP18      MEMS Packaging Examples

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP19      Materials Challenges

             This table is a text table. For ease of editing, please use the Word file found online at:
             http://www.itrs.net/ITWG/word_files.html
INDEX LINK   Table AP20          Package Substrate Physical Properties
                                    Year of Production                                               2007     2008       2009
                                    Glass Transition Temperature (°C)
                                    Rigid Structure                                                   300      350        350
              State of the Art Buildup Structure                                                      220      250        250
                                    Tape Structure                                                    350      350        350
                                    Dielectric Constant (at 1GHz)
                                    Rigid Structure*                                                   3        3         2.7
                                    Buildup Structure                                                 2.8      2.8        2.5
              State of the Art Tape Structure                                                         2.2      2.2        2.2
                                    Ceramics Structure/Low Dielectric Material                         4        4          3
                                    Ceramics Structure/High Dielectric Material                       100      100        100
                                    Dielectric Loss (at 1GHz)
                                    Rigid Structure                                                   0.01     0.01      0.006
                                    Buildup Structure                                                0.002    0.002      0.002
              State of the Art
                                    Tape Structure                                                  0.0002    0.0001     0.0001
                                    Ceramics Structure                                              0.0005    0.0005     0.0005
                                    Coefficient of Thermal Expansion: X-Y Direction (ppm/°C)
                                    Rigid Structure                                                    10       9          8
                                    Buildup Structure                                                  5        4          4
              State of the Art
                                    Tape Structure                                                     10       10         10
                                    Ceramics Structure                                              4 – 12    4 – 12     4 – 12
                                    Coefficient of Thermal Expansion: Z Direction (ppm/°C)
                                    Rigid Structure                                                    20       20         15
                                    Buildup Structure with core layer                                  10       10         10
              State of the Art
                                    Tape Structure                                                     10       10         10
                                    Ceramics Structure                                              4 – 12    4 – 12     4 – 12
                                    Water Absorption at 23°C/24hrs Dipped (Weight %)
                                    Rigid Structure                                                   0.04     0.04       0.04
                                    Buildup with Reinforcement Material                               0.04     0.04       0.04
              State of the Art
                                    Buildup without Reinforcement Material                            0.1      0.1        0.1
                                    Tape Structure                                                    0.2      0.2        0.2
                                    Young’s Modulus (GPa)
                                    Rigid Structure                                                    45       45         45
                                    Buildup with Reinforcement Material                                35       35         35
              State of the Art Buildup without Reinforcement Material                                  6         6          6
                                    Tape Structure                                                     3         3          3
                                    Ceramics Structure                                              50-400   50 – 400   50 – 400
                                    Peel Strength from Cu (kN/m)
                                    Rigid Structure                                                   1.6      1.6        1.6
              State of the Art Buildup Structure Buildup Layer                                        1.6      1.6        1.6
                                    Tape Structure                                                    1.4      1.4        1.4
             State of the art materials may not be compatible with cost requirements for volume production
             Water absorption test is: JIS C6481
             Peel strength test: IPC TM650 2.4.8

                                       Manufacturable solutions exist, and are being optimized
                                                         Manufacturable solutions are known
                                                                  Interim solutions are known 
                                                   Manufacturable solutions are NOT known
 2010      2011      2012

  350       350       350
  250       250       250
  350       350       350

  2.7       2.7       2.7
  2.5       2.5       2.5
  2.2       2.2       2.2
   3         3         3
  100       100       100

 0.006     0.006     0.006
 0.002     0.002     0.002
 0.0001    0.0001    0.0001
 0.0005    0.0005    0.0005

   6         6         6
   4         4         4
   10        10        10
 4 – 12    4 – 12    4 – 12

   15        15        15
   10        10        10
   10        10        10
 4 – 12    4 – 12    4 – 12

  0.04      0.04      0.04
  0.04      0.04      0.04
  0.1       0.1       0.1
  0.2       0.2       0.2

   45        45        45
   35        35        35
    6        6          6
    3        3          3
50 – 400   50-400   50 – 400

  1.6       1.6       1.6
  1.6       1.6       1.6
  1.4       1.4       1.4

				
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