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Superconductor Technologies
for
Extreme Computing
Arnold Silver
Workshop on Frontiers of Extreme Computing
Monday, October 24, 2005
Santa Cruz, CA
A. Silver 1
Outline
Introduction
Single Flux Quantum (SFQ) Technology
State-of-the-Art
Prospects
Quantum Computing
Summary
A. Silver 2
Notional Diagram of a Superconductor Processor
Ambient Electronics
Wideband I/O Cryogenic Superconductor
RAM Processors
4 Kelvin
High Speed Cryogenic Switch Network
Superconductor processors communicate with local cryogenic RAM and with
the cryogenic switch network.
Cryogenic RAM communicates via wideband I/O with ambient electronics.
A. Silver Introduction 3
Early Technology Limited
Early superconductor logic was voltage-latching
– Voltage state data
– AC power required
– Speed limited by RC load and reset time (~GHz)
Single Flux Quantum (SFQ) is latest generation.
– Current/Flux state data
– SFQ pulses transfer data
– DC powered
– Higher speed (~100 GHz)
Incremental progress on DoD contracts.
– Small annual budgets
– Focus on small circuit demos
– Minimal infrastructure investment
A. Silver Introduction 4
SFQ Features
Quantum-mechanical devices
An “electronics technology”
High speed and ultra-low on-chip power dissipation
– Fastest, lowest power digital logic
– ≥ 100 GHz clock expected
– ~ nW/gate/GHz expected
Wideband communication on-chip and inter-chip
– Superconducting transmission lines
Low- loss
Low-dispersion
Impedance matched
– 60 GHz data transfer demonstrated with negligible cross-talk
Comparison of a 12 GFLOPS SFQ and CMOS chip
40 kgate SFQ chip 50 GHz clock 2 mW Plus 0.8 W cooling power
2 Mgate CMOS chip 1 GHz clock 80 W Also requires cooling
A. Silver Introduction 5
Some Issues Need To Be Addressed
Present disadvantages
– Low chip density and production maturity
– Inadequate cryogenic RAM
– Cryogenic cooling
– Cryogenic - ambient I/O
Density and maturity will increase with better VLSI
Promising candidates for cryogenic RAM
– Hybrid superconductor-CMOS
– Hybrid superconductor-MRAM
– SFQ RAM
Cryogenics is an enabler for low power
Options for wideband I/O exist
A. Silver Introduction 6
Technology Overview
Basic technology
– Josephson tunnel junctions and SQUIDs
– SFQ logic gates
– SFQ transmitters-receivers
– Cryogenic memory
– Superconducting films produce microstrip and stripline transmission
lines
• Zero-resistance at dc (no ohmic loss)
• Low-loss, low-dispersion at MMW frequencies
• Impedance-matched
• Wideband
Enabling technologies
– Advanced VLSI foundry
– Superconducting multi-chip modules
– Wideband I/O technologies
• Optical fiber
• Electrical ribbon cable
• Cryogenic LNAs
A. Silver SFQ Technology 7
Comparison of SFQ - CMOS Functions
Function CMOS SFQ
Basic Switch Transistor Josephson tunnel junction (a 2 terminal device)
Data Format Voltage level Identical picosecond (current) pulses
Asynchronous flip-flop, static divider
Speed Test Ring oscillator 770 GHz achieved
1,000 GHz expected
Data Voltage data bus “Ballistic” transfer at ~ 100 m/ps in nearly lossless and
Transfer RC delay with power dissipation dispersion-free passive transmission lines (PTL)
Clock Clock pulse regeneration and ballistic transfer at
Voltage clock bus
Distribution ~ 100 m/ps in nearly lossless and dispersion-free PTLs
Logic Switch Complementary transistor pair Two-junction comparator
Bit Storage Charge on a capacitor Current in a lossless inductor
Fan-In,
Large Small
Fan-Out
Power Volt levels Millivolt levels
Power
Ohmic power bus Lossless superconducting wiring
Distribution
Noise ≥ 300 K thermal noise 4 K thermal noise that enables low power operation
A. Silver SFQ Technology 8
Josephson Tunnel Junction
J JC sinq
h
V f
2e
1 dq
f
2 dt
Magnetic field h
q Insulator (~1 nm) 0 2.07mv ps
2e
Damping Parameter
bc
2
0
ICRd RdC
bc > 1 bc < 1
IC
IC
A. Silver SFQ Technology 9
SQUIDs Are Basic SFQ Elements
Combine flux quantization with the non-linear Josephson
effects
Store flux quantum or transmit SFQ pulse
Li circ
2 q JJ 2k ; k = integer
o junctions
Flux
Inductor 0
JJ JJ
0 Input
Double JJ (dc) SQUID
A. Silver SFQ Technology 10
SFQ Is A Current Based Technology
Ibias
~1mV
Input JJ ~2ps
When (Input + Ibias) exceeds JJ SFQ pulses propagate along
critical current Ic, JJ “flips”, impedance-matched passive
producing an SFQ pulse. transmission line (PTL) at the speed
Area of the pulse is 0=2.067 mV-ps of light in the line (~ c/3).
Pulse width shrinks as JC increases
SFQ logic is based on counting Multiple pulses can propagate in PTL
single flux quanta simultaneously in both directions.
A. Silver SFQ Technology 11
SFQ Gates
Clock
Data
Data Latch (DFF) “OR” Gate (merger) “AND” Gate
SFQ pulse is stored in a Pulses from both inputs Two pulses arriving
larger-inductance loop propagate to the output “simultaneously”
Clock pulse reads out stored switch output junction
SFQ DFF in each input
If no data is stored, clock produces clocked AND
pulse escapes through the gate
top junction
PTLs transmit clock and data signals
Average number of junctions per gate is 10
A. Silver SFQ Technology 12
SFQ Is The Fastest Digital Technology
Static Divider Speed (GHz)
1000
NGST-Nb
300 NGST-NbN
HYPRES
SUNY
100
Toggle Flip-Flop – Static
Frequency Divider 1 10 100
Benchmark of SFQ circuit JC (kA/cm2)
performance
Measured dc to 446 GHz static divider
Maximum frequency scales with JC
770 GHz demonstrated in experiment
~2mV
Picosecond SFQ pulses can encode terabits per second.
~1ps
A. Silver SFQ Technology 13
SFQ Is The Lowest Power Digital Technology
One SFQ pulse dissipates IC 0 in shunt resistor
– For IC = 100 A 2 x10-19 Joule (~ 1eV)
– ~ 5 junctions switch in single logic operation
– 1 nW/gate/GHz 100 nW/gate at 100 GHz
Vbias
Static power dissipation in bias resistors: I2R
Ibias
For IC = 100 A biased at 0.7 IC
– Typical Vbias = 2 mV (to maximize bias margin)
– 140 nW/JJ, 1400 nW/gate is 23 X the dynamic power
Vbias
Voltage-biased SFQ gates will eliminate
Data
bias resistors and static power dissipation
– Self-clocked complementary logic
– Incorporates clock distribution circuitry
– Vbias = 0FClock
A. Silver SFQ Technology 14
SFQ Digital ICs Have Been Developed
First SFQ circuit (~ 1977) was a dc to SFQ converter
integrated with toggle flip-flops to form a binary counter.
Extensive development of SFQ logic did not occur until
after 1990.
Advanced SFQ logic was developed on HTMT FLUX.
– Architecture
– Design tools
– LSI fabrication
– Logic
– High data-rate on-chip communications
– Inter-chip communications
– Vector registers
– Microprocessor logic chip
A. Silver State-of-the-Art 15
Superconductor IC Fabrication Is Simpler Than CMOS
Wire 3
Wire 2
Wire 1 Wire 2
Silicon Wafer
Josephson Junction MoNx 5/sq. Resistor
Ground Plane Mo/Al 0.15Ω/sq. Resistor
Legend: Nb SiO2 Nb2O5 Junction Anodization
2 nm Al oxide 100 nm Nb Counter Electrode
Tunnel Barrier
150 nm Nb Base Electrode
8 nm Al Oxide
Oxidized silicon wafers (100-mm)
1. Deposit films (Nb trilayer, Nb wires, resistors, and oxide)
2. Mask (g-line, i-line photolithography or e-beam)
3. Etch (dry etch, typical gases are SF6, CHF3 + O2, CF4)
4. Repeated 14 to 15 times
No implants, diffusions, high temperature steps
Trilayer deposition forms Josephson tunnel junction
All layers are deposited in-situ
Al is passively oxidized in-situ at room temperature
1 m minimum feature, 2.6 m wire pitch
Throughput limited by deposition tools
A. Silver State-of-the-Art 16
Cadence-based SFQ Design Flow (NGST)
Is similar to Semiconductor Design
Logic Synthesis & Verification
VHDL DRC
LVS
Schematic Layout
RSFQ Gate Library Gate
PCells
LMeter
VHDL
Schematic Symbol Layout
Structure
Malt
WRSpice
VHDL
Netlist
Generic
A. Silver State-of-the-Art 17
Complex Chips Have Been Reported
Function Complexity Speed Cell Library Organizations
FLUX-1. 8-bit P Yes.
prototype. 63 K Junctions. Designed for 20 GHz. Incorporates Northrop Grumman,
25 30-bit-dual-op 10.3 mm x 10.6 mm. Not tested. drivers/receivers for Stony Brook, JPL
instructions. PTL.
CORE110. 21 GHz local clock. Yes. ISTEC-SRL,
7 K Junctions.
8-bit bit-serial P. 1 GHz system clock. Gates connected by Nagoya U.,
3.4 mm x 3.2 mm.
7 8-bit instructions. Fully functional. JTLs and/or PTLs Yokohama National U.
Yes.
MAC and Prefilter for
6 K–11 K Junctions. Gates connected by
programmable pass- 20 GHz design Northrop Grumman
5 mm x 5 mm. parameterized JTLs
band A/D converter.
and/or PTLs
A/D converter 6 K Junctions. 19.6 GHz. ? Hypres
Digital receiver 12 K Junctions. 12 GHz. ? Hypres
4K bit. 32 bits tested at
FIFO buffer memory No Northrop Grumman
2.6 mm x 2.5 mm 40 GHz.
128 x 128 switch. NSA, Northrop
X-bar switch 2.5 Gbps. No
32 x 32 module. Grumman
SFQ X-bar switch 32 x 32 module. 40 Gbps. No Northrop Grumman
A. Silver State-of-the-Art 18
FLUX-1 Microprocessor Chip
• Objective to demonstrate of 5K Gate
SFQ chip operating at 20 GHz
• 8-bit microprocessor design
• 1-cm chip
• 8 - 20 Gb/s transmitters, receivers
• FLUX-1 chip redesigned, fabricated,
partially tested
• 1.75 m, 4 kA/cm2 junction Nb
technology
• 20 GHz internal clock
• 5 GByte/sec inter-chip data transfer
limited by P architecture
• Scan path diagnostics included
• 63 K junctions, 5 Kgate equivalent
• Power dissipation ~ 9 mW @ 4.5K
• 40 GOPS peak computational
capability (8-bits @ 20-GHz clock)
• Fabricated in TRW 4 kA/cm2 process
in 2002
8-20 Gb/s receivers
8-20 Gb/s transmitters
A. Silver State-of-the-Art 19
60 GHz Interconnect Demonstrated
Chip-to-MCM Pad Optimization
Micro-strip 100 m pad, 100 m space
chip 1 Interconnect chip 2
gsg gsg S 0
S12 (dB)
Chip-side MCM-side
G G
microstrip microstrip
Active circuitry S
Passive MCM
on chip G G -3
0 50 100 150 200
Frequency (GHz)
Measured Bit-error Rate MCM Nb stripline wiring is low loss, wideband
1
1e-01 60 High density, low impedance solder bump arrays
1e-02 50
40 Ultra-low power driver-receiver enables high data
PRN Bit-error Rate
1e-03
30 rate communications
1e-04 20
1e-05 10 SFQ data format enables multiple bits in
1e-06 transmission line simultaneously, increases
1e-07 throughput
1e-08
1e-09 Demonstrated to 60 Gb/s through 2 solder bumps,
1e-10 4 resistor, and 4 transmission lines on chip
1e-11 and MCM
1e-12 Timing errors produced BER floor above 30 Gb/s
-20 0 20 40 60 80 100 120 140
Receiver Bias Current (µA)
A. Silver State-of-the-Art 20
SFQ Faces Challenges of 100+ GHz Technologies
Low power
– Low fan-out, need “pulse splitting”:
• JTL provides current amplification IC=100A
• Amplified pulse can drive two JTLs
– All connections are point-to-point
– Fast, large RAM is hard to make IC=141A
High speed IC=100A
– No global clock
• Clock and data pulses are considered to be the same
• Need to consider asynchronous/delay insensitive/self-timed/micropipelined
– On-chip latencies can reach many clock cycles
• 10 ps clock period in PTL corresponds to 2 mm length
• Pulse splitting adds latency
On the cutting edge
– No truly automated place-and-route yet
– Off-the-shelf CAD tools need to be heavily customized
– Efficient gate library approach has to be refined
Requirement for wideband I/O to ambient RAM
A. Silver Prospects 21
Improved Chip Performance Feasible
Improve parameters by orders- Establish foundry following
of-magnitude CMOS practice
+ Increase junction and gate density Lithography at 250-180 nm; 90-60 nm
+ Increase clock frequency JC >20 kA/cm2; ≥100 kA/cm2
+ Increase junction speed to 1,000 Add superconducting layers 7-9; >20
Vertically separate power and data
GHz by increasing JC ≥ 100 kA/cm2
transmission from gates
+ Increase chip yield
Achieve ≥1M junctions/cm2 (≥105 gates);
– Reduce power dissipation to SFQ 100-250M junctions/cm2 (10-25M gates)
switching dissipation level Increase clock to 50 GHz; ≥100 GHz
– Reduce bias current Improve CAD tools and methods
May need to improve physical models
for junctions with higher JC
Shorten development time
A. Silver Prospects 22
Density Is Increased by Adding Wiring Layers
More metal layers are essential to increase
chip density
Vertically isolate power and communications
lines from active devices
Superconducting ground planes are excellent
shields
Full planarization and competitive lithography
IBM 90-nm Server-Class
CMOS process
Fully-Planarized, 6-Metal
Process (Proposed by
ISTEC-SRL, Japan,
Nagasawa et al., 2003)
A. Silver Prospects 23
SFQ Technology Projections
Before 2004 2010 Beyond 2010
Technology Projections
Technology Node 1 m 250 - 180 nm 90 nm or better
Current Density 8 kA/cm2 50 kA/cm2 > 100 kA/cm2
Superconducting Layers 4 7-8 ~ 20
Alternate barriers
New Process Elements NA Full Planarization Additional junction trilayers
Vertical resistors and inductors
CMOS-like
Power ICVbias Reduced Bias Voltage Reduced IC
Projected Chip Characteristics
Junction Density 60 k/cm2 2 - 5 M/cm2 100-250 M/cm2
Clock Frequency < 20 GHz 50 - 100 GHz 100 - 250 GHz
Power 0.2 W/Junction 8 nW/GHz/Junction 0.4 nW/GHz/Junction
Increased Clock Frequency Increased Density
Smaller line pitch
Process Improvement Smaller junction with higher JC
Greater vertical integration
Faster circuits More gates/cm2
Benefits
Larger signals Reduced on-chip latency
Possibly larger spreads
Potential Disadvantages Potentially lower yield
Increased system latency
Latency is measured in clock ticks
A. Silver Prospects 24
Gate Access Within Clock Period Is Important
Clock radius (RCL) is
maximum distance data
can travel within a clock
period.
NCL is number of gates
within a clock radius.
Clock radius is limited by
time-of-flight and the
clock frequency.
Increasing gate density is
essential to increasing NCL
effectiveness.
RCL
A. Silver Prospects 25
Density Is Clock
25 50 100 200 250
(GHz)
Key To Gate Clock Radius
4 2 1 0.5 0.4
(mm)
Access Clock Area
50 12.6 3.14 0.79 0.5
(mm2)
Density Density
Number of Gates Within Clock Radius (NCL)
(JJs/cm2) (Gates/mm2)
5K 5 250 63 16 4 2.5
60 K 60 3K 750 190 47 30
1M 1K 50 K 13 K 3.1 K 790 500
5M 5K 250 K 63 K 16 K 4K 2.5 K
30 M 30 K 1.5 M 380 K 94 K 24 K 15 K
100 M 100 K 5M 1.3 M 310 K 79 K 50 K
250 M 250 K 12.5 M 3.1 M 790 K 200 K 130 K
Clock radius assumed to be 1/2 of time-of-flight.
A. Silver Prospects 26
High-End SFQ Computing Engine
2005
Not feasible
~ 100 chips per processor
0.5 M processor chips, ~ 109 gates
2010
~ 10 chips per processor
40 K processor chips, ~ 109 gates
After 2010
~ 10 to 20 processors per chip
400 processor chips, including embedded memory
A. Silver Prospects 27
Applications to Quantum Computing
Quantum computing is being investigated
using superconducting qubits.
Flux-based superconducting qubits are
physically similar to SFQ devices.
SFQ circuits are best candidates to
control/read superconducting qubits at
millikelvin temperatures.
A. Silver SFQ and Quantum Computing 28
Summary
SFQ needs major engineering development in
chip technology if it is going to be a player in
high-end computing.
The engineering requirements are understood
and a development plan defined.
Prospects are exciting and achievable.
A. Silver Summary 29
