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Finite State Machines and Their

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Finite State Machines and Their Powered By Docstoc
					                          Experiment 7

  VHDL Modeling of Embedded
     Microprocessors and
       Microcontrollers


ECE 448 – FPGA and ASIC Design with VHDL   George Mason University
            Simple Microprocessor




ECE 448 – FPGA and ASIC Design with VHDL   George Mason University
 Basic Architecture
• Control unit and
  datapath
                                                                            Processor
   • Note similarity to                                  Control unit                                    Datapath
     single-purpose                                                                                        ALU

     processor                                            Controller                    Control
                                                                                        /Status

• Key differences
                                                                                                         Registers
   • Datapath is
     general
   • Control unit
                                                   PC                     IR


     doesn’t store the
     algorithm – the                                                                      I/O
                                                                               Memory
     algorithm is
     “programmed”
                                  Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"
     into the memory
ECE 448 – FPGA and ASIC Design with VHDL                                                                                  3
  Instruction Cycles

PC=100                                                                                 Processor

  Fetch Decode Fetch Exec. Store                                       Control unit                                  Datapath
               ops         results                                                                                     ALU
clk                                                                     Controller                 Control
                                                                                                   /Status


                                                                                                                     Registers



                                                                                                                     10
                                                                  PC 100             IR                         R0        R1
                                                                               load R0, M[500]



                                                                                                    I/O

                                                                    100 load R0, M[500]    Memory
                                                                                                                 ...
                                                                                                          500    10
                                                                    101    inc R1, R0                     501
                                                                    102 store M[501], R1                         ...

ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                                               4
  Architectural Considerations
• Clock frequency
                                                                                        Processor
      • Inverse of clock                                              Control unit                             Datapath

        period                                                                                                   ALU
                                                                       Controller                    Control
      • Must be longer                                                                               /Status


        than longest                                                                                           Registers

        register to
        register delay in                                        PC                    IR

        entire processor
      • Memory access                                                                                 I/O
                                                                                            Memory
        is often the
        longest
ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                                         5
  A Simple (Trivial) Instruction Set

               Assembly instruct.            First byte             Second byte              Operation


               MOV Rn, direct              0000       Rn                direct         Rn = M(direct)


               MOV direct, Rn              0001           Rn            direct         M(direct) = Rn


               MOV @Rn, Rm                 0010       Rn           Rm                  M(Rn) = Rm

               MOV Rn, #immed.             0011       Rn             immediate         Rn = immediate

               ADD Rn, Rm                  0100       Rn           Rm                  Rn = Rn + Rm

               SUB Rn, Rm                  0101       Rn           Rm                  Rn = Rn - Rm

               JZ Rn, relative             0110       Rn              relative         PC = PC+ relative
                                                                                        (only if Rn is 0)
                                           opcode               operands




ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                          6
  Addressing Modes
     Addressing                                                       Register-file       Memory
       mode                       Operand field                        contents           contents



     Immediate                        Data


   Register-direct
                                 Register address                         Data


      Register
                                 Register address                   Memory address          Data
      indirect


       Direct                    Memory address                                             Data


      Indirect                   Memory address                                        Memory address


                                                                                            Data




ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                      7
  Sample Program
                      C program                                          Equivalent assembly program

                                                                 0       MOV R0, #0;            // total = 0
                                                                 1       MOV R1, #10;           // i = 10
                                                                 2       MOV R2, #1;            // constant 1
                                                                 3       MOV R3, #0;            // constant 0
               int total = 0;
                                                               Loop:     JZ R1, Next;           // Done if i=0
               for (int i=10; i!=0; i--)
                  total += i;                                    5       ADD R0, R1;            // total += i
               // next instructions...                           6       SUB R1, R2;                // i--
                                                                 7       JZ R3, Loop;               // Jump always

                                                               Next:      // next instructions...




ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                                   8
Architecture of a Simple Microprocessor
• Storage devices for each
  declared variable
                                                                                          Datapath
   • register file holds each                 Control unit                    To all
                                                                              input        RFs
                                                                                                    1
                                                                                                       2x1 mux
                                                                                                              0


      of the variables                                                        control
                                                                              signals
                                                                                           RFwa          RFw
• Functional units to carry                                Controller
                                                        (Next-state and
                                                             control          From all
                                                                                           RFwe
                                                                                                        RF (16)
  out the FSMD operations                             logic; state register)  output
                                                                              control
                                                                                           RFr1a


   • One ALU carries out                                         16
                                                                              signals      RFr1e

                                                                                           RFr2a
      every required                         PCld
                                             PCinc
                                                      PC             IR
                                                                                 Irld
                                                                                           RFr2e
                                                                                                   RFr1        RFr2

      operation                              PCclr
                                                                                           ALUs
                                                                                                         ALU
• Connections added                                 2       1         0
                                                                                           ALUz


  among the components’                      Ms
                                                         3x1 mux             Mre Mwe
  ports corresponding to
  the operations required
  by the FSM                                                 A                     Memory       D



• Unique identifiers created
  for every control signal Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"
 ECE 448 – FPGA and ASIC Design with VHDL                                                                           9
  A Simple Microprocessor

              Reset     PC=0;                                 PCclr=1;


              Fetch     IR=M[PC];                             MS=10;                                                                     Datapath   1
                                                                                               Control unit                  To all                              0
                        PC=PC+1                               Irld=1;                                                                     RFs
                                                                                                                             input                      2x1 mux
Decode                      from states                       Mre=1;
                                                                                                                             contro
                            below                             PCinc=1;
                                                                                                                             l
                                                                                                                             signals      RFwa
                      Mov1        RF[rn] = M[dir]             RFwa=rn; RFwe=1; RFs=01;                      Controller                                     RFw
         op = 0000                  to Fetch                  Ms=01; Mre=1;                               (Next-state and                 RFwe
                                                                                                              control        From all                   RF (16)
                      Mov2        M[dir] = RF[rn]             RFr1a=rn; RFr1e=1;                                             output
                                                                                                            logic; state                  RFr1a
             0001                  to Fetch                   Ms=01; Mwe=1;                                                  control
                                                                                                             register)
                                                                                                                             signals      RFr1e
                      Mov3        M[rn] = RF[rm]              RFr1a=rn; RFr1e=1;
             0010                  to Fetch                   Ms=00; Mwe=1;                                       16                      RFr2a
                                                                                              PCld                             Irld
                                  RF[rn]= imm                 RFwa=rn; RFwe=1; RFs=10;                PC               IR                           RFr1         RFr2
                      Mov4                                                                                                                RFr2e
             0011                   to Fetch                                                  PCinc
                                                                                                                                          ALUs
                      Add         RF[rn] =RF[rn]+RF[rm]       RFwa=rn; RFwe=1; RFs=00;        PCclr
             0100                                                                                                                                          ALU
                                    to Fetch                  RFr1a=rn; RFr1e=1;                                                          ALUz
                                                              RFr2a=rm; RFr2e=1; ALUs=00              2      1         0
                       Sub        RF[rn] = RF[rn]-RF[rm]      RFwa=rn; RFwe=1; RFs=00;
             0101                   to Fetch                  RFr1a=rn; RFr1e=1;
                                                              RFr2a=rm; RFr2e=1; ALUs=01      Ms
                                                              PCld= ALUz;                                  3x1 mux          Mre Mwe
                       Jz         PC=(RF[rn]=0) ?rel :PC
             0110                   to Fetch                  RFrla=rn;
                                                              RFrle=1;
                                                    FSM operations that replace the FSMD
                      FSMD
                                                     operations after a datapath is created                                     Memory
                                                                                                              A                                 D
             You just built a simple microprocessor!



ECE 448 – and Givargis, "Embedded System Design:VHDL Hardware/Software Introduction"
 Source: Vahid FPGA and ASIC Design with A Unified                                                                                                                      10
                 PIC Microcontroller




ECE 448 – FPGA and ASIC Design with VHDL   George Mason University
     PIC Microcontroller implemented inside of
                an FPGA device
         FPGA

                                                               CLK

                                                PIC            RESET
                                             µController
                                                               STROBE = PORTC(0)
                                                       PORTC

                                           PORTB       PORTA



                                       7-Seg Decoder




                                           Display     PORTA

ECE 448 – FPGA and ASIC Design with VHDL                                       12
  PIC Microcontroller Core
                                                                                    MCLR   CLK

       PROGRAM

                                                                             CONTROL
         PICROM           8   P                                                UNIT
          256 x 12 Addr       C        Address Bus
           Data
                                                                       DATA
               12                                                  REGFILE
                                                                        R8
  Instruction Decoder                                           Fsel

     8              4                  8                               R31
    CONSTANTS       OPCODES                             FSR
                                                                 Din         Dout

                                           Data Bus     8
   W        ALU

                 EXTENDED                  4            8               8
    COMPUTATIONS   ALU                PORTA           PORTB        PORTC

                                           4                8           8
ECE 448 – FPGA and ASIC Design with VHDL                                                    13
 Flowchart of our PIC program

                             RESET


                      Set Port Directions


                          Sum <= ‘0’
                         Counter <= ‘0’          Wait for a rising edge at
                                                        Port C(0)
                    Wait for a rising edge at
                           Port C(0)
                                                Port B <= Sum(3 downto 0)

       N               Port B <= Port A
                     Sum <= Sum + Port A         Wait for a rising edge at
                    Counter <= Counter + 1              Port C(0)


                                            Y   Port B <= Sum(7 downto 4)
                          Counter = 8?




ECE 448 – FPGA and ASIC Design with VHDL                                     14
 Selected Registers of PIC
         ADDR
                   W                      Working Register (Accumulator)

                   PC                     Program Counter

           05   PORTA
           06   PORTB                                Bidirectional
           07   PORTC                             Input/Output Ports

           08     R8
           09     R9
           0A     R10
            .                                       Register File
            .                                     (General Purpose
                                                     Registers)
           1E      R30
           1F      R31

               TRISA
                                                    Direction Registers
               TRISB
                                                     for Ports A, B & C
               TRISC

ECE 448 – FPGA and ASIC Design with VHDL                                    15
 Selected PIC Instructions (1)

 MOVF f, d
                                           MOVF f, 1
                             f                              f  <8,31>
           MOVF f, 0
                                                            k  <0,255>
                            W

 MOVWF f                                   MOVLW k
                            W                               k
               MOVWF f                            MOVLW k

                             f                              W

ECE 448 – FPGA and ASIC Design with VHDL                                 16
 Selected PIC Instructions (2)
                              0
 CLRF f                           CLRF f

                             f             f  <8,31>


                              0
 CLRW                             CLRW

                            W




ECE 448 – FPGA and ASIC Design with VHDL                17
 Selected PIC Instructions (3)

 INCF f, d

                             f

                            +1
                                    INCF f,1

                                 INCF f,0

                            W




ECE 448 – FPGA and ASIC Design with VHDL       18
 Selected PIC Instructions (4)

 ADDWF f, d



                                   W           f

        ADDWF f, 0                                 ADDWF f, 1
                                           +




ECE 448 – FPGA and ASIC Design with VHDL                        19
 Selected PIC Instructions (5)

 ANDWF f, d



                                  W              f

         ANDWF f, 0                                  ANDWF f, 1
                                           and




ECE 448 – FPGA and ASIC Design with VHDL                          20
 Selected PIC Instructions (6)

 SWAPF f, d
                                           SWAPF f, 1



                           fH         fL
                                       SWAPF f, 0

                                W




ECE 448 – FPGA and ASIC Design with VHDL                21
 Selected PIC Instructions (7)
 CALL label                                GOTO label

 RETLW
                                           CALL label
                        CALL label         GOTO label




                                           label
                        label              label



                        RETLW




ECE 448 – FPGA and ASIC Design with VHDL                22
 Selected PIC Instructions (8)

 BTFSC f, b
                            f

                   7        b        0


             f(b) = 0?          BTFSC f, b
                       No
                                Next instruction
             Yes
                                After-next Instruction




ECE 448 – FPGA and ASIC Design with VHDL                 23
 Selected PIC Instructions (8)

 BTFSS f, b
                            f

                   7        b        0


             f(b) = 1?          BTFSS f, b
                       No
                                Next instruction
             Yes
                                After-next Instruction




ECE 448 – FPGA and ASIC Design with VHDL                 24
 Selected PIC Instructions (9)

 TRIS f                                     W



               TRIS PORTA                                    TRIS PORTC
                                                TRIS PORTB

                TRISA                      TRISB                  TRISC

                   4                        8                      8



            1 – Input port bit direction

            0 – Output port bit direction



ECE 448 – FPGA and ASIC Design with VHDL                                  25
 PIC Programming Environment
                                                   Source File in the PIC
                                           *.ASM
                                                   Assembly Language




                                           MPASM



    HEX File         *.HEX                              *.LST      Listing File




                                                       MPSIM




ECE 448 – FPGA and ASIC Design with VHDL                                          26
 Questions?




ECE 448 – FPGA and ASIC Design with VHDL   27

				
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