ENGG Microcomputer Interfacing

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					       ENG3640
Microcomputer Interfacing



        Week #9
 Serial Communications
Topics
   Serial I/O Background
   Asynchronous Communications
   The SCI Interface
   Synchronous Communications
   The SPI Interface
   SPI Topologies and Applications




                     ENG3640 Fall 2010   2
Resources

   Huang, Chapter 9, Sections
       9.1 Objectives
       9.2 Fundamental Concepts of Serial Communication
       9.3 The RS-232 Standard
       9.4 The 68HC12 Serial Communication Interface
       9.5 Interfacing SCI with EIA-232
       9.6 The SPI Function
       9.7 Registers Related to the SPI Subsystem
       9.8 SPI Circuit Connection

                         ENG3640 Fall 2010             3
                   1-KB SRAM
                 4-KB EEPROM            Port AD
68HC812A4           CPU12           Analog to Digital
   Block
 Diagram                                Port T
                                     Timer Module
                                        Port S
                                        Serial
                                     Communication




            I/O Ports

                               I/O Ports




                                                        4
Parallel and Serial Transmission

        Two types of transmission are widely used today:
        Parallel Transmission (busses)
    1.     Data is transmitted in one pulse (fast)
    2.     Usually used for short distances (Why?)
            Bulky and expensive (many I/O lines).
            Susceptible to reflection and induced noise.
            Many I/O devices do not have a high enough data rate to justify
             the use of parallel data transfer.
        Serial (RS-232, USB)
    1.     Serial by bit (slow)
    2.     Each bit takes one pulse
    3.     Generally used for longer distances
    4.     Cheap
                                  ENG3640 Fall 2010                            5
The Serial I/O Port
                                          The port contains a bus
                                           interface through which
                                           the microprocessor can
                                      1.     Send commands to the
                                             port.
                                      2.     Read port status
                                      3.     Access input/output data
                                             registers in the port.
                                          What distinguishes this
                                           port from the general
                                           structure of an I/O port is
                                           the conversion that occurs
                                           between serial and
                                           parallel data streams.




              ENG3640 Fall 2010                                      6
    Serial I/O Background
   Transmitter encodes a data signal to be sent to the receiver.
       The timing of the data signal is based on the transmitter clock fT
   The receiver samples the serial signal to detect/decode the data.
       The timing of the receiver sampling is based on a receiver clock fR
   In order to catch every data bit the receiver sampling times
    must be synchronized to the transmitted signal in some way!
       Synchronization techniques: (a) Synchronous (b) Asynchronous


                          Serial Communication Link



             Transmitter                               Receiver

                                   ENG3640 Fall 2010                          7
Modes of Channel Operation
                               Transmission is unidirectional.
                               Usually called receive only
                                transmission.
                               Example TV, Radio, PC  Printer


                               Transmission is possible in both
                                direction but not at the same time.
                               People communication in half-
                                duplex.
                               EX: Multiple computers connected
                                together talking

                               Full Duplex allows information
                                (data) to be transferred
                                simultaneously in both directions.
                               EX: Standard Telephone.


            ENG3640 Fall 2010                                    8
Traditional Configurations

                                         Host communicates with the
                                          terminals using a dedicated link.
                                         Terminals can communicate with
                                          each other via host only.




                                 Host communicates with the
                                  terminals using a shared
                                  connection.
                                          Terminals have to identify if data is
                                           intended to them (address)
                                 Other Topologies?
                                          Star, Mesh, Ring



              ENG3640 Fall 2010                                               9
The Serial Subsystems

         MCU12 has 2 subsystems for serial interfacing
    I.        An Asynchronous Serial Communication Protocol:
               The serial communication interface (SCI) that can be used
                to connect a terminal or personal computer to the
                microcontroller (used in our EVB Boards)
    II.       A Synchronous Serial Communication Protocol:
               The serial peripheral interface (SPI) can provide high-
                speed serial communication to peripherals or other
                microcontroller units
               Proposed by Motorola to facilitate the data exchange
                between microcontrollers and peripheral devices.


                                 ENG3640 Fall 2010                     10
I. Synchronous Serial Communication
   Synchronous communication systems always transmit a clock signal
    with the data to synchronize the receiver to each bit time.
   The clock is provided as a separate clock signal or it can be
    embedded in the data signal itself.

                   Transmitter                   Receiver




                      CLK




                             ENG3640 Fall 2010                   11
Principle Binary Codes
                                    There are many ways to
                                     encode data (i.e. identify
                                     marks (1) and the spaces (0)).
                                  1.    NRZ
                                  2.    NRZI
                                  3.    RZ
                                  4.    CMI
                                  5.    Manchester
                                  6.    Diff Manchester
                                    They are called coding types
                                     or modulation formats.




              ENG3640 Fall 2010
                                                               12
I. Synchronous Serial Communication
   The clock is provided as a separate signal or it can be
    embedded in the data signal itself.
     Two common ways to embed a clock into the data signal
      are to use (i) Manchester or (ii) variable pulse width
      signaling.
     Notice signal change in middle of every bit  used by
      receiver to synchronize the sampling process.




                         ENG3640 Fall 2010                13
Manchester Data Encoding




             ENG3640 Fall 2010
                                 14
Manchester Data Encoding
   A Clock extraction circuit is based upon a phase-locked loop (PLL)
   A VCO initially runs at a frequency close to the expected data rate.
   The phase detector compares the phase of VCO with incoming data.
   When not in phase an error proportional to frequency difference adjusts
    the VCO to match or lock to incoming data signal
   Reciever has now the capability of timing its decision circuit at exactly
    the rate of the data and in the center of the bit period.




                                 ENG3640 Fall 2010                         15
Synchronous: Separate Clock Signals
        Other synchronous serial communication systems send the
         synchronization clock as a separate clock signal.
          The clock’s rising edge always falls in the center of the data bit time.
          Examples: Motorola SPI, Phillips I2C, National MicroWire.
        The advantage of using a separate clock:
    1.     Circuit Simplicity (rising edge triggered shift register)
    2.     Data rate does not have to be fixed
        The disadvantage?
    1.     A Separate clock signal is required (long distance, expensive, reliability!)




                                       ENG3640 Fall 2010                              16
II. Asynchronous Serial Communication

   Each device uses its own clock.
       The clocks must run at the same rate but do not need to be
        synchronized.
       The receiver clock must be within 4% of the transmitter clock.




                                ENG3640 Fall 2010                        17
UART :
Universal Asynchronous Receiver Transmitter.


                                           The UART is the interface
                                            chip that implements serial
                                            data transmission.
                                           Also known as (ACIA)
                                            asynchronous
                                            communication interface
                                            adapter.
                                           If you need more serial ports
                                            you would use an UART to
                                            interface with your MCU.
                                           Six major components:
                                            1.   Chip select & read/write cont
                                            2.   Data bus buffers
                                            3.   Transmit data Register
                                            4.   Receive data Register
                                            5.   Status Register
                                            6.   Control Register
                    ENG3640 Fall 2010                                    18
    Asynchronous Data Frame
   The basic unit of information is the character or data
    frame
       A Frame is a complete and non divisible packet of bits.
        • It includes both information (data) and overhead (extra bits)

   Synchronization is achieved using Start-Stop bits.
       i.e. the receiver needs to know when a character starts and when it
        stops => character is framed by start and stop bits
            Idle time




                                 ENG3640 Fall 2010                        19
Start and Stop Framing. Parity
   The transmitter can send characters at any rate, so there
    may be delays between the transmission of each
    character
   The receiver detects the falling edge of the start bit and
    then attempts to sample in the center of each bit time.
   Parity is used to detect single bit errors
     type: even or odd

     the quantity of 1 bits in the data determine the parity bit

   The receiver also needs to know (i) number of data bits
    in each character, (ii) type of parity used if any, (iii) number
    of stop bits.

                            ENG3640 Fall 2010                    20
Start, Stop and Parity Bits




               ENG3640 Fall 2010   21
 Example
      The letter `A’ is to be transmitted in the format
       with (i) 8 data bits (ii) no parity (iii) one stop bit
       Sketch the output
          The ASCII code for `A` is $41 or %01000001

                  1   0    0 0       0      0       1 0
                                                                           LSB


Idle
                                                                Stop Bit
  Start Bit
                          LSB                             MSB
                                ENG3640 Fall 2010                            22
 Example: Using RS-232
+15V


                                                                 time
0V

                                                      Using RS-232
-15V


                 1   0    0 0     0      0      1 0



Idle
                                                              Stop Bit
     Start Bit
                         LSB                          MSB
                                ENG3640 Fall 2010                        23
Example
        Show the framing bits when the char B (21)16
         is sent at 7 data bits, 2 stop bits, odd parity:
        Solution:
    1.    start bit: 0
    2.    data bits: 0100001
    3.    parity bit: 1
    4.    stop bits: 11

                    1 0 0 0 0 1 0 1



                          ENG3640 Fall 2010            24
Data Speed, Baud
        Two units of speed are employed in data
         transmission.
    1.    # of data bits transmitted per second (BPS)
    2.    Baud : the rate at which the signal changes
        For a binary two-level signal, a data rate of one bit
         per second is equivalent to one Baud.
         if a data transmission system uses signals with 16 possible
          discrete level, each signal can have 16 = 24 different values
          (i.e., signal element encodes 4 bits)
         Example: If the 16-level signals are transmitted at 1,200
          Baud, the data rate is 4 x 1,200 = 4,800 bps.
        Effective BPS = (nr of data bits)/(nr of frame bits) x
         baud
                              ENG3640 Fall 2010                     25
Example
     How long does it take to transmit one character at a
      speed of 9600 bauds? Each character is transmitted
      using a format of seven data bits, even parity, one stop
      bits.
     Solution:
    1. Each character consists of 10 bits (1 start, 1 stop, 1
        parity, 7 data)
         1.   Effective Data bit rate: 7/10 x 9600 = 6720 BPS
    2.   Each bit requires 104 uS = (1/9600)
    3.   Thus each character will require
         10 x 104uS = 1.04 mS


                                ENG3640 Fall 2010               26
The RS-232 Standard
        The RS-232 standard was established in 1960 by the Electronic Industry
         Association (EIA) for interfacing between a computer and a modem.
          The standard is referred to as either RS-232 or EIA-232
          In data communication terms, both computers and terminals are called data
           terminal equipment (DTE).
          Modems and routers are called Data Communication Equipment (DCE)
        There are four aspects to the EIA-232 standard
    1.     Electrical specifications -- specifies the voltage level, data rates, distance of
           communication
    2.     Mechanical Specifications – specify the number of pins and the shape and
           dimensions of the connectors.
    3.     Functional Specifications – specify the function of each signal.
    4.     Procedural Specifications – specifies the sequence of events for transmitting
           data




                                        ENG3640 Fall 2010                                      27
Data Communications Interfacing




              ENG3640 Fall 2010   28
Modems
   Modems is a contraction                    the serial port, the RS-232
    of modulator-demodulator                    data terminal equipment
   Modem is used to send                       (DTE) -> connected to a
                                                modem, a data
    and receive serial
                                                communication equipment
    digital data over a                         (DCE) -> to a telephone line
    telephone line
                                               Transmission ...
   Basics of modems
                                               Receiving ...
   Modem is connected to a                    The audio signal is known as
    serial port                                 the carrier signal
       dedicated circuit
                                               Tech: PSK; DPSK; QAM



                            ENG3640 Fall 2010                            29
Carrier Modulations (Basics)




             ENG3640 Fall 2010   30
Carrier Modulations (Basics)




             ENG3640 Fall 2010   31
Differential Phase Modulation
   Phase is shifted by multiples of 90, therefore
    two bits at a time can be transmitted.




                                                 32
(1) The EIA-232 Electrical Specs
       The interface is rated at a signal rate less than
        20 KBPS. With good design, however, we can
        achieve a higher data rate.
       The signal can transfer correctly within 15
        meters. Greater distance can be achieved with
        good design.
       Driver maximum output voltage is -25V to +25V
        A voltage more negative than -3V at the receiver’s
         input is interpreted as logic one.
        A voltage more positive than +3V at the receiver’s
         input is interpreted as logic zero.

                           ENG3640 Fall 2010                  33
(2) The EIA-232 Mechanical Specs



                                            RJ45 (EIA-561) Connector




                                            DB9 (EIA574) Connector
 V.24/RS-232 DB25 Pin Connector

                        ENG3640 Fall 2010                            34
Cont .. Mechanical: The EIA-232
Cable




       The simplest RS232 cable uses just :
        TXD,
        RXD and
        Ground with optional ground shield.
           The shield provides protection from electric field interference.



                                  ENG3640 Fall 2010                            35
(3) Functional Specs
              I.           DSR (Data Set Ready)
              II.          RTS (Request to Send)
              III.         CLS (Clear to Send)
              IV.          RI (Ring Indicator)
              V.           TX (Transmit)
              VI.          RX (Receive)
              VII.         ….




                   ENG3640 Fall 2010               36
Cont … Functional Specs




            ENG3640 Fall 2010   37
Procedural Specification
    E.g. Asynchronous private line modem
     (Point-to-Point Link ``Not over the phone line”
    The modem will require only the following
     signals to operate:
    1.   GND,                               Computer         Modem
                                                             (DCE)
                                                                                            Modem
                                                                                            (DCE)
                                                                                                           Computer
                                                                                                            (DTE)
                                             (DTE)

    2.   Tx, Rx,                                 Tx
                                                 Rx
                                                            Tx
                                                            Rx
                                                                                                Tx
                                                                                                Rx
                                                                                                           Tx
                                                                                                           Rx
                                                DCD         DCD            Direct link         DCD         DCD
    3.   RTS, (Request to Send)                 CTS         CTS                                CTS         CTS
                                                RTS         RTS                                 RTS        RTS
    4.   CTS, (Clear to Send)                   DSR
                                                GND
                                                            DSR
                                                            GND
                                                                                                DSR
                                                                                               GND
                                                                                                           DSR
                                                                                                           GND

    5.   DSR, (Data Set Ready)              Tx: transmit data
                                            Rx: receive data
                                                                     CTS: clear to send
                                                                     RTS: request to send
                                            DCD: data carrier detect DSR: data set ready
    6.   DCD (Data Carrier Detect)                     Figure 9.2 Point-to-point asynchronous connection

                        ENG3640 Fall 2010                                                                    38
(2) Functional/Procedural Specs
I.      DSR (Data Set Ready)  From DCE (i.e Modem is ready)
II.     RTS (Request to Send)  DTE to DCE (i.e DTE Wants to send info)
III.    CLS (Clear to Send)  ACK from DCE (i.e Data may be transmitted now)
IV.     Local Computer (i.e., DTE) sends data serially to modem.
V.      Local Modem (i.e., DCE) modulates signal but before that sends a carrier
        signal to remote modem.
VI.     Remote Modem detects the carrier signal ring and asserts DCD to inform
        remote DTE that a call arrived.
VII.    DCD (Data Carrier Detect)  Remote Modem (i.e., DCE) indicates that a
        carrier frequency has been established.
VIII.   Remote Modem (i.e., DCE) receives modulated data, demodulates it and
        sends it to remote DTE.




                                 ENG3640 Fall 2010                           39
Sequence of events occurred during data transmission over dedicated link




                                                       Time
                Local                                                      Remote
                        1. DCE asserts DSR

2. DTE asserts RTS
                        3. DCE asserts CTS


4. DTE starts to send
  data (to local DCE)

                        5. DCE sends out a
                         carrier and then the
                           modulated data                       6. DCE asserts DCD

                                                                                     7. DTE waits for
                                                                                       arrival of data


                                                                8. DCE sends out
                                                                    demodulated
                                                                   received data
                                                                                      9. DEC receives
                                                                                      demodulated data




                                                ENG3640 Fall 2010                                        40
Procedural Specification
   Over the telephone line the modems will have
    to go through the following phases:
    1.   Phase 1: Establishing the Connection
    2.   Phase 2: Data Transmission
    3.   Phase 3: Disconnection
   The modem will require more signals to
    operate: GND, Tx, Rx, RTS, CTS, DSR, DCD,
    …..    Computer
            (DTE)
                               Modem
                               (DEC)
                                                             Modem
                                                             (DEC)
                                                                                  Computer
                                                                                   (DTE)

                Tx             Tx                                  Tx             Tx
               Rx              Rx                                 Rx              Rx
             RING              RING                             RING              RING
                                              Phone line
             DCD               DCD                              DCD               DCD
              CTS              CTS                               CTS              CTS
              RTS              RTS                               RTS              RTS
              DSR              DSR                               DSR              DSR
              DTR              DTR                               DTR              DTR
             GND               GND                              GND               GND

                                                                                             41
                      Figure 9.3 Asynchronous connection over public phone line
   Sequence of events occur during data transmission over public phone line




                                                            time
                     Local(transmission side)                                     Remote (receiving side)
 Connection
establishment
    phase
     1. DTE asserts DTR

                            2. DCE dials the
                               phone number                        3. DCE detects the ring
                                                                       and asserts RING
                                                                                                   4. DTE asserts DTR
                                                                                                      to accept the call


                                                                   5. DCE sends out a
                                                                   carrier and asserts
                            6. DCE asserts DSR                             DSR
                             and DCD and also
                              sends out a carrier
                                for full duplex
                                   operation
                                                                    7. DCE asserts DCD
                                                                    (full duplex operation)




                                                ENG3640 Fall 2010                                                     42
                Sequence of events occur during data transmission (continued)




                                                          time
                   Local(transmission side)                                    Remote (receiving side)
    Data
transmission
    phase
    1. DTE asserts RTS

                              2. DCE asserts CTS

    3. DTE sends out
        data to DCE
                             4. DCE modulates data
                                 and sends it out                  5. DCE demodulates
                                                                      data and forwards
                                                                       the data to DTE         6. DTE receives
                                                                                                     data
Disconnection
    phase

    1. DTE drops RTS
                              2. DCE drops CTS
                              and drops the carrier
                                                                  3. DCE deasserts
                                                                     DCD & DSR
                                                                                             4. DTE deasserts
                                                                                                   DTR


                                              ENG3640 Fall 2010                                                  43
RS-232 Interface Standard: Summary
   Equipment using                             Many signals are not used =>
    asynchronous serial com.                     serial ports also use a DB-9
    normally use the RS-232                      connector
    interface                                   Common signals:
   The logic levels used for RS-                   Transmit data: TxD or TD
    232 signals are:                                Receive data: RxD or RD
       +12 V for logic 0;                          Request to send: TSR
       -12 V for logic 1                           Clear to send: CTS
   This is to allow signals to be                  Data set ready: DSR
    transmitted over greater                        Signal ground: SG
    distances                                       Data carrier detect: DCD
   This is a bipolar form of NRZ                   Data terminal ready: DTR
    format                                          Ring indicator: RI
   The standard defines 25                     From normal HCMOS and TTL
    different signals                            levels we need to use special
                                                 driver chips for ...

                             ENG3640 Fall 2010                                  44
Null Modem      The EIA standard
                 doesn’t allow for a
                 direct connection
                 between two DTEs
                When two DTEs wish
                 to communicate then
                 we have to use a DTE-
                 DTE null modem cable
                 configuration.
                The Null Modem
                 fools both DTEs into
                 thinking that they are
                 connected to
                 modems.


                                    45
RS422
   To increase the baud rate and maximum distance, the
    balanced differential line protocols were introduced.
   RS422 signal is encoded in a differential signal A-B
    because each signal requires two wires
   RS422 can connect one transmitter to 10 receivers.




                       ENG3640 Fall 2010               46
RS232 vs. RS422




             ENG3640 Fall 2010   47
The Serial Communication Interface
(SCI) in 68HC12
   With additional conversion                Transmitting is a simple
    circuits the SCI can be used               matter of writing bytes to a
    to communicate with remote                 data register SCDR
    devices                                       the SCI handles the
   SCI uses port S pin PS1 as                     framing requirements
    TxD and PS0 as RxD                             (no parity)
   These lines can be enabled                The SCI receiver
    or disabled by one of the SCI              automatically changes each
    control registers (SCCR2)                  framed serial character into a
   When enabled SCI                           byte
    subsystem has control of the              BAUD register is used to
    respective port S lines and                configure the clock
    overrides DDRS settings



                           ENG3640 Fall 2010                              48
SCI Block Diagram




                                Transmit/Receive
                                through S0,S1 or S2, S3

            ENG3640 Fall 2010                      49
Simplified Functional Block Diagram of the SCI

        Consists of:
    1.     A transmit data register (SC0DRL) that acts as a buffer
    2.     A 10 or 11-bit shift register
        When a byte is written to SC0DRL, that byte along with Start bit, Stop bit
         and optionally a Parity bit is transferred to the transmit shift register.




    Transmitter




         Receiver



                                         ENG3640 Fall 2010                            50
 SCI Control and Status Registers




Control




Status




 Data


                ENG3640 Fall 2010   51
         Configuring the SCI

        Several steps have to be taken to configure
         the SCI sub module within the MCU12
    1.    Setup the baud rate
    2.    Setup the operating mode
    3.    Enable the appropriate interrupts
    4.    Transmitting SCI Data
    5.    Receiving SCI Data




                         ENG3640 Fall 2010             52
(1) Baud Rate Generation
       The first step in configuring the SCI is to set the baud rate
       There is a standard set of baud rates for asynchronous
        communication systems, most notably, 2,400, 4,800, 9,600 bps.
       The baud rate is controlled by the bits SBR12-SBR0
       SCI Baud Rate (transmitter) = fP/(16.BR)
         BR is the value stored in SBR12-SBR0
         fP is the frequency of the MCU P-clock
         P-clock is an internal MCU clock that has the same frequency as the E-
          clock FXTAL/2 but is 90 out of phase




                                       SBR12 SBR11SBR10 SBR9 SBR8


                     SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

                                  ENG3640 Fall 2010                            53
       Baud Rate Register Setting
      The table shows the required baud-rate register setting
       for standard baud rates and a Module Clock of 10.2
       MHz.
I.      The baud rate divisor is
        the value written to the
        SBR12-SBR0 bits
II.     The receiver clock
        frequency is the MCLK
        divided by the baud rate
        divisor.
III.    The transmitter clock
        frequency is the receiver
        clock frequency divided
        by 16.


                                ENG3640 Fall 2010            54
    SCI Control Register SC0CR1
        The second step in configuring the SCI is to set up the
         operating mode by loading a value into the first SCI control register,
         SC0CR1.
    1.     LOOPS: Loop mode bit (0=Normal Mode, 1= Loop Mode)
    2.     M: Mode bit (0 = Normal 8-bit mode, 1 = 9-bit mode)
    3.     WAKE: Wake-up Mode (0=Wake up by idle line, 1= WU 9th bit)
    4.     PE: Parity Enable Bit (0= No Parity, 1 = 9th bit used for parity)
    5.     PT: Parity Type (0=Even Parity, 1=Odd Parity)




                        LOOPS                     M      WAKE    PE     PT




                                     ENG3640 Fall 2010                         55
    SCI Status Registers: SC0SR1/SR2
        The progress of the transmitter/transmitter can be determined by
         several flags in SC0SCR1/SC0SCR2 registers
        Transmitter:
    1.     TDRE: Transmit Data Register Empty Flag (Set after the data have been
           transferred to the shift register)
    2.     TC: Transmit Complete Flag (Set when the shift register completes
           shifting out the data)




                      TDRE   TC




                                   ENG3640 Fall 2010                          56
Example
Example 9.4 Write a subroutine to output the character in accumulator A to the SCI0
channel using the polling method.
Solution:
- The subroutine will wait until the bit 7 of SC0SR1 register is set before sending out the
  character in accumulator A.

#include "d:\miniide\hc12.inc"
putc_sc0 brclr     SC0SR1,$80,*          ; wait for TDRE to be set
           staa    SC0DRL                ; output the character
           rts




                                      ENG3640 Fall 2010                                       57
    SCI Status Registers: SC0SR1/SR2
     Receiver:
    1. RDRF: Receive Register Full Flag (Set when a
       character is received and transferred into SC0DRL,
       Data Register)
    2. IDLE: Idle Line Flag (Set when an idle line is detected)

    3. RAF: Receiver Active Flag (Set when a character is
       being received)


                         RDRF IDLE



                                                 RAF



                          ENG3640 Fall 2010                  58
Example
Example 9.5 Write a subroutine to read a character from the SCI channel 0 using the polling
method. The character will be returned in accumulator A.
Solution: Assembly function is as follows:

#include "d:\miniide\hc12.inc"

getc_sc0   brclr    SC0SR1,$20,*      ; wait until RDRF bit is set
           ldaa     SC0DRL            ; read the character
           rts




                                    ENG3640 Fall 2010                                         59
    Error Types
        Several errors may occur during transfer
         using asynchronous serial transmission:
    1.    Framing Error.
    2.    Receiver Overrun Error.
    3.    Noise Error.
    4.    Parity Error.




                           ENG3640 Fall 2010        60
Framing Error Example

                                     A Framing Error
                                      occurs when a
                                      received character is
                                      improperly framed by
                                      start bit or stop bits.
                                       It is detected by the
                                        absence of the stop
                                        bit.
                                     It indicates
                                      synchronization error
                                      and faulty
                                      transmission.



          ENG3640 Fall 2010                               61
Overrun Error


                                   A receiver overrun error
                                    occurs when one or more
                                    characters in the data
                                    stream are lost.
                                   The characters are usually
                                    received but not read from
                                    the buffer (i.e., shifted but
                                    cannot be loaded into the
                                    receive register because it
                                    is already full!!)




            ENG3640 Fall 2010                                 62
Noise Error

                                     The receiver uses a
                                      sampling clock that
                                      has a frequency of
                                      16 times the baud
                                      frequency.
                                     Once the receiver
                                      has established the
                                      bit boundaries, it
                                      samples the bits
                                      during the 8th, 9th,
                                      and 10th cycles of
                                      the sampling clock.
                                     If the samples are
                                      not identical then a
                                      noise error occurred.

              ENG3640 Fall 2010                               63
    SCI Status Registers: SC0SR1/SR2
        Receiver:
    1.     OR: Overrun Flag (Set when a character is shifted into the
           receiver but cannot be transferred because the receive register is
           already full)
    2.     NF: Noise Flag (Set when noise is detected by receiver)
    3.     FE: Framing Error Flag (Set when a zero is detected during the
           Stop bit time.
    4.     PF: Parity Error Flag (Set when the incorrect parity is detected by
           rec.



                                                      OR   NF   FE   PF




                                  ENG3640 Fall 2010                        64
    SCI Control Register SC0CR2

        The third step in configuring the SCI is to enable appropriate interrupts
         by loading a value into the second SCI control register, SC0CR2.

    1.     TIE: Enables TDRE flag (Trans DR Empty) to generate interrupt request.
    2.     TCIE: Enables TC flag (Trans Complete) to generate interrupt request.
    3.     RIE: Enables RDRF flag (Receive DR Full) to generate interrupt request.
    4.     ILIE: Enables IDLE flag (Idle Line ) to generate interrupt request.




                          TIE   TCIE     RIE       ILIE


                                       ENG3640 Fall 2010                       65
    SCI Control Register SC0CR2

        The fourth step in configuring the SCI is to enable the SCI Transmitter
         and Receiver
    1.     TE: Enables the SCI Transmitter and Configures the TXD pin
    2.     RE: Enables the SCI Receiver.




                                                        TE   RE

                                    ENG3640 Fall 2010                         66
SCI Driver Routines
; -----------------------------------------------------------------------------------------------
;         SCI_OPEN  Initializes SCI
;         Normal 8-bit mode, 9600bps, no interrupts
;------------------------------------------------------------------------------------------------
 SCI_OPEN movw #52, SC0BD                         ; 9600bps @ 8MHz Eclk
                  movb #$00, SC0CR1 ; Normal 8-bit mode, no parity
                  movb #$0C, SC0CR2 ; No ints enable transmitter, receiver
                  rts
;-----------------------------------------------------------------------------------------------
;        SCI_READ  Read SCI
;        returns ACCB = char or 0 if no char has been received
;-----------------------------------------------------------------------------------------------
 SCI_READ clrb
                  brclr SC0SR1, RDRF, SCI_READ                             ; get status
                  ldab SC0DRL                                               ; get data
                  rts
;-----------------------------------------------------------------------------------------------
;        SCI_WRITE  Write to SCI
;        Outputs the character passed in ACCB
;-----------------------------------------------------------------------------------------------
 SCI_WRITE brclr SC0SR1,TDRE, SCI_WRITE                                     ; wait for TDRE
                   stab SC0DRL                                                ; send data
                   rts
                                                    ENG3640 Fall 2010                               67
Synchronous Serial I/O Subsystem
   The SPI (Serial Peripheral Interface) consists of a clock
    driven by the Master, MISO (Master In Slave Out), MOSI
    (Master Out Slave In) and Slave Select Pin (SS)




                         ENG3640 Fall 2010                 68
      SPI Configuration
     To configure the SPI, we need to
    1. Set the baud rate

    2. Configure the SPI clock format

    3. Set the data mode

    4. Set the pin direction in the data direction register for
        PORTS.




                                          2010
                             ENG3640 Fall 2009                    69
    Synchronous Serial I/O Subsystem
       The HC12 uses bit 7, 6, 5 and 4 of PORT S for its SPI data lines.
       If a pin of PORT S needs to be set up as output in order to use the
        HC12 SPI, you need to write a 1 to that bit of the DDRS.
         In Master Mode, you need to write a 1 to bit 7, 6, 5.
         In Slave Mode, you need to write a 1 to bit 4 (MISO)
       You should setup DDRS before you set up the SPI Control Registers




                                    ENG3640 Fall 2010                         70
    Synchronous Serial I/O Subsystem
   Each SPI module has an 8-bit shift register connected to the SPI
    data register (SP0DR).
   The synchronization clock is always generated by the master.
   When data is written to the Master SP0DR register, the SPI shifts
    the 8-bits out of the MOSI pin while shifting in 8-bits from the MISO
    pins




                              ENG3640 Fall 2010                         71
Slave Select Line

                                  A Master HC12 can talk with
                                   more than one slave HC12’s
                                  A slave uses its Slave
                                   Select (SS) line to
                                   determine if it is the one the
                                   master is talking with.
                                  There can only be one
                                   master HC12, because the
                                   master HC12 is the device
                                   which generates the serial
                                   clock signal.




           ENG3640 Fall 2010                                 72
        Using SPI With Other Devices
       The HC12 can communicate with many type of devices
        using its SPI
        For example, a Digital-to-Analog Converter.
        The D/A converter has three digital lines connected to the HC12
         (Serial Data, Serial Clock, Chip Select)




                               ENG3640 Fall 2010                       73
        Using SPI With Other Devices
       The HC12 can talk to a Real Time Clock (RTC)
         An RTC keeps track of the time (year, month, day, …)
         An RTC can be programmed to generate an alarm (interrupt) at a
          particular time
       The HC12 initially tells the RTC what the time is
       The RTC keeps track of time from then on.




                                  ENG3640 Fall 2010                        74
Comparison of Sync Serial Comm




                          2010
             ENG3640 Fall 2009   75
Summary
   The main drawbacks of using parallel data transfer:
       Requires many I/O pins
       Many I/O devices do not have high enough data rate to
        justify the use of parallel data transfer
       Cost is high and limited distance
   Serial communications comes in two flavors
       Asynchronous mode (RS-232, EIA-232, RS-442, ….)
       Synchronous mode (requires clock signal)
   The main characteristics of asynchronous serial
    communications (RS-232)
       Data rate is 20Kbps
       Signal can transfer correctly within 15 meters
       Driver max output voltage is -25V and +25V
       A voltage more negative than -3V is interpreted as 1.

                           ENG3640 Fall 2010                    76
ENG3640 Fall 2010   77
(4) Procedural Specification
        E.g. Asynchronous private line modem
1.       When turned on and ready, modem (DCE) asserts
         DCE ready
2.       When DTE ready to send data, it asserts Request to
         Send (RTS)
         Also inhibits receive mode in half duplex
3.       Modem responds when ready by asserting Clear to
         send (CLS)
4.       DTE sends data
5.       When data arrives, local modem asserts Receive
         Line Signal Detector and delivers data
                              ENG3640 Fall 2010         78
Modem Control Signals




            ENG3640 Fall 2010   79
Dial Up Operation (1)
(2) TX                                            (6) DTE B Asserts DTR
                 (1) DTR
                                                                    (5) Alert DTE B
                           (7) DCE B asserts DSR




         (3) DCE A Dials              (4) DCE B detects
                              ENG3640 Fall 2010                                80
Dial Up Operation (2)




               ENG3640 Fall 2010   81
Dial Up Operation (3)




               ENG3640 Fall 2010   82
     SPI Configuration Registers
     The SPI configuration registers include
    1. A Baud-Rate Register

    2. Two Control Registers.




                           ENG3640 Fall 2010    83
        SPI Baud Rate
       The SPI clock frequency and baud rate are controlled by
        SPR2, SPR1, SPR0 bits in SP0BR Register.
       The SPI clock frequency and data rates are
        RSPI = FSCK = (FP)/2 (SPR+1)
       Assume P-clock = 8MHz,
        If SPR2, SPR1, SPR0 are zero then the SPI data rate is 4Mbps.
        If SPR2, SPR1, SPR0 are ones then the SPI data rate is 31.3Kbps




                                                   SPR2 SPR1   SPR0


                               ENG3640 Fall 2010                      84
    SPI Clock Format

   A large number of devices in the market today use
    synchronous serial communications.
   One of the main problems that face engineers is that
    many devices have different timing requirements.
   To make the SPI compatible with as many devices as
    possible, it is designed to be versatile by providing
    programmable clock formats.
   The clock format is controlled by the CPOL and CPHA
    bits in the SP0CR1 register.

                                            CPOL CPHA


                        ENG3640 Fall 2010                   85
SPI Clock Format

                                   CPOL  controls the
                                    clock polarity.
                                   The polarity bit
                                    CPOL, determines
                                    the clock edge used
                                    to sample the data.
                                   CPHA  controls the
                                    clock phase.
                                   The phase bit CPHA
                                    determines whether
                                    the first clock edge or
                                    the second clock
                                    edge qualify the data
                                    to be valid.




            ENG3640 Fall 2010                         86
    Miscellaneous SPI Configurations

   SPIE : SPI Interrupt Enable (if 1, then the SPI interrupt
    occurs when SPIF or MODF flags are set)
   SPE: SPI System Enable (if 1  SPI Enabled)
   MSTR: SPI Master/Slave Mode (if 1  Master Mode)




             SPIE   SPE            MSTR




                           ENG3640 Fall 2010                    87
        Miscellaneous SPI Configurations

       SSOE: Slave Select Output Enable Bit
        0 = /SS pin is used for the MODF function (Mode Fault Flag)
        1 = /SS function is enabled
       LSBF: LSB First Enable Bit (if 1 Data are sent LSB first)




                                                           SSOE LSBF




                                ENG3640 Fall 2010                      88
    SPI Status/Data Register
   To transfer data to or from a slave device, a program
    must make use of the SPI status register, SPOSR, and
    the SPI data register, SP0DR.
   To send data, the program must test the SPI transfer
    complete flag, SPIF, and write the data to the SPI data
    register, SP0DR.

             SPIF




             BIT 7                                 BIT 0

                         ENG3640 Fall 2010                    89

				
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