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					Special applications of VLSI design



                                Summer Semester 2008

                                     Results of Phase 1

                         Eduard Wernergold, Tim Wegner




Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock   Slide 1
    Design and architecture
    Chosen type of filter: Direct form I


x(i)
                z(-1)                    z(-1)                                  z(-1)




           h(0)                      h(1)                                h(8)               h(9)

0
       +                      +                                 +                       +
                                                                                             y(i)




        Institute of Applied Microelectronics and Computer Engineering
        College of Computer Science and Electrical Engineering, University of Rostock               Slide 2
Design and architecture
Chosen adders and multipliers

• adders : Ripple Carry Adder ( easy to design but slow due to serial
  computation)
• multipliers : individual approach for each tap
          • realization of filter coefficients through shifting and adding
           adding with ripple carry adders

          a0      b0                    a1      b1                    a2      b2


c0      full adder          c1         full adder          c2         full adder   c3



             s0                            s1                            s2


     Institute of Applied Microelectronics and Computer Engineering
     College of Computer Science and Electrical Engineering, University of Rostock      Slide 3
      Design and architecture
      Multipliers

      • coefficients 1, 8, -17, -25, 28, 28, -25, -17, 8, 1 symmetric
             only 5 coefficients need to be implemented
             „1“ means shifting the input into a register
             implementation only for 8, -17, -25, 28 + delay for the rest
             advantage: easier design, faster due to smaller number of gates


„8“                       „-17“                                             „-25“                  „28“

<<3           <<1    <<2       <<3      <<5       <<6           <<1        <<2   <<5   <<6   <<2    <<3     <<4


                ripple carry adder                                  ripple carry adder       ripple carry adder


          Institute of Applied Microelectronics and Computer Engineering
          College of Computer Science and Electrical Engineering, University of Rostock                   Slide 4
        Design and architecture
        Multipliers: design overview
x(i)
       R0         R1             R2             R3             R4            R5       R6       R7       R8

                                                                                           R

            „8“          „-17“          „-25“           „28“                      R        R    „8“

                                                                        R         R        R

 RCA        RCA          RCA            RCA            RCA            RCA     RCA      RCA      RCA      RCA


        can be removed                                                                                    y(i)


            Institute of Applied Microelectronics and Computer Engineering
            College of Computer Science and Electrical Engineering, University of Rostock             Slide 5
 Design and architecture
Facts


                        Mandatory values for FPGA
                        Frequency f                        43.397MHz
                        Area Aslices
                                                                676
                        (# of slices)
                        f/Aslices                      0.0641MHz/Slice




        Institute of Applied Microelectronics and Computer Engineering
        College of Computer Science and Electrical Engineering, University of Rostock   Slide 6
Design and architecture
Simulation Results




   Institute of Applied Microelectronics and Computer Engineering
   College of Computer Science and Electrical Engineering, University of Rostock   Slide 7
Further Improvements
• replacement of ripple carry adder
     aspire faster (and smaller) design (e.g. carry-skip, carry-look-ahead)


• using direct form II ( outputs computed faster)

• faster/more efficient approach for multipliers
     maybe without shift registers


• pipelining the registers and logic blocks to reach higher performance




    Institute of Applied Microelectronics and Computer Engineering
    College of Computer Science and Electrical Engineering, University of Rostock   Slide 8

				
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posted:6/14/2011
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