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DPPworkshop_CERN

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					                                             CERN
                                             Electronics Pool
Tools for Discovery




Digital Pulse Processing Workshop
                      June 23rd 2010, CERN
                           Carlo Tintori
                                                                                                                                                             Outline
•   Description of the hardware of the waveform digitizers

•   Use of the digitizers for physics applications

•   Comparison between the traditional analog acquisition chains and the new fully
    digital approach

•   DPP algorithms:
     • Pulse triggering
     • Zero suppression
     • Pulse Height Analysis
     • Charge Integration
     • Time measurement
     • Gamma-Neutron discrimination
     • Multi Channel Scaler

•   Overview on the CAEN Digitizer family

•   Experimental setup description and practical demonstrations


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                                                                                 Digitizers vs Oscilloscopes
• The principle of operation of a waveform digitizer is the same as the
  digital oscilloscope: when the trigger occurs, a certain number of
  samples (acquisition window) is saved into one memory buffer
• However, there are important differences:
    –   no dead-time between triggers (Multi Event Memory)
    –   multi-board synchronization for system scalability
    –   high bandwidth data readout links
                                                                                                                                                     Memory Buffer
                                                                                                                                                       TIME STAMP
    –   on-line data processing (FPGA or DSP)                                                                                                              S[0]
                                                                                                                                                           S[1]
                                                                                                                                                           S[2]
                                                                                                                                                           S[3]
                                                                              ACQUISITION WINDOW

                                                                                                                                                             S[n-1]




                                                                                                                                 Sampling Clock
                                                                                TRIGGER
                                                                                                                                                                          Time
                                                                        PRE                 POST TRIGGER




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                                                                                  Block Diagram
• Mother-daughter board configuration:
•     The mother board defines the form-factor; it contains one FPGA for the readout
      interfaces and the services (power supplies, clocks, I/Os, etc…)
•     The daughter board defines the type of digitizer; it contains the input amplifiers,
      the ADCs, the FPGA for the data processing and the memories
                                     DAUGTHER BOARDS
                                                                MOTHER BOARD
                                                                                                   CLK-OUT

                                                                                                   CLK-IN
                                              SAMPLING CLOCK
                                                                            PLL
                FIXED GAIN
                AMPLIFIER                                                           INT. OSCILL.
ANALOG
 INPUTs
                             +      ADC                        LOCAL BUS                           VME/USB
                                                 FPGA          GLOBAL TRG
                                                                            FPGA
                                                 (AMC)            SYNC      (VME)
                                    DAC                         SELF TRG
                                                                                                   CONET
                                                                                                      TRG-IN
                                                                                                      SYNC-IN
                                 n CHANNELS    SRAM                                                   TRG-OUT
                                              MEMORY                                                  I/Os



                                                                                  DAC                 MONITOR
                                       Opt. Link                                                                                    Board Layout
                          DAC out                                                         TRG in-out                             CLK in-out
   I/Os




                                     PLL                                                                                                                         ADC
                                                                                                                   FPGA


                         Lin. Reg.                                                                                                                             FPGA

                                                          LOCAL BUS
DC-DC
                                 DC-DC



                                                                                                                                                   Memory

                                                                                                                                                VME
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                                                            Multi-board synchronization (I)

• Clock distribution
   • External Clock In/Out (differential LVDS)

   • Clock Distribution:
       • Daisy Chain: Clock-Out to Clock-In chain (the first board can act as a clock master)
       • Fan-Out: one clock source + 1 to N fan-out

   • High performance and low jitter PLL for clock synthesis
       • Frequency multiplication: necessary when the sampling clock frequency is high
       • Jitter cleaning: the PLL can reduce the jitter coming from the external clock source

   • Programmable clock phase adjust to compensate the cable delay




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                                                       Multi-board synchronization (II)

• Trigger and Sync Distribution
   • External Trigger In/Out
   • Trigger Time Stamp synchronous with the ADC sampling clock
   • External Sync input to start-stop the acquisition synchronously and/or to
     keep the time stamp alignment between boards
   • External Trigger and Sync must be synchronous with the sampling clock
   • The trigger re-synchronization causes a jitter of one clock period (trigger
     uncertainty)
   • It is necessary to digitize the trigger signal in the cases where the trigger is
     used as a time reference to be correlated with the channels
   • The trigger latency can be compensated by means of the pre-trigger size
     (memory look back)




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                                                                                            Triggers and acquisition

•   Trigger types:
     • External Trigger (same as the ‘Ext Trigger’ in the scopes)
     • Software Trigger (same as the ‘Auto Trigger’ in the scopes)
     • Self-Trigger (same as the ‘Normal Trigger’ in the scopes)
•   The trigger can be common to all the channels in a board (like in the scopes) or
    individual; in the first case, the self trigger of one channel is propagated to the
    others
•   Self trigger: just a simple threshold or advanced triggers based on digital
    algorithms implemented in the FPGAs (input pulse recognition)
•   Programmable Acquisition Window and Pre/Post Trigger Size
•   Dead-Timeless Multi Event Acquisition (memory paging)
•   Some digitizers have auxiliary digital I/Os or communication busses that allow to
    use external trigger logics (coincidences, multiplicity, etc…)




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                                                          Fundamentals of A/D conversion
•   Analog Bandwidth <= Sampling rate / 2

•   LSB = Dynamic Range / 2Nbit

•   Quantization noise:  = LSB / 12 = ~ 0.3 LSB

•   SNR = 20 log (S/N); THD = 20 log (S/D); SINAD = 20 log (S / (N+D))

•   Effective Number of bits: ENOB = (SINAD – 1.76dB) / 6.02

•   Oversampling: Fovs = 4 Nadd                                        *   Fs  N’bit = Nbit + NAdd
•   Sampling clock jitter: SNRJITTER = -20 log (2 FANALOG TJITTER)

•   Other sources of noise: DNL, INL




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                                                 Digitizers for Physics Applications
• Traditionally, the acquisition chains for radiation detectors are made out
  of mainly analog circuits; the A to D conversion is performed at the very
  end of the chain
• Nowadays, the availability of very fast and high precision flash ADCs
  permits to design acquisition systems in which the A to D conversion
  occurs as close as possible to the detector
• In theory, this is an ideal acquisition system (information lossless)
• The data throughput is extremely high: it is no possible to
  transfer row data to the computers and make the analysis off-
  line!
• On-line digital data processing in needed to extract only the information
  of interest (Zero Suppression & Digital Pulse Processing)




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                                                                 Traditional chain: example 1
                                                                                                charge sensitive preamplifiers




                                     TIME                 Q = ENERGY




             DETECTOR

                                                                                            DECAY TIME
                                  RISE TIME




       PREAMPLIFIER

                                                                             PEAK AMPLITUDE = ENERGY

SHAPING AMPLIFIER


 TIMING AMPLIFIER
                                                    ZERO CROSSING

                        CFD
                                                     This delay doesn’t depend
                                                      on the pulse amplitude
          CFD OUTPUT

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                                                                      Traditional chain: example 1
                                              trans-impedance (current sensitive) preamplifier




                           TIME                     Q = ENERGY




     DETECTOR
                                                                                    •       The QDC is not self-triggering; need a
                                              ZERO CROSSING                                 gate generator
            CFD
                                                                                    •       need delay lines to compensate the
          GATE                                                                              delay of the gate logic
DELAYED SIGNAL
                                                        CHARGE
                                                      INTEGRATION




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                                                       Benefits of the digital approach

• One single board can do the job of several analog modules
• Full information preserved
• Reduction in size, cabling, power consumption and cost per
  channel
• High reliability and reproducibility
• Flexibility (different digital algorithms can be designed and
  loaded at any time into the same hardware)




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                                                                                                             Readout Bandwidth
• Example with Mod720:
   • 1 sample = 12 bit = 1.5 byte
   • 1 channel = 1.5 byte @ 250MHz = 375 MB/s
   • 1 VME board = 8 channels = 3 GB/s !!!

• Continuous acquisition not possible!
• Example2 (triggered acquisition):
   • Record length = 512 samples (~ 2 s) = 768 bytes per channel
   • Trigger Rate = 10 KHz
   • 1 VME board = ~ 61 MB/s

• Readout Bandwidth of CAEN digitizers:
   •   VME with MBLT:                                    60 MB/s
   •   VME with 2eSST:                                   150 MB/s
   •   Optical Link:                                     70 MB/s
   •   USB 2.0:                                          30 MB/s


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                          Digital Pulse detection (self-triggering)

• A good trigger is the basis for both the DPP and the Zero
  Suppression
• The aim of the self-trigger is to identify the good pulses and
  trigger the acquisition on channel by channel basis
• Pulse identification can be difficult because of the noise,
  baseline fluctuation, pile-up, fast repetition, etc…
• Trigger algorithms based on a fixed voltage threshold are
  not suitable for most physics applications
• It is necessary to apply digital filters able to reject the
  noise, cancel the baseline and to do shape and timing
  analysis



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                                                                    DPP algorithms for triggering
• Timing filter RC-(CR)N issues:
   •   High frequency noise rejection (RC filter  mean)
   •   Baseline restoration (CR or CR2 filter  1st or 2nd derivative)
   •   Immune to pile-up and low frequency noise (baseline fluctuation)
   •   Bipolar signal  Zero crossing time-stamp (digital CFD)
• Constraints on the Time Over Threshold and/or zero crossing can
  be added to improve the noise rejection

                                                                        Missed Pulse


                                                         Bad Trigger

                                                                                                                                      Threshold
                 Input Signal

                                   Trigger
                                                                                                                                     Time




                                                                                                                                      Threshold
                   Timing
                    Filter


                                   Trigger
                                                                                                                                     Time


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                                                                       DPP for the Zero Suppression

 • Data reduction algorithms can be developed to reduce the data
   throughput:
    – Full event suppression: one event (acquisition window) is
    discarded if no pulse is detected inside the window
    – Zero Length Encoding: only the parts exceeding the threshold
    (plus a certain number of samples before and after) are saved.



                                         ZLE threshold



suppressed                                     suppressed                                suppressed

Look Back           Region of                Look Ahead
 Window              Interest                  Window




                                                                                                                T          SAMPLES             T     SAMPLES        T   SAMPLES



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                                              DPP for the Pulse Height Analysis
                                                                      (DPP-TF)

• Digital implementation of the shaping amplifier + peak sensing ADC
  (Multi-Channel Analyzer)
• Implemented in the 14 bit, 100MSps digitizers (mod. 724)
• Use of trapezoidal filters to shape the long tail exponential pulses
• Pile-up rejection, Baseline restoration, ballistic deficit correction
• High counting rate, very low dead time
• Energy and timing information can be combined
• Best suited for high resolution spectroscopy (especially Germanium
  detectors)




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                                                                                                 DPP-TF Block Diagram

                                                       a b N                           Thr
                                                                                                                ARMED             CLK             COUNTER                  TIME STAMP
                                                                                                   COMP


                                                      TRG & TIMING
                                                        FILTER                                                                           TRIGGER
                    D                                                                                                  COMP
                                                                                                       ZERO
                                                        RC-(CR)N                          Nsbl
                                                           N = 1,2

INPUT        DECIMATOR
                                                       kmM                                                                                     ftd           Nspk
                                                                                               BASELINE
              D = 1,2,4,8                                                                        MEAN

                                                                                                                                                     PEAK
                                                                                                                                 SUB                                       ENERGY
                                                     TRAPEZOIDAL                                                                                     MEAN
                                                        FILTER
                                                                                     ftd = Flat Top Delay                                Nspk = Peak mean
                                                                                       (ballistic deficit)
            Thr = TRG Threshold                                                                                                                         M = Time Constant
                                                                            K = Shaping Time                                                             (PZ cancellation)
   b = RiseTime

TIMING
                                                                       TRAPEZOID
FILTER
                                         zero crossing
                                                                                              Nsbl = Baseline Mean                             m = Flat Top
                a = Low Pass mean



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                                                           DPP-TF / Analog Chain set-ups




                   N1470
                    High
                   Voltage
                                                                                    N968                                  N957
                                                                                  Shaping                              Peak                                         Energy
                                                                                  Amplifier                         Sensing ADC
60Co
                                              C.S.
137Cs                Ge / Si
                                              PRE




                                                                                                  DT5724                                            Energy
                                                                                           14bit @ 100MSps
                                                                                           Digitizer + DPP-TF                                       Time

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                                                                                       DPP-TF vs Analog Chain
• PROs
  –   All in one board
  –   Stability and reproducibility
  –   Counting rate (lower dead-time)
  –   Source Activity measurement (count all pulses)
  –   Ballistic deficit correction
  –   Timing information
  –   Dynamic Range
  –   Channel density
  –   Synchronization and coincidences in multiple channel systems
  –   Total Cost per Channel
  –   Better Energy Resolution (?)

• CONs
  – Parameters set-up (need good software interface)
  – Getting started more difficult
  – Lower Energy Resolution (?)

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                                                                                               DPP-TF: Test Results
• Tested with Germanium Detectors at LNL (Legnaro - Italy) in Nov-08
  and Feb-09, at GSI (Germany) on May-09, at INFN-MI on Jan-10, in
  Japan on Feb-10: resolution = 2.2 KeV @ 1.33 MeV (60Co)
• Tested with Silicon Strip (SSSSD and DSSSD) and CsI detectors in
  Sweden at Lund and Uppsala (ion beam test)
• Tested with NaI detectors in CAEN (see demo)
• Tested with PET in U.S.A.
• Tested for a homeland security application using CsI



                                                                                               60Co with

                                   228Th with                                                         Ge
                                      DSSSD                                                 FWHM @ 1.33 MeV:
                                                                                                2.2 KeV



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                                                         DPP for the Charge Integration
                                                                              (DPP_CI)

• Digital implementation of the QDC + discriminator and gate generator
• Implemented in the 12 bit, high speed digitizers ( Mod. 720(*) )
• Self-gating integration; no delay line to fit the pulse within the gate
• Automatic pedestal subtraction
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Energy and timing information can be combined
• Typically used for PMT or SiPM/MPPC readout and for gamma-neutron
  discrimination in scintillating detectors


(*) Implementation in the Mod751 is being studied

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                                                                                                       DPP-CI Block Diagram
      INPUT

     b = RiseTime
                             Thr = TRG Threshold

     TIMING                                                                                                                          QLSB = TS * VLSB / 50
     FILTER
                                                                                                                                          = 40 fC (Mod 720)
  a = Low Pass mean
                                    W = Gate width



      GATE

Nsbl = Baseline mean                                                                                                  CLK              COUNTER                   TIME STAMP

    DELAYED                                                     a b
     INPUT
                                                                                              Thr
                                                                                                                           TRIGGER
 D = Delay (Pre-Gate)                                                                                    COMP
                                                           TRG & TIMING                                                                           W
                                                             FILTER



                                                                                                                                                          GATE
                                                                                                                                    MONOSTABLE
                       INPUT
                                                                 D                      Nsbl


                                                                                                                                                    ACCUMULATOR
                                                                                               BASELINE                           SUB                                           CHARGE
                                                              DELAY                                                                                 (INTEGRATOR)
                                                                                                 MEAN




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                                                              DPP-CI / Analog Chain set-ups



            N1470
                                                                                      Delay                                           QDC
             High                                                                                                                                                        Charge
                                                                                      N108A                                          V792N
            Voltage                                 Splitter
                                                     A315
                                                                          CFD                         Dual Timer
                                                                          N842                          N93B
                                PMT
           NaI(Tl)

60Co
137Cs
                                                                                                                                       TDC
                                                                                                                                                                         Time
                                                                                                                                      V1190



                                                                                                                DT5720                                            Charge
                                                                                                         12bit @ 250MSps
                                                                                                         Digitizer + DPP-CI                                       Time

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                                                                                        DPP-CI vs Analog Chain
• PROs
  –   All in one board
  –   Stability and reproducibility
  –   Self-Independent-Retroactive-Adaptive Gate
  –   No conversion time (dead-timeless acquisition)
  –   Baseline restoration
  –   Accept positive, negative and bipolar signals
  –   Extremely wide Dynamic Range
  –   Coincidences between couples of channels
  –   Total Cost per Channel
  –   Better Energy/Timing Resolution (?)

• CONs
  –   Parameters set-up (need good software interface)
  –   Getting started more difficult
  –   Channel density
  –   Lower Energy/Timing Resolution (?)
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                                                                                                  DPP-CI: Test Results




                                                                                                                           DPP-CI                          Analog QDC
                                                                              Energy (MeV)                                 Res (%)                             Res (%)

                                                                   0.481 (137Cs Compton edge)                           9.41  1.18                        12.80  0.70
                                                                      0.662 (137Cs Photopeak)                           7.01  0.04                         8.17  0.04
                                                                        1.33 (60Co Photopeak)                           5.67  0.03                         6.66  0.18
                                                                        1.17 (60Co Photopeak)                           5.46  0.02                         5.89 0.13
Resolution = FWHM * 100 / Mean                                          2.51 (60Co Sum peak)                            3.82  0.11                         4.10  0.24

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                                                                                                  DPP-CI: Other Tests
• Tested with SiPM/MPPC detectors at Univerità dell’Insubria (Como –
  Italy) and in CAEN (2009/2010):
   –   Dark Counting Rate
   –   LED pulser




                                                                                                                                     •Threshold scan
                                                                                                                                                                        •0.5 ph

   –   Readout of a 3x3mm Lyso Crystal + Gamma source                                                                                                                   •1.5 ph

   –   Readout of a scintillator tile for beta particles                                                                                                                •2.5 ph




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                                                                        DPP for Time Measurements
• Digital implementation of the TDC + CFD
• Actually implemented in both DPP-TF and DPP-CI (without interpolation)
• Digital algorithms to implement Constant Fraction Discriminators or
  Timing Filters (RC-CRN)
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Interpolation between a set of samples can increase the resolution well
  beyond the sampling period (up to picoseconds)
• Resolution strongly dependent on pulse signal rise-time and
  amplitude (V/ T)




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                                  Digital algorithms for Timing Analysis
• Positive/negative pulses digitally transformed into bipolar pulses
• The Zero Crossing doesn’t depend on the pulse amplitude
• Timing filters: RCN or Digital CFD
• Optional RC filter (mean filter) to reduce the HF noise
• ZC interpolations:
    • Linear (2 points)
    • Cubic (4 points)
    • Best fit line or curve (4 or more points)
                                                                                                                                             High Resolution ZC after
                                                                                                                                   S1        math. Interpolation

                                                                                                                                        S2

  INPUT                                                                                                                                                                 Time
                                                                                                                                        S3

                                                                                                   S4 = ZC time stamp
                                                                                                                                             S4
                                                                                                   Resolution = Ts / 12
 Timing
  Filter
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                                                              Digital CFD and Timing Filters
                                                                                   e-t/T


      INPUT


                                                                     -(1/T)     e-t/T
  CR Filter:
 st
1 derivative


                                                                  (1/T2)     e-t/T
   CR2 Filter:
2nd derivative



                                                                                                                 D = CFD delay
                                                                       K   e-t/T        K = f(D, F)              F = CFD Fraction

      Digital
       CFD



  NOTE: the higher ZC slope and the lower tail, the better filter

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                                                                                                                        ZC timing errors
                                                               •         The timing resolution is affected by three main
               TSAMPL                                                    sources of noise:
                                                                          –         Electronic noise in the analog signal (not
                                                                                    considered here)
                ANALOG
                SIGNAL
                                                                          –         Quantization error Eq
                                             SN+1
                                                                          –         Interpolation error Ei
     Ei                                                        •         Both simulations and experimental test
                                                                         demonstrate that there are two different regions:
                                                               •         When Rise Time > 5*Ts the pulse edge can be
                                                                         well approximated to a straight line, hence Ei is
                                               zero                      negligible. The resolution is proportional to the
                                                                         rise time and to the number of bits of the ADC.
                                                               •         When Rise Time < 5*Ts the approximation to a
                                                                         straight line is too rough and Ei is the dominant
                             Eq                                          source of error. The resolution is still proportional
                                                                         to the number of bit but becomes inversely
                   LINEAR
               INTERPOLATION
                                                                         proportional to the rise time. Resolution
                                                                         improvement expected for cubic interpolation.
                                                 LSBADC        •         The best resolution is for Rise Time = 5*Ts,
                                                                         regardless the type of digitizer
SN
                                                               •         The resolution is always proportional to the pulse
                                                                         amplitude (more precisely to the slope V/T)
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                         Sampling Clock phase effect (RT<5Ts)                                                                                                                (I)
DELAYA-B = N*TS                     CHA                CHB


                                                                                                     DELAYAB = N * Ts:
                          ERRA              ERRB
                                                                                                     same clock phase for A and B 
                                                                                                     same interpolation error 
                                                                                                     ERRA  ERRB 
                                                                                                     Error cancellation in calculating TIMEAB



TIMEAB      = (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA - ERRB )


DELAYA-B = (N+0.5)*TS             CHA                           CHB


                                                                                                     DELAYAB = (N+0.5) * Ts:
                                                                                                     rotated clock phase for A and B 
                        ERRA                           ERRB


                                                                                                     same interpolation error 
                                                                                                     ERRA  ERRB 
                                                                                                     No error cancellation. ERRA and ERRB
                                                                                                     are symmetric: twin peak distribution



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                        Sampling Clock phase effect (RT<5Ts)                                                                                                                                                                                                                (II)

9   0   0




                                                                                                                            '   h   i   s   t   o   _   M           o       d       7   2   4   _   d   t   1       0       n       .       t   x   t   '




                                                                                                                            '   h   i   s   t   o   _   M           o       d       7   2   4   _   d   t   1       5       n       .       t   x   t   '




8   0   0




7   0   0




                         DELAY = N * Ts
6   0   0




5   0   0




4   0   0




                                                                                                                    DELAY = (N + 0.5) * Ts
3   0   0




2   0   0




1   0   0




        0




                    0               2   0   0         4   0   0         6   0   0         8   0   0         1   0   0   0                                   1   2       0       0                               1       4       0       0                   1   6   0   0




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                     Sampling Clock phase effect (RT<5Ts)                                                                                                                      (III)
                     10

                                 Vpp = 100mV                                                                                     Mod1751: 10bit 1GSps

                                                                                                                               Mod1720: 12bit 250MSps
                                 Rise Time = Ts                                   14bit – 100MSps                              Mod1724: 14bit 100MSps

                                 Emulation

                                                                                12bit – 250MSps
                       1




                                                                                     10bit – 1GSps
Std_Dev[ns]




                     0.1




                   0.01

                           0.5                                1                                  1.5                                  2                                  2.5


                                                                                             Delay in Ts

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                            Sampling Clock phase effect (RT<5Ts)                                                                                                                   (IV)
                   10

                            Vpp = 100mV                                                                                               5 ns  RiseTime 5ns

                                                                                                                                    10 10ns
                                                                                                                                RiseTime ns
                            Mod720: 12bit 250MSps
                                                                                                                                    15 15ns
                                                                                                                       Rise TimeRiseTime ns
                            Emulation                                                                                               20 20ns
                                                                                                                                RiseTime ns

                                                                                                                                    30 30ns
                                                                                                                                RiseTime ns




                    1
Std_Dev[ns]




                  0.1




                 0.01

                        3                       4                        5                        6                        7                        8                          9


                                                                                              Delay[ns]
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                                                                                 Preliminary results: Mod724
                                                                                                                                          (14 bit, 100 MS/s)
              DELAYAB = (N+0.5) * Ts (worst case)
StdDev (ns)




                                                                                     RiseTime (ns)

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                                                                                 Preliminary results: Mod720
                                                                                                                                          (12 bit, 250 MS/s)
              DELAYAB = (N+0.5) * Ts (worst case)
StdDev (ns)




                                                                                     RiseTime (ns)

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                                                                                 Preliminary results: Mod751
                                                                                                                                          (10 bit, 1 GS/s)
              DELAYAB = (N+0.5) * Ts (worst case)
StdDev (ns)




                                        NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot



                                                                                     RiseTime (ns)

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                                                                     Mod724 vs Mod720 vs Mod751

              Amplitude = 100 mV
StdDev (ns)




                                                                                     RiseTime (ns)

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                                                                                                                    Mod751 @ 2 GS/s




                                          The cubic interpolation can reduce the gap between best and
                                          worst case as well as increase the resolution for small signals!
StdDev (ns)




                                                                                                                                                               2 ps !




                                                                                 Amplitude (mV)
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                                                                              DPP for -n Discrimination


• Digital implementation of the double gate QDC or rise time discriminator
• Different digital algorithms
    – rise-time/energy correlation (charge sensitive preamplifiers)
    – double gate charge integration (PMTs or current sensitive preamplifiers)
    – zero crossing

• It’s a combination of the previous energy and timing DPP algorithms
• Dead-timeless acquisition (no conversion time)
• Algorithms being tested (collaboration with Duke University)




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                                                           -n Discrimination Block Diagram


                                                                                                                                                         Threshold




SHORT GATE
                                                                                                                                      T1

                                                                                                                                       T2
LONG GATE


                                                                                                   START
                                                                                                   STOP               COUNTER               ZC TIMING


                                                 Thr
                                                                        ARMED                           CLK           COUNTER               TIME STAMP
                                                             COMP
                                   a b

                                                                                                  TRIGGER (ZC)
                                                                              COMP
                                   TIMING
                                   FILTER
                                                                 ZERO                                            W1                           W2


                                                                                                      MONOSTABLE                   MONOSTABLE
     INPUT
                                    D                           Nsbl
                                                                                                              GATE1                   GATE2


                                                                                                                                                 CHARGE (Fast Comp)
                                                                                                                    ACCUMULATOR
                                                                      BASELINE                      SUB
                                  DELAY                                                                             (INTEGRATOR)                 CHARGE (Slow Comp)
                                                                        MEAN


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                                                                     DPP for Pulse Counting (SCA)


• Digital implementation of the discriminator + scaler (Single-Channel
  Analyzer)
• Can be implemented in the high density digitizers (mod. 740)
• Pulse Triggering: baseline restoration, noise rejection, etc…
• Single or Multi-Channel Energy Windowing
                                                                                                                                            ThrH

                                                                                                                                             ThrL
                                            ThrH
                                                            COMP
INPUT            CR-RC
                                                                                                               COUNTER                     ACTIVITY
                                            ThrL
                                                            COMP



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                                                                                                           DPP readout modes
Waveform mode
•   same operating mode of the standard firmware (except for the individual pulse
    triggering)
•   The memory buffer contains one acquisition window (1 trigger  1 buffer)
•   Very useful during the parameters setting and debug
•   High data throughput  low counting rate (typ. < 1KHz)
•   The waveform mode allows the users to develop and test new DPP algorithms
    (off-line analysis)
List mode
•   Readout of lists of events
•   1 event = Energy (Charge/Height), Time Stamp, samples for ZC interpolation
•   The memory buffer contains many events (N triggers  1 buffer)
•   Small data size  high counting rate (1 MHz or more)
•   Histograms, coincidences, etc… easily implemented off line
Mixed Mode
•   Energy and/or Time stamps saved within the waveform samples
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                                                                                          Building DPP algorithms

• The digitizer is a general purpose acquisition module; in most cases it
  requires a dedicated firmware or software to implement a specific
  application
• The first algorithm validation can be done using software signal
  emulators (mathlab, LabView, C/C++, etc…). Everything happens
  inside the computer
• Then it is then possible to verify the algorithm applying them to real
  data read from the digitizer in oscilloscope mode (off-line)
• Once validated, the algorithm must be implemented in the FPGA
  (VHDL or Verilog) or DSP (C/C++) of the digitizer
• Finally, the algorithm can be tested on-line




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                                                                             CAEN Waveform Digitizers

                                                                                        •       VME, NIM, PCI Express and Desktop
                                                                                        •       VME64X, Optical Link (CONET), USB 2.0, PCI
                                                                                                Express Interfaces available
                                                                                        •       Memory buffer: up to 10MB/ch (max. 1024 events)
                                                                                        •       Multi-board synchronization and trigger
                                                                                                distribution
                                                                                        •       Programmable PLL for clock synthesis
                                                                                        •       Programmable digital I/Os
                                                                                        •       Analog output with majority or linear sum
                                                                                        •       FPGA firmware for Digital Pulse Processing
                                                                                                  –      Zero Suppression
                                                                                                  –      Pulse Triggering
                                                                                                  –      Trapezoidal Filters for energy calculation
                                                                                                  –      Digital CFD for timing information
                                                                                                  –      Digital Charge Integration
                                                                                                  –      Pulse Shape Analysis
                                                                                                  –      Coincidence
                                                                                                  –      Possibility of customization
• From 2 to 64 channels
                                                                                        •       Software Tools for Windows and Linux
• Up to 5 GS/s sampling rate - Up to 14 bit
• FPGA firmware for Digital Pulse Processing

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                                                                                                                 Digitizers Table




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                                                                              Mod724: 14 bit, 100 MS/s
•   Very high resolution and low noise digitizer
•   DPP-TF for Pulse Height Analysis (Trapezoidal Filters)
•   Replacement of the shaping amplifier + peak sensing ADC
•   Three dynamic range options (500mVpp, 2.25Vpp and 10Vpp)
•   Best suited for very accurate energy measurements
•   Good timing resolution with slow signals (rise time >= 50 ns)
•   Mid-Low speed signals (Typ: output of charge sensitive preamplifiers)
•   Applications:
     • Spectroscopy (MCA) with Ge, Si and other detectors
     • Any application using charge sensitive pre-amplifiers
     • Low noise applications
     • Neutrino and dark matter physics




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                                                                              Mod720: 12 bit, 250 MS/s
•   Best compromise between resolution and speed
•   DPP-CI for Charge Integration
•   Best suited for PMT and SiPM/MPPC readout
•   Mid-High speed signals (Typ: output of PMT/SiPM)
•   Good timing resolution with fast signals (rise time < 100 ns)
•   Applications:
     • Spectroscopy with NaI, CsI and other detectors (fast pre-ampli)
     • Gamma Neutron discrimination
     • Single Photon Counting
     • PET
     • Homeland Security




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                                                                                 Mod740: 12 bit, 65 MS/s
•   High channel density
•   No DPP available (few FPGA resources)
•   Best suited for high density systems
•   Low speed signals (Typ: output of sensors, CCDs or shaping amplifiers)
•   Applications:
     • Sensors readout (temperature, pressure, CCD, etc…)
     • Coincidence Matrix
     • Imaging
     • Single channel analyser
     • Readout of Shaping Amplifiers
     • TPC readout systems
     • Any application with many channels




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                                                Mod751/761: 10 bit, 1-2-4 GS/s
•   Very high sampling rate
•   2 GS/s: half channels; 4GS/s: one fourth channels
•   No DPP available (DPP-CI perhaps available in the future)
•   Best suited for very high speed detectors (diamond? LaBr? …)
•   High speed signals (Typ: output of wideband amplifiers)
•   Applications:
     • Diamond detectors
     • RPC readout systems
     • Time of flight
     • Fast PMT readout




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                                                          Mod721/731: 8bit, 0.5-1 GS/s
•   Precursor of the od751; today its low cost version
•   No DPP available




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                                                                                           Mod742: 12bit, 5 GS/s
•   Excellent combination of very high sampling rate, resolution and high density
•   Based on the DRS chip (developed by S. Ritt at PSI)
•   No DPP available (at least for the moment)
•   Best suited for very high energy and timing resolution applications
•   Very high speed / high dynamics signals
•   Mixed fast and slow acquisition mode
•   50-100us Dead Time: not suitable for high counting rate
•   Max. 1024 points: not suitable for long pulses
•   Applications:
     • Fast detector test benches
     • Cherenkov Telescopes
     • Ultra precise Pulse Shape discrimination
     • Very high resolution TDC (5-10 ps)?



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                                                                                                      Experimental Demo 1
                                                                                                V1718
                                                                                               VME-USB
                                                                                                Bridge

                                                                                                                            USB
                                                      VME

       V6534                                                                                                                               USB
        High
       Voltage

60Co                       850V

                                                                                                                 DT5724                         Energy
       NaI(Tl)                            Charge Sensitive
                                                                                                          14bit @ 100MS/s
                                         Preamplifier for PMT                                             Digitizer + DPP-TF
                      PMT




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                                                                                                     Experimental Demo 2
                                                                                                                                    V1718
                                                                                                                                   VME-USB
                                                                                                                                    Bridge

                                                                                                                                              USB
                                                                                         VME

       V6534
        High
       Voltage

60Co                     -650V

                                                                        V1720                                      Charge
       LaBr3                                                   12bit @ 250MS/s
                     PMT                                       Digitizer + DPP-CI




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                                                                                                   Experimental Demo 3
                                                                                                                                                     V1718
                                                                                                                                                    VME-USB
                                                                                                                                                     Bridge

                               Trigger                                                                                                             USB
                                                                                                           VME




                                                    2 GHz, 0-50dB
                      HIGH VOLTAGE
                                                   VARIABLE GAIN
                     BIAS GENERATOR
                                                 WIDEBAND AMPLIFER
                                                                                                      V1720                           Charge
 LED                                                                                         12bit @ 250MS/s
PULSER                                                                                       Digitizer + DPP-CI
                                       SiPM


                                                SP5600
                                                                                                                                             USB



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                                                                                              Experimental Demo 4



                                                                                                                    USB
                                                      VME
        V6534
         High                                                                                                                      USB
        Voltage


               450V

                                          A1422                                                                                         Energy
                                                                                                         DT5724
                                      Charge Sensitive                                            14bit @ 100MS/s
                                        Preamplifier                                              Digitizer + DPP-TF




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