Amazon-se by keralaguest


   General use for Amazon-SE:
   The Amazon-SE offers cost-effective ADSL2/2+ Modem/Router solutions. Amazon-SE (PSB
   50601) comes with a variety of hardware interfaces and it is assembled in a LQFP package
   which enables a system board to be built on a 2-layer only PCB. Together with complete
   software packages, the Amazon-SE system solution supports data, voice and video
   equipment to access the internet at greatest speed and convenience. Focused on cost
   sensitive market segment, Amazon-SE is an ideal choice for broadband users from residential
   to SOHO (Small Office/Home Office) environments.

ADSL2+ System Solutions Software Features:
The Amazon-SE software has two different packages:
   • Linux based bridge/router version
   • Simple bridge version, based on eCos platform

   Linux Software Package Features
   • Networking
   – 802.1d transparent bridging
   – Learning Bridge
   – Static Routing
– PPPoE (RFC 2516)
– PPP (RFC 1661)
– PPPoA (RFC 2364)
– Multi-protocol Encapsulation over AAL5 (RFC 2684)
• IP Protocols
– IP v4, future upgrades to IP v6
• User Authentication
– PAP/CHAP with PPP (RFC 1345 and RFC 1994)
• ATM Support (Configuration for hardware processing on ATM QoS)
–   Traffic classes: UBR, CBR and VBR-rt, VBR-nrt
Traffic Shaping according to ATMF Traffic Management 4.1
– ILMI (ATM Forum Integrated Local Management Interface Specification 4.0) Auto
– ITU-T I.610 OAM F4/F5
• Applications
– DHCP Server (RFC 2131, 2132)
– DHCP client (RFC 2132)
– DNS proxy
– Dynamic DNS
– Telnet server
– TFTP server
– HTTP server
– SNMP v1/2/3
• Address Translation
– NAT with various ALG support
• Firewall
– Stateful Packet Inspection and Filtering
– Intrusion Detection and protection
• Management
– TR-069 WAN side CPE Management
• Security
– IPSec, PPTP, L2TP pass through
–   Real time, easy of use ADSL loop and system diagnostic tools

eCoS Bridge Software Package Features
• Networking
– 802.1d Transparent Bridging
– 802.1q header insertion towards WAN and removal towards LAN over RFC2684 bridge
   mode over AAL5
   – Supports multiple VLANs on multiple PVCs and mapping VLANs, PVCs and physical LAN
   ports to multiple bridges
   – Static Routing
   • IP Protocols
   – IPv4
   – TCP
   – UDP
   – ARP
   – ICMP
   • ATM
   – Traffic shaping
   – UBR, CBR, UBR+, VBR-nrt and VBR-rt ATM QoS.
   – I.610 OAM F5 loop back
   – ATM PVC auto-searching
   – Multi protocol Encapsulation over ATM Adaptation Layer-5 (RFC 1483/2684), LLC SNAP or
   VC Mux
   • Applications
   – DHCP Client (RFC 2132)
   – Telnet Server, FTP Client, TFTP Client, HTTP Server
   – SNMP V1/V2c
   • Management
   – Web-based (HTTP) GUI
   – System Logging of ADSL UP/Down events, system UP time
ADSL2+ System Solutions Hardware Features:
The architecture overview which includes the functional block diagram is shown below:
The CPU MIPS4KcC processors features are:
   • 32-bit Address paths
   • 32-bit Data paths
   • MIPS32™ Compatible Instruction Set
   – All MIPS II™ Instructions
   – Multiply-Add and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU)
   – Targeted Multiply Instruction (MUL)
   – Zero and One Detect Instructions (CLZ, CLO)
   – Wait Instruction (WAIT)
   – Conditional Move Instructions (MOVZ, MOVN)
   – Prefetch Instructions (PREF)
   • MIPS32 Enhanced Architecture (Release 2) Features
   – Vector interrupts and support for external interrupt controller
   – Programmable exception vector base
   – Atomic interrupt enable/disable
   – GPR shadow registers
   – Bit field manipulation instructions
   • MIPS16e Application Specific Extension
   – 16-bit encoding of 32-bit instructions to improve code density
   – Special PC-relative instructions for efficient loading of addresses and constants
– Data type conversion instructions (ZEB, SEB, ZEH, SEH)
– Compact Jumps (JRC, JALRC)
– Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE)
• Instruction and Data Cache
– 8 K Byte Instruction Cache Size in a 4-Way set associative organization
– 8 K Byte Data Cache Size in a 2-Way set associative organization
– Loads blocks only until critical word is available
– Supports Write-back with write-allocation and Write-through with or without write- allocation
– 16-byte cache line size, word sectored
– Virtually indexed, physically tagged
– Support for cache line locking
– Non-blocking prefetches
• MIPS32™ privileged resource architecture
– Count/Compare registers for real-time timer interrupts
– Instruction and Data watch registers for software breakpoints
– Separate interrupt exception vector
• Memory Management Unit
– 16 dual entry JTLB with variable page size
– 4-entry instruction micro TLB
– 4-entry data micro TLB
• Core Bus Interface Unit (Core BIU)
– All I/Os fully registered
– Two 16 Bytes collapsing write buffers
• Multiply Divide Unit
– Maximum issue rate of one 32 X 16 multiply per clock
– Maximum issue rate of one 32 X 32 multiply every other clock
– Early-in divide control. Minimum 11, maximum 34 clock cycles
• Big and Little Endian Support
• Performance Monitoring Interface for System to implement performance counters
• Power Control
– Power Down mode (triggered by WAIT instruction)
– Support for software controlled clock divider
• EJTAG Debug Support
– CPU control with start, stop and single-step feature
– Software Breakpoints via SDBBP instruction
– Hardware Breakpoints on virtual addresses
– Test Access Port (TAP) facilitates high speed download of application

To top