Computer Organization

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					Computer Organization

 Topics covered:
 68000 Instruction Set Architecture
    68000 Instruction Set Architecture

   Registers and addressing
   Addressing modes
   Instructions
   Assembly language
   Branch instructions
   Stacks and subroutines
   Simple programs in 68000 assembly language

   Registers and addressing

 External word length:
    Word length used to transfer data between the processor and
    16 bits.
 Internal word length:
    Refers to the size of the processor registers
    32 bits.

   Register structure

 8 data registers (D0-D7) and 8 address registers (A0-A7):
      Each is 32 bits long.
 Instructions use operands of three different lengths:
    Long word – 32 bits
    Word – 16 bits
    Byte – 8 bits
 A byte or a word operand stored in a data register is in the
  low order bit positions of a register:
    Most instructions operating on byte or word operands do not
     affect the higher order bit positions.
    Some instructions extend the sign of a shorter operand into
     the high-order bits.

   Register structure (contd..)

 Address registers hold information used in determining the
  addresses of memory operands:
    Address and data registers can also be used as index registers.
    Address register A7 has a special function of serving as the
     processor stack pointer.
 Address registers and calculations involve 32 bits:
      Only the least 24 significant bits of an address are used
       externally to access the memory.
 Processor Status Register (SR):
      Five condition code bits.
      Three interrupt bits (function will be clear when we discuss
      Two mode-select bits.

      Register structure (contd..)
          Long word
     31    16 15      8 7           0


                                                                                          User stack pointer                    Stack
D3                                                                                      Supervisor stack pointer               pointers
                                                                                      15 13 10 8   4     0
                                                                                 SR                          Status register
D7                                                      T - Trace mode select                                       C-   Carry
                                                    S - Supervisor mode select                                      V-   Overflow
                                                           I - Interrupt mask                                       Z-   Zero
A0                                                                                                                  N-   Negative



A3                                      Address




addresses                Contents

   0           byte 0                byte 1                  •Byte addressable memory
                                               Long word 0
                                                             •Memory is organized in 16-bit words.
   2           byte 2                byte 3
                                                             •Two consecutive 16-bit words constitute
                                                             one 32-bit long word.
                                                             •Word address must be an even number,
                                                             that is, words must be aligned on an
   i           byte i               byte i+1                 even boundary.
                                               Long word i
                                                             •Byte in the high-order position has the
  i+2         byte i+2              byte i+3
                                                             same address as the word, the byte in
                                                             the low-order position has the next
                                                             higher address. This is the big endian
                                                             address assignment.
224 - 2     byte 224 - 2       byte 224 - 1

   Addressing (contd..)

 68000 generates 24-bit memory addresses.
 Addressable space is 224 (16,777,216 or 16M) bytes.
 Addressable space may be thought of as consisting of:
    512 (29) pages of 32K (215) bytes each.
    Page 0 is hexadecimal addresses 0 to 7FFF.
    Page 1 is hexadecimal addresses 8000 to FFFF.
    Last page is hexadecimal addresses FF8000 to FFFFF.

   Addressing modes

 Instruction size:
    Many instructions are one word (16-bit long), some require
     additional 16-bit words for extra addressing information.
    First word of an instruction is the OP-code word.
    Subsequent words (if any) are called extension words.
    Note that the 68000 does not place a one word limit on the
     instruction size, it is a CISC architecture.
 Immediate mode
    Operand is included in the instruction.
    Byte, word, long-word operands are specified in the extension
    Some very small operands are included in the OP-code word.

   Addressing modes (contd..)

 Absolute mode:
    Absolute address of an operand is given in the extension word.
    Long mode: 24-bit address is specified.
    Short mode: 16-bit value is specified, which serves as the low-
     order 16 bits of an address.
      • Sign bit of the 16-bit value is extended to provide the high-
        order 8 bits.
      • Sign-bit is 0 or 1, so two pages can be addressed: 0, and
 Register mode:
      Operand is in a processor register specified in the instruction.
 Register indirect mode:
      Effective address (EA) of an operand is in a processor register
       which is specified in an instruction.

   Addressing modes (contd..)

 Autoincrement mode:
    EA is in one of the address registers which is specified in the
    After the operand is addressed, the contents of the address
     register are incremented by 1 (byte), 2 (word), 4 (long-word).
 Autodecrement mode:
      Same as above, except the contents are decremented before
       the operand is accessed.
 Basic index mode:
      16-bit signed offset and an address register are specified.
 Full index mode:
      8-bit signed offset, an address register and an index register
       (either a data or address register) are specified.
 Basic relative and Full relative modes:
      Same as Basic index and Full index modes respectively, except
       PC is used instead of address register.

       Addressing modes (contd..)

1000      OP-code word                        •Consider the instruction:
1002      Extension word                             ADD 100(PC,A1), D0
                                              •Full relative mode for the source operand.
                           100 = offset       •Register mode for the destination operand.
                                              •Compute the EA of the source operand:
                                                - Suppose A1 holds the value 6.
                            6 = index            - Suppose the OP-code word is at 1000.
1106                                      Array
                                                 - After the OP-code word is fetched, PC
1108         Operand
                                                   points to the extension word, i.e. 1002.
                                                   EA = [PC] + [A1] + 100
                                                   Thus, EA is 1108.
                                              •This could be used to address the data in an
                                              array form.
                6          A1                 •In relative modes, PC need not be specified
                                              explicitly in the instruction.


 Extensive set of instructions.
 Both two-operand and one-operand instructions.
 Two-operand instructions:
      Format: OP src, dst.
      Assembly language notation, the actual encoding may not be in
       the same order.
      OP specifies the operation performed.
      Result is placed in the destination location.
      For most two operand instructions, either src, or dst operand
       must be in a data register. Other operand may be specified
       using any one of the addressing modes.
      The only two operand instruction where any addressing mode
       may be used to specify both the operands is the MOVE

   Instructions (contd..)

                               Consider the instruction: ADD #9, D3
                            Add 9 to contents of D3 and store result in D3.

  15 12 11 9 8 7 6 5               0
                                           •Bits 15-12 and 8 specify the operation.
   1 1 01 dst 0             src
                                           •Bits 9-11 specify the destination register D3.
                                           •Bits 7-5 specify the size of the operands, default is
                     size                  word, with a bit pattern 01.
         operation                         •Bits 5-0 identifies that the source operand is immediate
                                           with the pattern 111100.
                                           •The actual value of the source operand is in the extension
Binary      1 1 0 10 1 1 00 1 1 11 1 0 0   word.
Hex           D       6     7      C
                                           •Binary and hex encoding of the OP-code word are

     Instructions (contd..)

                             Consider the instruction: ADD #9, D3
                          Add 9 to contents of D3 and store result in D3.

                                                                 •OP-code word is at location i.
       i                   D67C         OP-code word
                                                                 •Operand 9 is in the extension
       i +2                 9           Immediate operand

       i +4
                                                                 word at location i+2.
                                                                 •After the OP-code word is fetched
                                                                 PC points to i+2.
D3            25                  D3             34
                                                                 •After the extension word is
PC            i                   PC            i+4
                                                                 fetched, PC points to i+4.
                                                                 •Contents of D3 before execution
           Before                                After
      instruction fetch                  instruction execution   are 25, and after execution are 34.

   Assembly language

 Instructions can operate on operands of three sizes, size of
  the operands must be indicated:
    Size of the operand is indicated in the operation mnemonic,
     using L for long-word, W for word, and B for byte.
    ADD.L indicates ADD operation with operand size long-word.
 Representation of numbers:
    Default representation is in the decimal form.
    Prefix $ is used for hexadecimal, and % for binary.
 Representation of Alphanumeric characters:
    Placed within quotes, replaced by the assembler with their
     ASCII codes.
    Several characters may be placed in a string between quotes.

   Assembler directives

 ORG: Starting address of an instruction or data block.
 EQU: Equating names with numerical values
 DC (Define Constant): Data constants.
      Size indicator may be appended to specify the size of the data
       constants. DC.B, DC.W, DC.L.
 DS (Define Storage): Reserve a block of memory.
 Names can be associated with memory locations using labels
  as described earlier.

   Condition code flags

 Five condition code flags, stored in the status register.
      N
      Z
      V
      C
      X – Extend flag, set the same way as C flag, but not affected
       by many instructions. Useful for precision arithmetic.
 Since operands can be of three sizes (byte, word and long-
      C and X flags depend on the carry-out from bit positions 7, 15
       and 31.

   Branch instructions

 Recall that a conditional branch instruction causes program
  execution to continue with the instruction at the branch
  target address if the condition is met, else the instruction
  immediately following the branch is executed.
      Branch target address is computed by adding an offset to the
 Branch instructions with two types of offset, 8 and 16 bit.
 Branch instructions with 8-bit offset:
    Offset is included in the OP-code word.
    Branch target address is within –127 to 128 of the value in PC.
    PC contents are incremented at each fetch, offset defines the
     distance from the word that follows the branch instruction OP-
     code word.

   Branch instructions (contd..)

 Branch instructions with a 16-bit offset:
    Offset is specified in an extension word following the OP-code
    Branch target address can be in the range of +32K to –32K
     from the value in PC.
    Offset is the distance from the extension word to the branch
 16 conditional branch instructions, each with two offsets.
 1 unconditional branch instruction.

   Stacks and subroutines

 Stack can be implemented using any of the address
  registers, with the help of autoincrement and
  autodecrement addressing modes.
 Register A7 is designated as the processor stack pointer,
  and it points to the processor stack.
      Stack used by the processor for all operations that it performs
       automatically, such as subroutine linkage.
 Two different stack pointer registers, for two modes of
      Supervisor mode: All machine instructions can be executed.
      User mode: Certain privileged instructions cannot be executed.
      Application programs: user mode.
      System software: supervisor mode.

   Stacks and subroutines (contd..)

 Stack may be used for:
    Subroutine linkage mechanism.
    Passing parameters to a subroutine and returning result from
     the subroutine.
 Branch-to-Subroutine (BSR) is used to call a subroutine:
      Causes the contents of the PC to be pushed onto the stack.
 Return from Subroutine (RTS) is used to return from a
      Causes the return address at the top of the stack to be popped
       into the PC.

 Simple programs in 68000 assembly language.

 Add the contents of memory locations A and B, and place the result in C.
                    Size of operands A and B is word.

Recall that:
  - For a two-operand instruction, one of the operands has to be placed in a
    data register D0 through D7.

 MOVE A, D0           Move A to register D0.
 ADD B, D0            Add the contents of location B to D0 and store the
                        result in D0.
 MOVE D0, C           Transfer the result in register D to location C.

    Simple programs in 68000 assembly language.

A = 201150                63910

B = 201152              - 21510
                                                         •Add the contents of A and B,
   201200            OP-code word                        and place the result in location
                                               MOVE A,D0 C.
   201202                 20
   201204                1150                            •Size of the operands at locations
   201206            OP-code word
                                                         A and B is 16 bits.
                                                         •A, B, and C and the program
   201208                 20
                                               ADD B,D0 to add is stored in the memory
   20120A                1152
   20120C            OP-code word
   20120E                 20
                                               MOVE D0,C
   201210                2200

C = 202200

             After execution, [202200] = 424

 Simple programs in 68000 assembly language

Program to add A and B, and store the result in C with assembler directives.

                               Memory                Addressing
                               address               or data
                               label     Operation   information

        Assemblerdirectives       C      EQU         $202200
                                         ORG         $201150
                                  A      DC.W        639
                                  B      DC.W        – 215
                                         ORG         $201200
        Statemen that                    MOVE        A,D0
         generate hine                   ADD         B,D0
         instructions                    MOVE        D0,C
        Assembler irective               END

Simple programs in 68000 assembly language.
       Add N numbers:
         - The first number is stored at the starting address NUM1.
         - The count of entries to be added is stored at address N.
         - Store the result at location SUM.
         - Size of each number to be added is Word.

       MOVE.L      N,D1          N con  tains n, the number of entries
                                   to be added, and D1 is usedas
                                   a coun that determineshow
                                   many times to executethe loop.
       MOVEA.L     #NUM1,A2      A2 is usedas a pointer to the list entries.
                                   It is initialized to NUM1, the address
                                   of the first en .
       CLR.L       D0            D0 is used to accum    ulate the sum.
LOOP   ADD.W       (A2)+,D0                  e
                                 Successiv numbers are added in D0.
       SUBQ.L      #1,D1                      t
                                 Decremen the counter.
       BGT         LOOP          If [D1]> 0, executethe loop again.
       MOVE.L      D0,SUM        Store the sum in SUM.


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