Verification and Validation of Programmable Logic Devices James A. Cercone1), Michael A. Beims2) Presented by Kenneth G. McGill3) 1) West Virginia University – Institute of Technology 2) Science Applications International Corporation 3) National Aeronautics and Space Administration’s IV&V Facility Abstract attributed in part to the lack of such standards, procedures or guidelines. The usage of Programmable Logic Devices Presently, NASA has provided no clear guidance (PLDs) is becoming commonplace within NASA on the software aspects (design and development) of projects, facilities, and research. Programmable PLDs, nor on how to assure the safety, reliability, or Logic Devices often replace older control systems, quality of these hybrid devices. Considering the NASA facilities, and programmable logic chips, such current practice where PLDs undergo limited software as Field Programmable Gate Arrays (FPGAs), are analysis and testing and are typically tested for being employed to create custom capabilities within functionality as a hardware item, software assurance satellites and instrumentation. engineers rarely verify the process used to develop the coding for the devices, nor the end software “product.” 1. Introduction Testing is typically limited to testing the software design and simply verifying the checksum of Programmable Logic Devices (PLDs), also known programmed devices. As the application of PLDs as Field Programmable Gate Arrays (FPGAs) are becomes more widespread, especially in mission essentially hybrids of hardware and software. While critical applications, the means to verify and validate essentially hardware devices, PLDs implement their design and functionality will be essential. software logic programs. This hybrid aspect of PLDs PLD software designs are presently tested for is not being sufficiently addressed when the devices are functionality, boundary conditions, and operational developed, tested, and validated. Presently, within the simulation but unlike main stream software, most PLD NASA culture, PLDs are essentially viewed as software designs are not subjected to formal hardware and tested for desired functionality. In Verification and Validation, not to mention essence, successful functional testing is the primary Independent Verification and Validation practices. criteria for releasing PLD/FPGA logic based projects Considering the accepted fact that detecting and fixing into production. The software development processes defects at the design phase of the logic is much simpler and techniques employed to produce the software and less expensive than in later phases, the objective of implemented in the PLDs are usually overlooked. this research is to develop a methodology that V&V A recent survey conducted within the NASA and IV&V analysts can apply to the software aspects of Centers intended to identify projects, facilities, and PLDs in the earlier phases of PLD development. NASA organizations that might use PLDs revealed that This research aims to identify PLD/FPGA specific their usage at NASA is widespread and varied. The design fault characteristics and then explore the survey also indicated that PLDs are used in safety- feasibility of applying existing inspection methods (e.g. related projects and facilities as well as in pure research Fagan and Gibbs) that may be candidates for direct environments. Additionally, the survey revealed that application to PLD/FPGA designs. Once a suitable set approximately two-thirds (2/3) of all the projects of methods has been identified, the research will result surveyed did not incorporate the use of any standards, in the development of modifications to the design procedures, or project guidelines in the development of phase, peer and design reviews to incorporate those the software implemented in PLDs, which may be methods, and to test these methods by providing Verification and Validation on a NASA case study.