VHDL Process Models by SanjuDudeja

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									VHDL Process Model for Simple Register:

Process (clock, Reset)

Begin

        If Reset = ‘1’ then Q <= ‘0000’;

        Else Rising_Edge (clock) then Q <= D;

        End if;

End process;



VHDL Process Model for Shift Register:

Signal QINT: std_logic_vector (3 downto 0);

Process (clock, Reset)

Begin

        If Reset = ‘1’ then QINT <= ‘0000’;

        Else Rising_Edge (clock) then QINT <= QINT (2 downto 0), SIN;

        End if;

End process;

Q <= QINT;

    -   Is reset synchronous or asynchronous?

    -   Is it shifting left or right?



 

								
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