PLA

Document Sample
PLA Powered By Docstoc
					Philips Semiconductors Programmable Logic Devices                                                                        Product specification


  Programmable logic array
                                                                                                                                   PLS173
  (22 × 42 × 10)


DESCRIPTION                                         FEATURES                                 PIN CONFIGURATIONS
The PLS173 is a two-level logic element             • I/O propagation delay: 30ns (max.)                           N Package
consisting of 42 AND gates and 10 OR gates
with fusible link connections for programming       • 12 inputs                                           I0 1                       24 VCC
I/O polarity and direction.
                                                    • 42 AND gates                                        I1 2                       23 B9
All AND gates are linked to 12 inputs (I) and
10 bidirectional I/O lines (B). These yield
                                                    • 10 OR gates                                         I2 3                       22 B8

variable I/O gate configurations via 10             • 10 bidirectional I/O lines                          I3 4                       21 B7


                                                    • Active-High or -Low outputs
direction control gates (D), ranging from 22                                                              I4 5                       20 B6
inputs to 10 outputs.                                                                                     I5 6                       19 B5

On-chip T/C buffers couple either True (I, B)       • 42 product terms:                                   I6 7                       18 B4
or Complement (I, B) input polarities to all          – 32 logic terms                                    I7 8                       17 B3
AND gates, whose outputs can be optionally            – 10 control terms
                                                                                                          I8 9                       16 B2
linked to all OR gates. Their output polarity, in
turn, is individually programmable through a        • Ni-Cr programmable links                            I9 10                      15 B1
set of EX-OR gates for implementing                 • Input loading: –100µA (max.)                       I10 11                      14 B0
AND/OR or AND/NOR logic functions.
                                                    • Power dissipation: 750mW (typ.)                   GND 12                       13 I11
The PLS173 is field programmable, enabling
the user to quickly generate custom patterns        • 3-State outputs                         N = Plastic DIP (300mil-wide)

using standard programming equipment.               • TTL compatible                                               A Package
Order codes for this device are listed below.                                                            I3   I2   I1   I0 VCC B9 B8
                                                                                                         4    3     2   1     28    27   26
                                                    APPLICATIONS                                NC 5                                          25 NC
                                                    • Random logic                               I4 6                                         24 B7

                                                    • Code converters                            I5 7                                         23 B6

                                                    • Fault detectors                            I6 8                                         22 B5


                                                    • Function generators
                                                                                                 I7 9                                         21 B4

                                                                                                 I8 10                                        20 B3
                                                    • Address mapping                           NC 11                                         19 NC

                                                    • Multiplexing                                       12   13   14   15    16    17   18
                                                                                                         I9   I10 GND I11 B0 B1 B2

                                                                                              A = Plastic Leaded Chip Carrier




ORDERING INFORMATION
                         DESCRIPTION                                            ORDER CODE                    DRAWING NUMBER

   24-Pin Plastic Dual-In-Line 300mil-wide                                       PLS173N                                0410D

   28-Pin Plastic Leaded Chip Carrier                                            PLS173A                                0401F




October 22, 1993                                                           25                                                      853–0324 11164
Philips Semiconductors Programmable Logic Devices                                                                               Product specification

  Programmable logic array
                                                                                                                                   PLS173
  (22 × 42 × 10)


LOGIC DIAGRAM

                                                     (LOGIC TERMS–P)                                (CONTROL TERMS)


             I0   1

             I1   2

             I2   3

             I3   4

             I4   5

             I5   6

             I6   7

             I7   8

             I8   9

             I9 10

            I10 11

            I11 13

                      B0


                      B1

                      B2

                      B3


                      B4

                      B5

                      B6

                      B7


                      B8

                      B9



                                                                                           S9   D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
                                                                                                                                   23 B9
                                                                                      X9
                                                                                           S8
                                                                                                                                   22 B8
                                                                                      X8
                                                                                           S7
                                                                                                                                   21 B7
                                                                                      X7
                                                                                           S6
                                                                                                                                   20 B6
                                                                                      X6
                                                                                           S5
                                                                                                                                   19 B5
                                                                                      X5
                                                                                           S4
                                                                                                                                   18 B4
                                                                                      X4
                                                                                           S3
                                                                                                                                   17 B3
                                                                                      X3
                                                                                           S2
                                                                                                                                   16 B2
                                                                                      X2
                                                                                           S1
                                                                                                                                   15 B1
                                                                                      X1
                                                                                           S0
                                                                                                                                   14 B0
                                                                                      X0
                           31            24 23             16 15       8 7        0


 NOTES:
 1. All programmed ‘AND’ gate locations are pulled to logic “1”.
 2. All programmed ‘OR’ gate locations are pulled to logic “0”.
 3.      Programmable connection.




October 22, 1993                                                             26
Philips Semiconductors Programmable Logic Devices                                                                                Product specification

  Programmable logic array
                                                                                                                                       PLS173
  (22 × 42 × 10)


FUNCTIONAL DIAGRAM                                                                             LOGIC FUNCTION
                          P31                 P0            D0       D9                                   TYPICAL PRODUCT TERM:
                                                                                                             Pn = A ⋅ B ⋅ C ⋅ D ⋅ . . .
          I0
                                                                                                          TYPICAL LOGIC FUNCTION:
                                                                                                             AT OUTPUT POLARITY = H
                                                                                                                 Z = P0 + P1 + P2 . . .


                                                                                                             AT OUTPUT POLARITY + L
                                                                                                                 Z = P0 + P1 + P2 + . . .
         I11                                                                                                     Z = P0 ⋅ P1 ⋅ P2 ⋅ . . .

               B0

                                                                                                 NOTES:
                                                                                                 1. For each of the 10 outputs, either function Z
                                                                                                    (Active-High) or Z (Active-Low) is available, but not
                                                                                                    both. The desired output polarity is programmed
               B9
                                                                                                    via the EX-OR gates.
                                                                                                 2. ZX, A, B, C, etc. are user defined connections to
                                                                                                    fixed inputs (I), and bidirectional pins (B).


               S9
                                                                                        B9
                                                    X9




               S0
                                                                                        B0
                                                    X0




ABSOLUTE MAXIMUM RATINGS1                                                                      THERMAL RATINGS
                                                                RATING                                           TEMPERATURE
 SYMBOL                         PARAMETER                  Min        Max         UNIT           Maximum junction                                150°C
  VCC               Supply voltage                                       +7       VDC            Maximum ambient                                  75°C
  VIN               Input voltage                                     +5.5        VDC
                                                                                                 Allowable thermal rise                           75°C
  VOUT              Output voltage                                    +5.5        VDC            ambient to junction
  IIN               Input currents                         –30        +30          mA
                                                                                               The PLS173 is also processed to military
  IOUT              Output currents                                   +100         mA          requirements for operation over the military
                                                                                               temperature range. For specifications and
  Tamb              Operating free-air temperature range    0         +75          °C
                                                                                               ordering information, consult the Philips
  Tstg              Storage temperature range              –65        +150         °C          Semiconductors Military Data Handbook.
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
   is a stress rating only. Functional operation at these or any other condition above those
   indicated in the operational and programming specification of the device is not implied.




October 22, 1993                                                    27
Philips Semiconductors Programmable Logic Devices                                                                     Product specification

  Programmable logic array
                                                                                                                            PLS173
  (22 × 42 × 10)


DC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V
                                                                                                             LIMITS
 SYMBOL                       PARAMETER                            TEST CONDITIONS                   MIN     TYP1     MAX       UNIT
  Input   voltage2
  VIL           Low                                                    VCC = MIN                                      0.8         V
  VIH           High                                                   VCC = MAX                      2.0                         V
  VIC           Clamp3                                           VCC = MIN, IIN = –12mA                       –0.8    –1.2        V
  Output    voltage2
                                                                       VCC = MIN
  VOL           Low4                                                   IOL = 15mA                                     0.5         V
  VOH           High5                                                  IOH = –2mA                     2.4                         V
  Input current9
                                                                       VCC = MAX
  IIL           Low                                                    VIN = 0.45V                                    –100       µA
  IIH           High                                                    VIN = VCC                                     40         µA
  Output current
                                                                       VCC = MAX
  IO(OFF)       Hi-Z state8                                            VOUT = 5.5V                                    80         µA
                                                                      VOUT = 0.45V                                    –140
  IOS           Short circuit3, 5, 6                                    VOUT = 0V                    –15              –70        mA
  ICC           VCC supply    current7                                 VCC = MAX                              150     170        mA
  Capacitance
                                                                        VCC = 5V
  IIN           Input                                                   VIN = 2.0V                             8                  pF
  CB            I/O                                                     VB = 2.0V                             15                  pF
NOTES:
1. All typical values are at VCC = 5V, Tamb = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs VIL applied to I11. Pins 1–5 = 0V, Pins 6–10 = 4.5V, Pin 11 = 0V and Pin 13 = 10V.
5. Same conditions as Note 4 except Pin 11 = +10V.
6. Duration of short circuit should not exceed 1 second.
7. ICC is measured with I0 and I1 = 0V, and I2 – I11 and B0 – B9 = 4.5V. Part in Virgin State.
8. Leakage values are a combination of input and output leakage.
9. IIL and IIH limits are for dedicated inputs only (I0 – I11).




October 22, 1993                                                      28
Philips Semiconductors Programmable Logic Devices                                                                                                                Product specification

  Programmable logic array
                                                                                                                                                                      PLS173
  (22 × 42 × 10)


AC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 470Ω, R2 = 1kΩ
                                                                                                         TEST                               LIMITS
 SYMBOL                      PARAMETER                        FROM                 TO                 CONDITION                  MIN         TYP              MAX           UNIT
    tPD          Propagation      delay2                      Input ±       Output ±                    CL = 30pF                                20              30          ns
    tOE          Output enable1                               Input ±       Output –                    CL = 30pF                                20              30          ns
    tOD          Output disable1                              Input ±       Output +                    CL = 5pF                                 20              30          ns
NOTES:
1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
   closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
   voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM                                             TEST LOAD CIRCUIT
 +3.0V
                                               90%
                                                                                                                         VCC          +5V        S1

                                                       10%
   0V
                                                                    C1                  C2                                                                            R1
                 5ns        tR     tF       5ns
                                                                                                                   I0                 BY

 +3.0V
                                                       90%                                                                                                  R2              CL
                                                                                             INPUTS                        DUT
                                                                                                                   I11
                                    10%                                                                            BW
   0V

                5ns                         5ns                                                                    BX                 BZ
                                                                                                                           GND                   OUTPUTS
  MEASUREMENTS:
  All circuit delays are measured at the +1.5V level
  of inputs and outputs, unless otherwise specified.
                                                              NOTE:
                       Input Pulses                           C1 and C2 are to bypass VCC to GND.



TIMING DEFINITIONS                                           TIMING DIAGRAM
 SYMBOL                    PARAMETER
                                                                                                                                                                      +3V
  tPD             Propagation delay between                                 I, B                 1.5V                          1.5V                    1.5V
                  input and output.                                                                                                                                   0V

  tOD             Delay between input change
                  and when output is off (Hi-Z
                  or High).                                                                                                                                           VOH
                                                                              B                             1.5V                            VT                1.5V
  tOE             Delay between input change                                                                                                                          VOL
                  and when output reflects
                                                                                                  tPD                          tOD                    tOE
                  specified output level.




October 22, 1993                                                                        29
Philips Semiconductors Programmable Logic Devices                                                                                                     Product specification

   Programmable logic array
                                                                                                                                                            PLS173
   (22 × 42 × 10)


LOGIC PROGRAMMING                                             PROGRAMMING AND
The PLS173 is fully supported by industry                     SOFTWARE SUPPORT
standard (JEDEC compatible) PLD CAD                           Refer to Section 9 (Development Software)
tools, including Philips Semiconductors                       and Section 10 (Third-Party
SNAP, Data I/O Corporation’s ABEL™, and                       Programmer/Software Support) of this data
Logical Devices Incorporated’s CUPL™                          handbook for addtional information.
design software packages.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and                        OUTPUT POLARITY – (B)
CUPL also accept, as input, schematic
capture format.
                                                                         S                                                         S
PLS173 logic designs can also be generated                                                                          B                                                     B
using the program table entry format detailed                                           X                                                  X

on the following pages. This program table
entry format is supported by the Philips
Semiconductors SNAP PLD design software
package.
                                                                             ACTIVE LEVEL             CODE                             ACTIVE LEVEL         CODE
To implement the desired logic functions, the                                HIGH1                       H                                 LOW               L
state of each logic variable from logic                                  (NON-NVERTING)                                                 (INVERTING)
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.

AND ARRAY – (I, B)

                                  I, B                                       I, B                                          I, B                                       I, B
       I, B                                        I, B                                           I, B                                     I, B
                                  I, B                                       I, B                                          I, B                                       I, B




                              P, D                                      P, D                                            P, D                                       P, D


              STATE            CODE                       STATE         CODE                              STATE         CODE                      STATE            CODE
         INACTIVE1, 2            O                         I, B           H                                  I, B         L                    DON’T CARE            –



OR ARRAY – (B)                                                                                                            VIRGIN STATE
                                                                                                                          A factory shipped virgin device contains all
                                                                                                                          fusible links intact, such that:
                         P                                                          P                                     1. All outputs are at “H” polarity.
                                                                                                                          2. All Pn terms are disabled.
                                               S                                                      S
                                                                                                                          3. All Pn terms are active on all outputs.



                  Pn STATUS              CODE                            Pn STATUS               CODE
                   ACTIVE1                A                               INACTIVE                •
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
   (inactive) AND gates Pn, Dn.
2. Any gate Pn, Dn will be unconditionally inhibited if both the True and Complement of any input
   (I, B) are left intact.




ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.


October 22, 1993                                                                            30
                              AND                                                                OR

                                                                                                                                 NOTES                                                                                 CUSTOMER NAME
                                                                                           ACTIVE          A
                                                                                                                B(0)             1. The PLA is shipped with all links intact. Thus a background
                   INACTIVE     0                                                          INACTIVE                                 of entries corresponding to states of virgin links exists in the
                   I, B         H                                                                                                   table.




October 22, 1993
                                    I, B(I)                                                 CONTROL                                 (Shown BLANK for clarity.)                                                         PHILIPS DEVICE #
                   I, B         L
                                                                                                                                 2. Unused I and B bits in the AND array must be programmed
                   DON’T CARE   —                                                          HIGH       H                             Don’t Care (—).
                                                                                                           (POL)
                                                                                                                                                                                                                                                                                                                   PROGRAM TABLE

                                                                                           LOW        L                          3. Unused product terms can be left blank.                                            PROGRAM TABLE #                     REV         DATE
                                                                                                                                                                                                                                                                                                                                   (22 × 42 × 10)




                    VARIABLE
                                                                                                                                                                                                                                                                                   T




                                                                                                                                                                                                                                           9
                                                                                                                                                                                                                                               8
                                                                                                                                                                                                                                                   7
                                                                                                                                                                                                                                                       6
                                                                                                                                                                                                                                                           5
                                                                                                                                                                                                                                                               4
                                                                                                                                                                                                                                                                   3
                                                                                                                                                                                                                                                                       2
                                                                                                                                                                                                                                                                           1
                                                                                                                                                                                                                                                                               0
                                                                                                                                                                                                                                                                                   E
                                                                                                                                                                                                                                                                                   R
                                                                                                                                                                                                                                                                                   M




                                                                                                                                                                                                                                 11




                                                                                                                            31
                                                                                                                                  30
                                                                                                                                       29
                                                                                                                                            28
                                                                                                                                                 27
                                                                                                                                                      26
                                                                                                                                                           25
                                                                                                                                                                24
                                                                                                                                                                     23
                                                                                                                                                                          22
                                                                                                                                                                               21
                                                                                                                                                                                    20
                                                                                                                                                                                         19
                                                                                                                                                                                              18
                                                                                                                                                                                                   17
                                                                                                                                                                                                        16
                                                                                                                                                                                                             15
                                                                                                                                                                                                                  14
                                                                                                                                                                                                                       13
                                                                                                                                                                                                                            12
                                                                                                                                                                                                                                      10




                                                                       D0
                                                                            D1
                                                                                 D2
                                                                                      D3
                                                                                           D4
                                                                                                D5
                                                                                                      D6
                                                                                                           D7
                                                                                                                D8
                                                                                                                       D9




                                       PIN
                      NAME                                                                                                                                                                                                                                                         11 10
                                                                                                                                                                                                                                                                                   9




                                       13 11 10
                                                                                                                                                                                                                                                                                   8




                                       9
                                                                                                                                                                                                                                                                                                                                   Programmable logic array




                                                                                                                                                                                                                                                                                   7




                                       8
                                       7
                                                                                                                                                                                                                                                                                   6
                                                                                                                                                                                                                                                                                                                                                              Philips Semiconductors Programmable Logic Devices




                                                                                                                                                                                                                                                                                           I




                                       6
                                                                                                                                                                                                                                                                                   5




                                       5
                                                                                                                                                                                                                                                                                   4
                                                                                                                                                                                                                                                                                   3




                                       4
                                       3
                                                                                                                                                                                                                                                                                   2




                                       2
                                                                                                                                                                                                                                                                                   1




                                       1
                                                                                                                                                                                                                                                                                   0
                                                                                                                                                                                                                                                                                                  AND




31
                                                                                                                                                                                                                                                                                   9
                                                                                                                                                                                                                                                                                   8
                                                                                                                                                                                                                                                                                   7
                                                                                                                                                                                                                                                                                   6
                                                                                                                                                                                                                                                                                   5
                                                                                                                                                                                                                                                                                           B(I)
                                                                                                                                                                                                                                                                                   4
                                                                                                                                                                                                                                                                                   3
                                                                                                                                                                                                                                                                                   2
                                                                                                                                                                                                                                                                                   1
                                                                                                                                                                                                                                                                                   0




                                       23 22 21 20 19 18 17 16 15 14
                                                                                                                                                                                                                                                                                   9
                                                                                                                                                                                                                                                                                   8
                                                                                                                                                                                                                                                                                   7
                                                                                                                                                                                                                                                                                   6
                                                                                                                                                                                                                                                                                   5
                                                                                                                                                                                                                                                                                                  OR
                                                                                                                                                                                                                                                                                           B(0)
                                                                                                                                                                                                                                                                                   4
                                                                                                                                                                                                                                                                                                        POLARITY




                                                                                                                                                                                                                                                                                   3
                                                                                                                                                                                                                                                                                   2
                                                                                                                                                                                                                                                                                   1
                                                                                                                                                                                                                                                                                   0




                                       23 22 21 20 19 18 17 16 15 14
                                                                                                                                                                                                                                                                                                                                          PLS173
                                                                                                                                                                                                                                                                                                                                                              Product specification
Philips Semiconductors Programmable Logic Devices                                                       Product specification

  Programmable logic array
                                                                                                           PLS173
  (22 × 42 × 10)


SNAP RESOURCE SUMMARY DESIGNATIONS
                                       P31                P0               D0            D9
                                         DIN173
                           I0
                                         NIN173




                          I11

                                B0                                              DIN173
                                                                                NIN173




                                B9

                                                    AND                         CAND
                                                                                              TOUT173

                                S9
                                                                                                  B9
                                                                X9

                                                               OR


                                S0
                                                                                                 B0
                                                                X0
                                                                     EXOR173




October 22, 1993                                               32

				
About if any file u wil find copyright contact me it will be remove in 3 to 4 buisnees days. add me on sanjaydudeja007@gmail.com or visit http://www.ohotech.com/