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Introduction to AlteraBoard

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					                     CSCE 488


        An Introduction to
FPGA and SOPC Development Board
      (Adapted from material developed by Yong Wang
                     & Stefan Hass)




                   Yuyan Xue
Outline

  •   What are Programmable Logic Devices?
  •   Architecture and Examples
  •   Why FPGA?
  •   Vendors and Device Series
  •   Development on Altera Devices
  •   Summary


                   CSCE488-2005              2
Programmable Logic Devices
Programmable Logic Devices

• Programmable digital integrated circuit
• Desired functionality is implemented by configuring
  on-chip logic blocks and interconnections
  (compared with ASIC)
• Developers only care about the logic design but
  not the internal hard-wire connection ( softwarelize
  the hardware design)



                        CSCE488-2005                     4
ASIC Vs. Programmable Logic Device
ASIC (Application Specific         Programmable Logic
Integrated Circuit)                Device
Longer design cycle and            Shorter design cycle and
costlier ECO (Engineering          cheaper ECO
Change order)
Faster performance                 Longer delay
Lower cost if produced in high     Higher cost per chip
volume
>10,000 chips                      Good for medium to low
                                   volume products
Energy saving                      More power consumption

                             CSCE488-2005                     5
Type of Programmable Logic Devices


 • PLD (Programmable Logic Device)

 • CPLD (Complex Programmable Logic Device)

 • FPGA (Field Programmable Gate Array)




                    CSCE488-2005              6
Architecture and Examples
PLD - Sum of Products
Programmable AND array followed by fixed fan-in OR gates
   A    B       C    Programmable switch or fuse
                                 Product Terms

                                       f1 = A • B • C + A • B • C




                                       f2 = A • B + A • B • C

                              any logical function can be written in SOP
        AND plane             (Sum of Products) form
                              =>
                              any function can be implemented by AND
                              gates generating products which feed to an
                              OR gate that sums them up
                        CSCE488-2005                                       8
    PLD - Macrocell
    Can implement combinational or sequential logic
                                                       Select
A      B    C                                                   Enable


                                                                         f1

                                           Flip-flop
                                                       MUX
                                           D      Q



                                   Clock




                   AND plane




                           CSCE488-2005                              9
CPLD Structure
Integration of several PLD blocks with a programmable
interconnect on a single chip
             I/O Block




                                                           I/O Block
              I/O Block




                                                            I/O Block
                          •    PLD
                               PLD             PLD
                                               PLD     •
                          •   Block
                              Block           Block
                                              Block    •
                          •                            •




                              Interconnection Matrix
                              Interconnection Matrix
             I/O Block




                                                           I/O Block
              I/O Block




                                                            I/O Block
                          •    PLD
                               PLD             PLD
                                               PLD     •
                          •   Block
                              Block           Block    •
                          •                   Block    •



                                  CSCE488-2005                          10
CPLD Example - Altera MAX7000




       EPM7000 Series Block Diagram


                 CSCE488-2005         11
CPLD Example - Altera MAX7000




            EPM7000 Series Device Macrocell

            CSCE488-2005                  12
FPGA - Generic Structure
FPGA building blocks:                        Logic block    Interconnection switches

•   Programmable logic blocks
    Implement combinatorial and                            I/O
    sequential logic
•   Programmable interconnect
    Wires to connect inputs, outputs
    and different logic blocks




                                       I/O




                                                                                       I/O
•   Programmable I/O blocks
    Special logic blocks at the
    periphery of device for external
    connections


                                                           I/O


                               CSCE488-2005                                            13
FPGA – Basic Logic Element
• LUT(Look Up Table) to implement combinatorial logic
• Register for sequential circuits
• Additional logic (not shown):
   – Carry logic for arithmetic functions
   – Expansion logic for functions requiring more than 4 inputs
                                                    Select



                                                             Out

            A
            B
            C
                     LUT
                     LUT                D      Q

            D

                             Clock



                                CSCE488-2005                       14
Look-Up Tables (LUT)
• Look-up table with N-inputs can be used to implement any
  combinatorial function of N inputs
• LUT is programmed with the truth-table
   A    B   C   D     Z
    0   0   0   0     0                  A
    0   0   0   1     1                  B
    0   0   1   0     1                  C          LUT
                                                    LUT        Z
    0   0   1   1     1                  D
    0   1   0   0     0
    0   1   0   1     1
    0   1   1   0     1                      LUT implementation
    0   1   1   1     1
    1   0   0   0     0
                                         A
    1   0   0   1     1
    1   0   1   0     1                  B
    1   0   1   1     1                                            Z
    1   1   0   0     0
    1   1   0   1     0                  C
    1   1   1   0     0                  D

        Truth-table                      Gate implementation
                          CSCE488-2005                                 15
Other FPGA Building Blocks
• Clock distribution
• Embedded memory blocks
• Special purpose blocks:
  – DSP blocks:
    • Hardware multipliers, adders and registers
  – Embedded microprocessors/microcontrollers
  – High-speed serial transceivers



                        CSCE488-2005               16
Special Features
• Clock management
    – PLL,DLL
    – Eliminate clock skew between external clock input
      and on-chip clock
    – Low-skew global clock distribution network
•   Support for various interface standards
•   High-speed serial I/Os
•   Embedded processor cores
•   DSP blocks
                        CSCE488-2005                  17
Configuration Storage Elements
• SRAM
   – Logical configuration is controlled by the state of SRAM
     bits
   – FPGA needs to be configured at power-on by another
     separated ROM

• Flash
   – Logical configuration is implemented by floating-gate
     transistors that can be turned off by injecting charge onto
     its gate. FPGA itself holds the program
   – reprogrammable, even in-circuit



                            CSCE488-2005                           18
Example: Altera Stratix Series
Why FPGA?

• handle dense logic and memory elements
  offering very high logic capacity
• Easy to revise the logic design
• Lower cost and shorter development cycle
• Complete integrated design environment (IDE)
• Easy to learn and use



                   CSCE488-2005              20
FPGA Vendors
• Altera
• Xilinx
  – Virtex-II/Virtex-4: Feature-packed high-performance
    SRAM-based FPGA
  – Spartan 3: low-cost feature reduced version
  – CoolRunner: CPLDs

• Actel
• Lattice
• QuickLogic

                        CSCE488-2005                      21
Introduction to Altera Devices
•   Programmable Logic Families
     – High & Medium Density FPGAs
        • Stratix™ II, Stratix, APEX™ II, APEX 20K, & FLEX® 10K
     – Low-Cost FPGAs
        • Cyclone™ & ACEX® 1K
     – CPLDs
        • MAX® 7000 & MAX 3000
     – Embedded Processor Solutions
        • Nios™, ExcaliburT™
     – Configuration Devices
        • EPC




                                CSCE488-2005                      22
Nios: The processor in software

• a user-configurable, 16-bit instruction set
  architecture (ISA), general-purpose RISC
  embedded processor
• designers can use the SOPC (system-on-a-
  programmable-chip) Builder system
  development tool to very easily create custom
  processor-based systems

                     CSCE488-2005               23
Development on Altera Devices




             CSCE488-2005       24
What is available?

• Altera Stratix Nios Development Board

• Altera UP2 Development Board




               CSCE488-2005               25
Altera Stratix Nios Development Board




               CSCE488-2005         26
Altera Stratix Nios Development Board

• Stratix EP1S10F780C6
  – 10,570 Logic Elements
  – 920 Kb on-chip memory
• Provide hardware platform for developing
  embedded system
  – Comes pre-programmed with a 32-bit Nios
    processor reference design



                     CSCE488-2005             27
Altera Stratix Nios Development Board
• 8 MB of flash Memory,1MB of static RAM, 16MB of
  SDRAM
• On-board Ethernet MAC/PHY device
• Compact Flash connector hearder
• Two RS-232 DB9 serial ports
• 50MHz oscillator and zero-skew clock distribution
  circuitry
• Four push-button switches
• Dual 7-segment LED display

                      CSCE488-2005                    28
Altera UP2 Development Board




             CSCE488-2005      29
Altera UP2 Development Board

  • EPF10K70RC240-4 device
  • EPM7128SLC-7 device
  • One RS-232 serial port
  • Four push-button switches
  • Dual 7-segment LED display
  • 25.175MHz oscillator

                   CSCE488-2005   30
  FPGA Design Flow

Design Specification       Design Entry


                            Simulation

                            Synthesis


                          Place & Route


                            Simulation


                       Program device & test



                          CSCE488-2005         31
FPGA Design Flow
Design Specification                   Design Entry/RTL Coding
                                       Behavioral or Structural Description of Design


                                             RTL Simulation
                                             • Functional Simulation
                                             • Verify Logic Model & Data Flow
                                             (No Timing Delays)

      LE               Synthesis
                       • Translate Design into Device Specific Primitives
  MEM       I/O


                                      Place & Route
                                      • Map Primitives to Specific Locations inside
                                        Target devices



                                    CSCE488-2005                                        32
FPGA Design Flow
   tclk
          Timing Analysis
          - Verify whether Performance Specifications Were Met
          - Static Timing Analysis




                 Gate Level Simulation
                  - Timing Simulation
                  - Verify whether Design Will Work in Target Device




                                  Program & Test
                                  -Download Design Program to the device
                                  -& Test Device on Board



                   CSCE488-2005                                        33
Design Entry Methods
• Text-based

  – VHDL(Very High Speed
    Integrated Circuit
    Hardware Description
    Language)

  – Verilog HDL




                      CSCE488-2005   34
Block Diagram
Contents of a block can be
  any type of design unit




                         CSCE488-2005   35
State Diagram
• “Bubble” diagram

     • States

     • Conditions

     • Transitions

     • Outputs


• Useful for developing
  control modules

                          CSCE488-2005   36
Program Devices
• Once we verify our design, it
  should be downloaded to the
  FPGA devices
• Designs can be downloaded
  through parallel port in PC to
  the JTAG connector on board
  using download cables
• Designs can also be
  downloaded via the Internet
  to a target device


                           CSCE488-2005   37
Introduction to Altera Design Software
            • Software & Development Tools:
              – Quartus II
                 • Stratix II, Stratix, Stratix GX, Cyclone,
                   APEX II, APEX 20K/E/C, Excalibur, &
                   Mercury Devices
                 • FLEX 10K/A/E, ACEX 1K, FLEX 6000,
                   MAX 7000S/AE/B, MAX 3000A Devices
              – Quartus II Web Edition
                 • Free Version
                 • Not All Features & Devices Included
              – MAX+PLUS® II
                 • All FLEX, ACEX, & MAX Devices


                 CSCE488-2005                                  38
Quartus II Development System
•   Fully-Integrated Design Tool
•   Multiple Design Entry Methods
•   Logic Synthesis
•   Place & Route
•   Simulation
•   Timing & Power Analysis
•   Device Programming
•   SignalTap® II & SignalProbe™ Debug Tools

                     CSCE488-2005              39
Quartus II Operating Environment




               CSCE488-2005        40
Main Toolbar & Modes
                                  Execution Controls
                                                                     Compiler Report
 Window & new file                             Simulation Controls
 buttons             Floorplans




 Project Navigator

                                  CSCE488-2005                                  41
Summary
• Prerequisite
  – Electronics and circuits
  – Digital logic design
  – VHDL
• FPGA
  – Combine technologies in hardware & software
  – Benefits



                       CSCE488-2005               42

				
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