FPGA Architecture

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FPGA Architecture Powered By Docstoc
					               FPGA Architecture
• Assembly of Fundamental Blocks
   – Hierarchical
   – Integration of Different Building Blocks
      •   Logic (Combinational and Sequential)
      •   Dedicated Arithmetic Logic
      •   Clocks
      •   Input/Ouput
      •   Delay Locked Loop
      •   RAM
• Routing (Interconnections)
   – Channeled Architecture
   – Sea-of-Module Architecture
Channel Architecture
Act 3 Architecture
Channeled Routing Structure
     Sea-of-Modules Structure
• Some programmable elements require
  silicon resources
  – SRAM flip-flops
  – ONO antifuse
• Metal-to-metal antifuses are built above the
  – No routing channels
  – Higher density
  – Faster
Virtex Architecture Overview

                   IOB = I/O Block
                   DLL = Delay-locked loop
                   BRAM = Block RAM
                          (4,096 bits ea.)
                   CLB = Configurable Logic
Two Slice Virtex CLB
              UT4090 Architecture

RAM Blocks

Logic Array

RAM Blocks
    MRC Orion

Hierarchical Architecture
  MRC Orion: Level 0

A tier-0 logic tile formed from 16 logic elements
     interfaced to a level-0 routing structure.
     MRC Orion: Level 1

A tier-1 logic tile formed from 16 tier-0 tiles interfaced
              to a level-1 routing structure.
     MRC Orion: Level 2

A tier-2 logic tile formed from 16 tier-1 tiles interfaced
              to a level-2 routing structure.
AT6010 Architecture
Cell-to-cell and Bus-to-bus Connections
AT6010 Architecture
  Busing Network (one sector)
AT6010 Architecture
Symmetrical Array Surrounded by I/O

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