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DYNAMIC PARTIAL RECONFIGURATION

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					   DYNAMIC PARTIAL
   RECONFIGURATION
                 Andrés Upegui
         Logic Systems Laboratory – LSL
École Polytechnique Fédérale de Lausanne - EPFL
                                     Outline

 ♦ Introduction:
         • Reconfigurable Computing
         • FPGAs
 ♦ Xilinx FPGAs architecture
 ♦ Static Configuration
 ♦ Dynamic Reconfiguration
         • Module Based
         • Difference Based
         • Jbits
 ♦ Applications


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                   Reconfigurable computing
 ♦ Methods for execution of algorithms:
         • hardwired technology: high performance
         • software-programmed microprocessors: high flexibility
 ♦ Reconfigurable computing is intended to fill the gap between
   hard and soft, achieving potentially much higher performance
   than software, while maintaining a higher level of flexibility
   than hardware (Compton and Hauck, “Reconfigurable
   computing”, ACM Computing Surveys, June 2002)
 ♦ Reconfigurable computing:
         • systems incorporating some form of hardware programmability
         • when we talk about reconfigurable computing we are usually talking
           about FPGA-based systems design


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                                   FPGAs




                                                                             programmable
                                               programmable                     functions
                                              interconnections


                                                                     configuration

         logic cell   I/O cell
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         Xilinx FPGAs architectures




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         Virtex II Architecture




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           Virtex II Logic Element
     CLB
                                                           Slice




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         Configuration Column Example
                    (XCV50)




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                    Reconfiguration timing

 ♦ Minimal times (SelectMap 50 MHz)
 ♦ Header + frame(s) + dummy frame


                               Minimum reconfiguration time [µs]
                    Bits per
          Device                                                              1 CLB
                    frame        1 frame                1 LUT                         Full Device
                                                                             column
          XCV50       384          2,88                 17,28                 48       1.388,16
          XCV300      672          4,32                 29,52                83,28      4.374
          XCV800     1088           6,4                  47,2                134,24   10.970,72
          XCV1000    1248           7,2                   54                 153,84    58.658




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          Static Reconfiguration




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          Synthesis methodology
          graphic editor                               VHDL


                          schematic
                          schematic

                            partition

                          placement

                             routing

                configuration bit-string
                configuration bit-string

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          Dynamic Reconfiguration




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            Dynamic Partial Reconfiguration
 ♦ Dynamic partial reconfiguration is done when the device is
   active. Except during some interdesign communication,
   certain areas of the device can be reconfigured while other
   areas remain operational and unaffected by the
   reprogramming.
 ♦ Several commercial options :
          • Xilinx Virtex families
          • Altera FPGAs
          • Atmel FPGAs
 ♦ They use partial configuration to achieve run-time
   reconfiguration.


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              Changing LUTs configuration

 ♦ Two styles:
    • Module based: A full module changes between two
      configurations.

          • Difference Based: Open the routed design with FPGA
            editor, modify any LUT function or memory content,
            generate a partial bitstream with bitgen –r.



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                      Module Based Layout




          In order to design the internal logic, it must be used modular design



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                                  Bus Macro




 ♦ Uses horizontal lines that connect CLBs.
          • Limits the size of reconfigurable modules: the width must be a
            multiple of 4, and must be placed on columns multiple of 4.




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                        Constraints

 ♦ The size and the position of a module cannot be changed.
 ♦ Input-output blocks (IOBs) are exclusively accessible by
   contiguous modules.
 ♦ Reconfigurable modules can communicate only with neighbor
   modules, and it must be done through bus macros.
 ♦ No global signals are allowed (e.g., global reset), with the
   exception of clocks that use a different bitstream and routing
   channels.




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      Difference Based Partial Reconfiguration

 ♦ Small changes on the FPGA configuration
 ♦ Manually done using the FPGA Editor
 ♦ What can be modified?
          •   LUTs equations
          •   BRAM contents and BRAM write modes
          •   I/O standards and pull-ups or pull-downs on external pins
          •   muxes that invert polarity,
          •   Flipflop initialization and reset values,
 ♦ What cannot be modified?
          • Routing – very dangerous: internal contentions.




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          How to change a LUT equation




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          How to change BRAM contents




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                            Problems

 ♦ It must be manually done
 ♦ Lack of automation
 ♦ In complex designs it is difficult to find the component you
   want to modify.




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                      Our solution

 ♦ Hard Macros
 ♦ Hard Macros must be also manually done in the FPGA_editor.
   But just once!!
 ♦ They can be placed using placement constraints.
 ♦ Once they are placed they can be automatically modified.




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             FAQ: Can FPGAs perform
               self-reconfiguration?
 ♦ YES!!!
 ♦ First solution:
    • Design your own Jtag programmer (in VHDL).
    • Access FPGA’s own configuration port.
    • Limitations: Dynamic feature needed (not supported for
      Spartan families)
 ♦ Second solution:
    • Virtex II and IV include an ICAP module
      (Internal Configuration Access Port)
    • ICAP access the SelectMap port.


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             More about Modular and Difference
                   based reconfiguration?

 ♦ A tutorial:
   A Module-Based Dynamic Partial Reconfiguration Tutorial
          http://ic2.epfl.ch/~gmermoud/files/publications/DPRtutorial.pdf


 ♦ The reference:
   Xilinx application note 290
   http://direct.xilinx.com/bvdocs/appnotes/xapp290.pdf
   including design files in:
   http://www.xilinx.com/bvdocs/appnotes/xapp290.zip

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                        Another option:                            JBits

     ♦ JBits is a Java API used for describing circuits
          • Circuits are created when the java code is executed
          • Structural description
          • Blocks are generated in run-time, depending on: available area,
            desired speed, …
          • RTP Cores: run-time parameterizable cores
     ♦ Advantages of JBits
          • Design Flow compatible with RTR (run-time reconfiguration)
          • Manipulation of configuration bitstreams.
          • Easy access to low level FPGA details
     ♦ Disadvantage: Research tool !!!!! – not well documented


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                       JBits : The tools

 ♦ XHWIF : Xilinx HardWare InterFace API : interface that allows
   communicating with FPGA boards.

 ♦ VirtexDS : Simulator tied to XHWIF that allows testing
   bitstreams without using the hardware.

 ♦ BoardScope : Interactive tool for design debugging.

 ♦ WaveForm Viewer : time diagram visualization for RTPCores.



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              JBits : Design Flow and architecture




          Architecture sommaire de
          l’API JBits


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          JBits : Les outils : Boardscope




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                   More about Jbits?

 ♦ Where to get it?
   http://www.xilinx.com/labs/projects/jbits/
 ♦ A tutorial:
   http://www.hopsys.com/whitepaper.html




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          APLICATIONS




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            Evolving Artificial Neural Networks
                                                              Connection matrix

          network           5                                                  From 1 to 4
                                                                      1→        0   0   1    1   0
                    3           4                                     2→        0   0   0    1   1




                                                               from
                                                                      3→        1   0   0    0   1
                                                                      4→        0   0   0    1   1
                                                                      5→        0   0   0    0   0
                        1           2                                                   to


                                                genome
                                00110 00011 10001 00011 00000


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               Evolvable Hardware Platform

♦ Partial reconfiguration would allow to test different possible combinations




                                                                                      Different possible
                                  Module 2




                                                                           Module n
                       Module 1




                                                                                      configurations for
                                             FPGA                                     module n




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                            Topology Evolution
Genotype
 Log2 (# of possible            The genome
 configurations)




                                                                                    BUS MACRO

                                                                                                BUS MACRO
       m1      m2                  mn


                    Number of
                    modules                                                                                   Phenotype


Genetic operators
                Mutation
                                                                               no

                Cross-over                                             End of
                                                                                                            Test and
                                                         yes
                                                                     generation?                            compute
                                                                                                             fitness

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          Other Evolvable Hardware Systems

 ♦ Fuzzy systems




                   Fuzzifi-
                                            Inference Defuzzy-
                    cation                           +
                                              Rules    fication
                                BUS MACRO




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                   A Hard Macro Example

          For evolving Fuzzy rules we designed a rule macro




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                MODULAR ROBOTICS
          YaMoR (Yet another Modular Robot)




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          YaMoR units




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          Some initial configurations with YaMoR




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          Some initial configurations with YaMoR




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          But, wires must be removed!!




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          Self-Reconfigurable Modular Robots:
           Mechanic dynamic reconfiguration

            M-TRAN II from AIST




            Video from AIST
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          Reconfigurable Controller




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          Bus Macro for Spartan-3




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                                           Reconfigurable
                                           Functional-unit
                                                                     ♦ Processor architecture




                                             BUS MACRO
                                           Reconfigurable
                                           Functional-unit
                                             BUS MACRO




    Andres Upegui - Eduardo Sanchez
Ecole Polytechnique Fédérale de Lausanne
                                                          VLIW
                                                                                                Other Applications



                                                         Processor




                                             BUS MACRO
                                           Reconfigurable
                                           Functional-unit
                                             BUS MACRO
                                           Reconfigurable
                                           Functional-unit
               Other Applications

 ♦ Filter implementation


               Reconfigurable




                                                                                                      Reconfigurable
                                            Reconfigurable


                                                                         Reconfigurable

                                                                                          BUS MACRO
                                BUS MACRO



                                                             BUS MACRO
                  stage 1


                                               stage 2




                                                                                                         stage 4
                                                                            stage 3


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