# Picosecond Timing Project

Document Sample

```					DEVELOPMENT OF A READOUT SYSTEM FOR LARGE SCALE TIME OF
FLIGHT SYSTEMS WITH PICOSECOND RESOLUTION

Considerations and designs for a system of tdc’s with 1psec resolution

CDF IS TAKEN AS AN EXAMPLE ( so we can be definite)
TIME BETWEEN BEAM CROSSINGS =396NS
CHARGED PARTICLES PER COLLISION = APPROX 12
NUMBER OF COLLISIONS/ CROSSING =3
OVERALL SIZE OF DETECTOR ---A CYLINDER 1.5 METER RADIUS AND 3 METER LONG
SIZE OF PROPOSED DETECTOR TILE = 5 CM SQUARE
PROPOSED PIXELS/TILE =4
We require one set of input / output bus lines per 5cm of

circumference which results in 189 lines for a 1.5 meter

radius cylinder. The cylinder is 3 meters long which means

we will have 60 modules per line. Each module covers 5cm

square. The total number of 4-cell modules is then 11,340.

There will be about 1 event every five collisions in each line of

modules assuming 40 charge particles collision

Data generated for each cell per event is about 5 bytes .
We require on set of input/
output bus per 5cm of
circumference which
resultsut tin 189 lines for a
1.5 meter
cylinder is 3 meters long
which means we will have
60 modules per line. Each                                                          60th module

module cover 5cm square.
The total number of 4 cell
modules is then 11,340                       200 clock lines
4 cell module    4 cell mdoule
3meters long

4 cell module    4 cell module

Master
DATA
clock             1 to 200 fanout array
COLLECTION
62.5 mhz             to distribute clocks to
ARRAY
(8 x Fclock)         the indiviual logic cells

4 cell module    4 cell module

4 cell module    4 cell module

PICO-SECOND TOP BLOCK
MCP OUTPUT
PICOSECOND TIMING                               MCP OUTPUT
10PICOSECOND                                                                                     PICOSECOND TIMING
MODULE                                    10PICOSECOND
RISE TIME                                                                                           MODULE
RISE TIME

Module must be
synchronized with system
clock to associate stop
with event time
Clock fan-out buffer and
62.5 MHZ CLOCK IN                    digital output interface
data includes a/d converter
outputs and address of cell                  DIGITAL DATA OUT
2.5252 MHZ DATA                                                              daisy chain to next tube
REQUEST AND                                                                           cell
PIPELINE IN
(396ns period)

MCP OUTPUT                                                             MCP OUTPUT
PICOSECOND TIMING                                                         PICOSECOND TIMING
10PICOSECOND                                                           10PICOSECOND
MODULE                                                                    MODULE
RISE TIME                                                              RISE TIME

4 CELL PICO-SECOND TIMING
MODULE
125 mhz
CLOCK                                                                                  Charging
Fixed current
Low jitter phase locked                  source
oscillator 2GHZ                       200 “I”

2 GHZ clock                                                                                     Pulse width=
STOP                                                                                            K (Tc)
200ns max
fixed
In control        amplifier                                S
SET
Q                         curren                                 range
module                                        tHLT                                                t

Ss
R   CLR
Q                       xfer current                COUNTER CONTROL LINE
switch                   COUNTER IS IN CONTROL
tstart        F1
MODULE.
Start
interval                Tc=tstsrt-
Anode cell of
tHLT                             C     V REF
MCP 10 ps rise time                                                                            fixed
cap             High speed level
High speed level                                    Discharging                          discriminator
fixed current
discriminator                                          sink
1 „I'

“TIME EXPANDER”
PICOSECOND
MODULE
Simplified cell logic
1 0f 4 cells served by
control module
TIME EXPANDER OR DUAL SLOPE PICOSECOND
MODULE --- 1 OF 4 PER MCPT

THIS SIMPLE BLOCK DIAGRAM SHOWS A DISCRIMINATOR TO SET A “PULSE
GENERATE” STATE FLIP FLOP ON THE LEADING EDGE OF THE TUBE OUTPUT
A CURRENT EQUAL TO 200i CHARGES THE CAPACITOR “C” UNTIL THE STATE
FLIP FLOP IS CLEARED AT WHICH TIME THE CAPACITOR IS DISCHARGED AT I
EQUAL TO “i” (200 :1)
THE DISCHARGE TIME WILL BE 200 TIMES LONGER THAN THE CHARGE.
AN OUTPUT DISCRIMINATOR MEASURES THE PERIOD WHILE THE CAPACITOR
IS CHARGED,
THE OUTPUT IS SENT TO THE CONTROL MODULE TO ENABLE A 10GHZ WIDTH-
COUNTER AND ALSO SIGNAL THAT AN EVENT HAS HAPPENED.
THE DIFFICULT TASKS THAT MUST BE PERFORMED ARE:
•THE OSCILLATOR MUST HAE SUB-PICOSECOND JITTER,
•THE CHARGE AND DISCHARGE CURRENT MUST BE A STABLE RATIO
•200 TO 1 IS LARGE
•DISCRIMINATORS MUST HAVE SUB-PICOSECOND STABILITY.
To picosecond
From high speed front end chips
timing modules                                             Pulse width=
200 X width(ps)
(4) 1 GHZ clock
1
outputs
2           3             4

62.5
mhz
SYS                X16 SETUP
PLL
CLK               OSCILLATOR

4bit count out        enable
from PLL
512NS PERIOD                                                                  loop=# of 1ns
DATA            PHASE                                                          ticks
LOCKED                                                                       11 bit           11 bit         11 bit
REQUEST AND                                                                                                                                  11 bit
binary           binary         binary
SYNC                                                                                                                                     binary
RESET                                               counter=                        counter
5 BIT                                                    counter=                    counter=
Gate array                 PS               PS              =
16NS PERIOD                                                                                 PS
PS
COUNTER
CLOCK
S_62.5mhz

Data                                                             data
strobe

4 memory blocks 1/per front end–stores16ns,ns, and ps data

CONTROL BLOCK PULSE WIDTH TO COUNT
DESCRIPTION OF CONTROL BLOCK CASE –DIGITAL
COUNTER TO MEASURE PICOSECOND INTERVAL

INPUT PHASE LOCK LOOP OSCILLATOR-- SYNCHRONIZE WITH SYSTEM CLOCK
GENERATE 1 GHZ CLOCK FOR PICOSECOND CHIPS
GENERATE 5 GHZ CLOCK FOR PICOSECOND COUNTER CLOCK
FAST COUNT CLOCKS REDUCE THE TIME STRETCH IN THE PICOSECOND MODULES
THE 512NS SYNC CLOCK IS TIED TO THE COLLISION EVENT MOMENT AND IS USED
AS AN EVENT TIME MARKER
A 5 BIT COUNTER TO MEASURE 62.5MHZ (16NS) COUNTS AFTER THE SYNC MOMENT
THE PHASE LOCK LOOP HAS AN INTERNAL COUNTER TO REDUCE THE OUTPUT OF
1GHZ TO 62.5MHZ IN THE CONTROL LOOP. THIS COUNT IS RECORDED TO MEASURE
WHICH GHZ TICK (1NS) OCCURRED AT THE EVENT TIME
THE WORD WHICH INCLUDES THE 16NS COUNT,THE NS COUNT AND THE
STRETCHED-TIME COUNT GIVES THE TIME OF THE EVENT RELATIVE TO THE
SUBJECT EVENT CLOCK PULSE.
62.5MHZ
input clcok
Fixed current
Low jitter phase locked             source
oscillator 500 MHZ.

500 MHZ
clock
interval                   SET                       fixed
In control        amplifier                                  S          Q                 curren
module                                             HLT                                       t

Ss
R   CLR
Q                xfer current
F1
switch
start
Start
Sr                             Part of control module
interval
reset                      Differential
Anode cell of                                                            switch                      Output to 11
C
MCP 10 ps rise time
fixed      bit A/D
cap
converter
High speed level
discriminator
SET
S          Q

a/d
converter                                       R   CLR
Q
F2
done                          done
ALTERNATIVE DESIGN:
PICOSECOND TIMING MODULE
Simplified cell logic
1 0f 4 cells served by                                    TIME TO VOLTAGE CONVERTER
control module
DESCRIPTION OF PICOSECOND TO VOLTAGE CONVERTER
CONTAINS THE SAME PRECISION LOCKED OSCILLATOR
THE EVENT PULSE IS DICRIMINATED AND LATCHES A FLIPFLOP TO START A PULSE.
THE PULSE TURNS ON A CURRENT SOURCE “I” TO CHARGE A CAPACITOR “C”.
THE LOCAL CLOCK GENERATES THE END OF THE PULSE AND THE CURRENT IS
INTERUPTED LEAVING A VOLTAGE ON THE CAPACITOR
THE CONTROL MODULE IS SIGNALED TO PERFORM A VOLTAGE CONVERSION (A/D)
A RETURN SIGNAL RESETS THE CAPACITOR TO ITS BASELINE.
From high speed front end
chips
To picosecond timing modules                                                               differential voltages
=k (Pulse width)
(4) 1 GHZ clock                                                                                               and load strobes
outputs
1             2       3         4

62.5mhz
SYS CLK                X16 SETUP
PLL
OSCILLATOR

4bit count out        enable
from PLL
512NS PERIOD                                                                        loop=# of 1ns
DATA               PHASE                                                             ticks
REQUEST AND           LOCKED
11 bit                 11 bit
SYNC                                                                                             11 bit                 11 bit
RESET                                                             binary                 binary
5 BIT                                   binary                 binary
A/D                    A/D
16NS PERIOD         Gate array               A/D                    A/D
COUNTER
CLOCK
S_62.5mhz

Data                                                            data
strobe

4 memory blocks 1/per front end–stores16ns,ns, and ps data

CONTROL MODULE WITH A/D
CONVERTERS
DESCRIPTION OF CONTROL BLOCK PICOSECOND TO VOLTAGE CONVERTER
THIS MOULE IS ALMOST IDENTICAL TO THE PULSE WIDTH VARIATION
EXCEPT (4) A/D CONVERTERS REPLACE THE COUNTERS
DRAWBACKS TO THIS SOLUTION ARE THAT AN ANALOG SIGNAL MUST BE
PASSED BETWEEN THE ENCODER MODULE AND THE CONTROL
THE CONTROL MODULE MUST SIGNAL TO THE FRONT END TO RESET.– THIS
NOTE ON SYNCHRONIZATION OF CHERENKOV PULSE AND LOCAL PRECISION
CLOCK

THE EVENT IS ASYNCHRONOUS RELATIVE TO THE LOCAL CLOCK
THERE MUST BE A METHOD TO HANDLE EVENTS THAT HAPPEN CLOSE TO THE
CLOCK MOMENT TO ALLOW RECOVERY TIME OF THE MEASURING CIRCUITS.
THE PROPOSAL IS TO ALLOW THE EVENT PULSE TO SET A FLIP FLOP IMMEDIATELY
STARTING THE MEASURED INTERVAL.
THIS FLIP FLOP VALUE WILL BE SHIFTED INTO A SECOND FLIP FLOP BY THE
CLOCK. THIS FLIP FLOP WILL ALLOW THE CLEARING OF THE FIRST FLIP FLOP ON
THE NEXT CLOCK ENDING THE MEASURED INTERVAL
THIS MEANS THE MEASURED INTERVAL WILL BE AS MUCH AS 2 CLOCK INTERVALS,
BUT MORE THAN 1.
WE ARE PROPOSING A 1 GHZ CLOCK.
THE MAXIMUM INTERVAL WILL BE 2NS.
WHY USE A SIGE PROCESS?
PUBLISHED PAPERS FROM AN IBM DESIGN GROUP ON USING EARLIER
VERSIONS OF THIS PROCESS (5HP) REPORTING PLL OSCILLATORS
WITH SUB PICO SECOND JITTER (IBM J RES&DEV VOL 47 NO2/3 MARCH/MAY
2003 SiGe BiCMOS INTEGRATED CICUITS FOR HIGH-SPEED SERIAL
•HIGH SPEED
•LOW NOISE
OUR TOOLS, PLANS AND PROBLEMS
TOOLS INCLUDE CADENCE AND MENTOR GRAPHICS
DESIGN TOOLS, IBM DESIGN KIT FOR SiGe PROCESS.
WHAT WE MUST DO. WE NEED 2 DIFFERENT CHIPS
DESIGN CHIPS
SIMULATE DESIGN
DESIGN BOARD
ASSEMBLE A SUITABLE TEST FACILITY: EG SCOPES ETC
DESIGN DATA ACQUISTION FOR TESTING