# Sequential Logic and Circuits

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```					Chapter 5:                                     Sequential Logic and Circuits

A logic network is combinational if its static behavior can be described by a set of Boolean equations,
with each output variable expressed as a function of only the input variables. In this chapter we will review logic
network logic networks that do not satisfy this definition. Such networks are called sequential networks in which
equations and tables used to describe them time is taken into consideration also.

A sequential circuit is a circuit in which decisions are made based on combinations of the current
inputs as well as the past history of inputs.

A Finite state machine circuit is a sequential circuit that has an internal state, and whose outputs are
functions of both the current inputs and its internal state. e.g a vending machine controller, a traffic light
controller, a binary counter modulo , etc.

For the design of sequential circuits, there is a need to use circuit with a memory behavior, in which the outputs
depends upon their previous states and inputs. A basic memory element is called a latch.
Just as gates are fundamental units of combinational logic, elementary memory units called SR latches
(S: set, R: reset) are also for sequential networks. More complex memory elements are called flip-flops. A
sequential network consists of a combinational network and a digital memory made up of flip-flops for storing
the previous states. A flip-flop is a logic device capable of storing one binary digit of information. It may has
one or more inputs. It has two outputs, know as Q and Q'. Its next state, Q(t+d), is a function of the present state
Q(t) and the present input X(t), where τ represents the inherent delay of the device caused by its finite signal
propagation time from input to output. In that case of a synchronous flip-flop, the input-output relationship is
defined in terms of clock pulses that provide synchronization at the expense of operational speed , since the
clock period must be greater than the interval τ of the flip-flop. Therefore, we have the next state Qn+1(tn+1), at
clock pulse tn, as a function of the present state Qn(tn) and the present input Xn(tn) at the clock pulse tn. Another
notation for the successive clock pulses are t – 1 and t (convention used in your second textbook)
Synchronous sequential networks are cyclic, with a period that is determined by a special signal called
the clock. Quantizing times permit to establish a simple model of synchronous sequential networks: The state
Model. An asynchronous sequential networks are self-timed networks that are not driven by a clock signal. RS
Latches are small asynchronous networks.
A D flip-flop (DFF) are small synchronous element, its time-based behavior can be described by the following
equation: out(t) = in(t-1) or Out(tn+1) = In(tn)
In order to study sequential networks its important to consider a logic gate with the effect of delay or
propagation time. An inverter will be considered as followed:

A'(t)
A(t)              U1A       A'(t+d)                     A(t)           U2A                                 A'(t+d)
1           2             Equivalent to              1           2               d

Ideal Inverter     Delay elemnt: d = delay = time of propagation
Real Inverter

The delay notation is useful in defining the basic sequential element. The clock is a sequential circuit for the
generation of a stable reference signal called a square wave. The time interval of a repeating pattern is called the
period T, and its reciprocal is know as the fundamental clock frequency. The signal’s active time, td, divided by
its period is called the duty cycle . The active time interval is called a pulse and is bounded by a leading (rising)
edge and a trailing(falling) edge. These concepts are illustrated in figure 5.1.

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VDD
Vx                      50%                             50%

Gnd
Propagation delay           Propagation delay

VDD
90%         90%
VA                                      50%                                      50%

Gnd                                   10%                              10%

tr                         tf

Figure 5.1. Basic digital timing definitions

A sequential network can be represented by the following block diagram (figure 5.2)

w1                                           z1
Inputs                                                       Outputs
wn              Combinational                zm
w1                 circuit                   z1
Inputs                                                       Outputs
wn              Combinational                zm
circuit

yk                    Yk
yk       dk           Yk
dk
Present-state
Present-state                                             Next-state
Next-state
variables                                               variables
y1                    Y1
y1                    Y1
d1
d1

Figure 5.2. General model of a sequential network.

The delay elements are detailed, with output signals named y1, y2, …………yk and referred to as state
variables, and input signals denotes Y1, Yy2……Yk. The present sate of the network is then given by k-tuple of
state variables (y1, y2, y3…….yk); the next state (Y1, Y2, Y3……….Yk). Some of the output signals, Zis, may be
equivalent to Yis. When we force all delays in a sequential network to be equal ( i.e di = d2 = d3 …….= dk = d)

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and force the input n-tuple and state k-tuple to change at the same time, we operate that network in the
synchronous mode.
The combinational logic network accepts n inputs switching variables (W-vector) and p present state
variables (y-vector) and generates m next state variables (Y-vector) and m output variables (Z-vector). The next
state variables are function of the input variables and the present state variables, or Y=f(W,y). Similarly , the
output variables are function of the input variables and the present state variables, or Z = h(W,y). the
relationship between Yi and yi is defined as Yi(t) = yi(t+d) for asynchronous networks and Yi(n+1) = yi(n+1) for
synchronous networks, where d represents the memory device inherent delay and n the clock interval.

The sequential systems can have up to 2k states, S = (S1, S2, S3, …..S2), it is formally defined as a quintuple
M = (W, Z, S, f, h),
where
 W, Z, and S are finite, nonempty sets of inputs, outputs, and states, respectively.
 f is the state transition function, such that Next state = f(W(t), Present State)
 h is the output function.
Because the number of states of the sequential systems studied in this course is always finite, we called such
systems finite state machines.

1. Sequential Networks
Starting with a sequential network in the form of a logic diagram, it’s possible to write a set of
recursive logic equations by inspection, as in the case of combinational networks. In the case of large networks,
a systematic stimulus-response tabulation results in the state transition table, which lists every possible input and
present state combination and the resulting next state output values. A compact form of this table, the function
table, lists every input variable combination and defines the next state values in terms of 1, 0 or present state Q.
Also the “don’t care” states d are included.

RS Latches and Flip-Flops

There are four basic flip-flops types: the RS, the T, the D and the JK. The RS flip-flop can be either
asynchronous or synchronous. The T, D, and JK flip-flops are basically synchronous. The RS flip-flop can be
converted to synchronous operation by gating its inputs with a clock.
a) Latches
A latch is a binary memory element whose behavior is combinational for some input values. let us consider the
NOR network of figure 5.3 (a). In figure 5.3 (b) we have the logic table, x1 is often labeled S (set) since a 1 on
that input alone forces the latch to its set state. The input x2 is then the R or reset.

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Figure 5.3. NOR network.

Figure 5.4 shows an RS Latch with a control input.

Figure 5.4. SR Latch with a control input
By setting R = S, the undefined stated of an SR latch can be eliminated, in this case we have a D latch as shown
in figure 5.5.

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Figure 5.5. D Latch
The T latch or toggle latch has a single input, T and two output Q and Q’, whose states alternate as T changes
from 0 to 1 (figure 5.6).

Figure 5.6. T Latch
b) Flip-flops
A flip-flop is a synchronous binary element that exhibits on sequential activity. Algebraic and tabular
notation for flip-flops is also identical to that for latches, but where “present” and “next” are separated by gate
delays for latches, the clock period is used: clocked flip-flops.
The clock signal used for flip-lops can be active high or low. But most of the flip-flops use a method of edge-
triggering (transition from 0 to 1 or 1 to 0 ). Figure 5.7 gives an example of a positive edge pulse.

Figure 5.7. Generation of a positive edge pulse.

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The JK flip-flop solves the ambiguity of the RS Latch, when both the R and S inputs are in the 1 or high state.
This flip-flop has tree inputs, the J, the K, and the clock and two complementary outputs, Q and Q’. The
following example provides a detailed analysis for a positive edge, clock transition triggered JK flip-flop.

Figure 5.8. JK flip-flop.
Most clocked FFs have one or more asynchronous inputs which operate independently of the
synchronous inputs and clock input. These inputs can be used to set the flip-flop to 1 or to clear the flip-flop to
zero at any time (figure 5.9).

Figure 5.9. Clocked JK flip-flop with asynchronous inputs
The synchronous D flip-flop is obtained by using a D-Latch as indicated in the following figure:

Figure 5.10. Synchronous D-Latch : Q(t) = D(t-1) or Qn+1 = D

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HDL Specification :

Chip name:     DFF
Inputs:         in
Outputs:       out
Function:      out(t) = in (t-1)
Comment:       This clocked gate has a built-in
implementation and thus there is
no need to implement it

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1.2. Synchronous Sequential Networks

(a)

(b)

Figure 5.11. Synchronous sequential network

The block diagram of figure 5.2 can be modified to represent a synchronous network by replacing all the
memory elements by Flip-flops which are controlled by the same clock signal (figure 11).
All flip-lop changes are assumed to be synchronized by a single clocking signal and change their state following
the same edge of the clock. Activity in the network is cyclic with the clock signal. That activity consists of the
following.
1. Following the synchronizing clock edge:
(a) primary input variables W1, W2…….Wn may change value,
(b) flip-flop output variables y1, y2, ……yk may change value.
But all the changes must take place within a finite, know interval T f, usually T f is the maximum of the flip-flop
propagation delays.
2. Then the new input symbol to the combinational logic, the (n +p)-tuple (W1, W2….Wn, y1, y2…..yk),
propagates through that logic to form the m output Z1, Z2, …..Zm and the flip-flop input signals. All these

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changes must take place within a finite interval ,known as interval T g. Tg is the maximum propagation
delay through the combinational logic block.
3.   Then all the flip-flop input signals must be held at their final values for an interval equal to or greater than
the setup time Tsu for the flip-flops. Only after this interval it is safe to another synchronizing edge to occur.
The clock period T must therefore satisfy T > T f + Tg + Tsu for reliable behavior in the network.

a) The State Model

To analyze synchronous sequential network it’s important to consider the state model. A synchronous sequential
machine (network) with n binary input variable W1, W2……, Wn and m binary output variable Z1, Z2…., Zm
may be considered to consist of (1) ideal combinational logic, and (2) p synchronous flip-flops (FF or memory
element) interconnected as in figure 5.11.
The state of a sequential machine is the k-tuple of memory element states. A machine thus has 2 k states,
although it may not be possible to enter some of them. A very natural name to give a state is y i, where i is the
integer suggested by the binary k-tuple of that state.
y0 = ( 0, 0, ……0) all flip-flops reset
y1= (0, 0, ……..1) first flip-flop set
y2= (0, 0, …..1,0) second flip-flop set
…
ys = (1, 1, ………..1) all flip-flop set (s = 2k).
The set of all machines states, Y, is know as the state alphabet, y = {y0, y1, ….y2p-1}.
Let Xi be an n-tuple of valued variables Xi. Some of 2n possible input symbols of a machine may never be
represented to that machine, and fewer than 2n symbols may appear in the input alphabet, X.
W = {Wi1, Wi2, …..}  {W1, W2, …..W2n-1}.
An output symbol, zi, of a machine is then a m-tuple of valued output variables, zi, and the output alphabet of a
machine is the collection of all symbols that machine is able to generate.
Z = { Zi1, Zi2, …..}  {Z1, Z2, …..Z2m-1}.
The model of figure 5.11 suggests that combinational logic generates a unique output symbol Zi  Z and a next
state Yi  Y for each given input symbol Wj  X and present state yk  y. Thus the combinational logic of this
model defines two Boolean functions: Zi = h(Wj, yk) and Y = f(Wj, yk). That network model considers Z to be an
n + k-input, m-output switching function and is known as the Mealy model. The Moore model add memory
elements to obtained the outputs Z.
A sequential machine is then the 5-tuple (W, y, Z, f, h). Alphabets are conveniently expressed with tables.
Boolean functions f and h can also be expressed in tabular form, or equations, maps, and direct graphs may be
used.

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Inputs: W
Combinational
Combinational
State
circuit                         (Flip-                             circuit
Q

Clock

Figure 5.12. Clocked synchronous state-machine structure (Mealy Machine)

Inputs: W
Combinational
Combinational
State
circuit                          (Flip-                            circuit
Q

Clock

Figure 5.13. Clocked synchronous state-machine structure (Moore Machine)

b) Representation of the state transition and output functions

A state diagram is a directed graph used to represent the transition and output function in a sequential system.
Each state is represented by a node and each transition by an arc. An arc from node S k to node Sj and labelled
x/z specifies that, for a present state Sk and an input x, the next state is Sj and the output is z (figure 5.14).

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x/z

Sj
Sk

State

Figure 5.14. State Diagram (Mealy)

The equivalent Moore state diagram will be:

x

Sj/zj
Sk/zk

State

Figure 5.15 State Diagram (Moore)
A finite state machine can be represented using a state diagram or a state table. Figures 5.16 shows different
modes of representation of a Mealy Machine.

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1/1

0/1
S0                                    S1                                    S2

0/0p

1/0
0/0
1/1

(a) state diagram

Current State S(t)                                        Input x(t)
0               1
S0                                                        S1,1           S2,1
S1                                                        S1,0           S0,1
S2                                                        S1,0           S2,1
S(t+1),z(t)

(b) State Table

Present Sate                            Input             Next State                          Output z
x
A                    B                                   NA                  NB
0                       0: S0       0                  0                 1: S1              1
0                       0: S0       1                  1                 0: S2              1
0                       1: S1       0                  0                 1: S1              0
0                       1: S1       1                  0                 0: S0              1
1                       0: S2       0                  0                 1: S1              0
1                       0: S2       1                  1                 0: S2              1
( c) State transition table
Figure 5.16. Different modes of representations of a finite state machine.
The specification of a sequential system by means of a state description requires that each state is identified by a
state name. In general, these names are arbitrary; no special names have to be used for the description.
Now let consider the sequential circuits given in figure 5.17:

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Figure 5.17. Example of a sequential circuit.

-   The transitions equations
 Excitation equations:
D0 = Q0EN’ + Q0’EN
D1 = Q1EN’ + Q1’Q0EN + Q1Q0’EN
 Characteristics Equations:
Q0* = D0
Q1* = D1
 Substitute excitation equations into characteristic equations
Q0* = Q0EN’ + Q0’EN
Q1* = Q1EN’ + Q1’Q0EN + Q1Q0’EN

-   Transition state

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2.   Sequential Circuits

A typical sequential SSI logic configuration consists of a sixteen-pin DIP package that contains two flip-
flop devices. They may be RS-, D-, or JK-type storage elements, and together with the combinational logic, they
form the basis for sequential network designs. These devices are used as the building blocks for storage
registers, shift registers, and counters (MSI circuits).

a) Registers

An m-bit registers is an ordered set of m flip-flops used to store an m-bit word (zm-1, zm-2, ………..z1, z0).
Each bit of the word is stored in a separated flip-flop. Unless otherwise specified, the data lines of the flip-flops
are assumed to be independent. Data may be transferred to or from all flip-flops simultaneously; this mode of
operation is called parallel input-output. Since the stored information is treated as a single entity, common
control signals (clock, preset, clear) are used for all flip-lops in the register. Figure 5.18 shows a 5-bit register
constructed from D flip-flops.

Figure 5.18. A 5-bit register with parallel input-output
HDL Representation of Parallel Load Register:

There are many situations in computer design where it's useful to be able to shift the contents of a register to the
left or the right. A right-shift operation changes the register states as follows:
(0, zm-1, zm-2, ……..z1)  (zm-1, zm-2, ………..z1, z0), while a left shift performs the
transformation:
(zm-2, ………..z1, z0,0)  (zm-1, zm-2, ………..z1, z0)
A register organized to allow left- or right-shift operations of this kind is called a shift register. Figure 5.19
shows a simple 5-bit shift register using D flip-flops.

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Figure 5.19. A 5-bit shift register

Shift registers are useful design components in a number of applications. These applications include:
- Storage of serial data.
- Serial-t0-parallel and parallel-to-serial data conversion.
- Performing arithmetic operations; left- (right-) shifting and unsigned binary number is equivalent
to multiplication (division) by 2.
Shift operations are included in the instruction sets of most computers. A useful related operation is called
rotation. A left rotation performs the transformation
(zm-2, ………..z1, z0, zm-1)  (zm-1, zm-2, ………..z1, z0)
while a right rotation is defined by
(z0, zm-2, ………..z1)  (zm-1, zm-2, ………..z1, z0)
Rotation is easily implemented by connecting the serial output of a shift register to the corresponding serial
input.
Figure 5.20 presents a block diagram of a universal register (parallel load, shift operations)

Figure 5.20. A 4-bit universal register.

Write the HDL model of the 4-bit Universal Register.

b) Counters

A counter is a simple sequential machine designed to cycle through a predetermined sequence of k distinct
states S0, S1,…..Sk-1 in response to pulses on an input line. The k states usually represent k consecutive numbers;
the state transitions can be thus described by the expression Si+1  Si + 1 (modulo k).
Each input pulse increments the state by 1; the machine can therefore be viewed as counting the input pulses.
Counters come in many different varieties depending on the number codes used, the modulus k, and the timing
mode (synchronous or asynchronous).
The simplest counters can be obtained by minor modifications of an ordinary register or a shift register. Figure
5.21 shows a modulo-16 binary counter composed of four JK flip-flops. This circuit counts the pulses on the
count enable line. Note that the output of each flip-flop may alter the state of its right neighbor, so that the
"carry" signal ripple through the counter from left to right. This type of counter is therefore called ripple counter
(asynchronous) counter or ripple counter

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Figure 5.21. An asynchronous modulo-16 ripple counter

The design of a synchronous counter modulo-8 is pictured in figure 5.22.

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Figure 5.22. Design Process of a modulo-8 synchronous counter.

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HDL Model of a Counter (Figure 5.23)

Figure 5.23. Counter Simulation. At time 23 a reset signal is issued, causing the counter to emit
zero in the following time-unit. The zero persists until an inc signal is issued at time 25, causing
the counter to starts incrementing, one time-unit later. The counting continues until at time 29
the load bit is asserted. Since the counter’s input holds the number 527, the counter is reset to
that value in the next time-unit. Since inc is still asserted, the counter continues incrementing,
until time 33, when inc is de-asserted.

A counter is basically a serial-input parallel-output device. As in the case of shift registers, it can be
useful to have a parallel load capability. Another refinement that is occasionally useful is to permit the counter
to be decremented as well as incremented (Up-Down counter). Counters are also available whose modulus can
be altered by means of modulus-select control lines; such counters are frequently termed programmable. Figure
5.24 shows a block diagram of a programmable counter having all these features.

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Figure 5.24. A programmable up-down counter.

Counters have two major applications in computer design:
1. Storing the state of a control unit, e.g., a program counter. Incrementing the counter provides a
convenient means of generating a sequence of control states.
2. Generating timing signal. Suppose that the count enable input is connected to a source of clock
pulses. Then pulses appear on the output lines of the counter with frequencies which are directly
related to the clock frequency.

c)   RAM (Random Access Memory)

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