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					LAB 2                       Binary and BCD Counters


Objectives:
Upon completion of this laboratory, the student should be able to:
      Enter the design for a binary counter with synchronous load using MAX+ PLUS
       II graphic editor.
      Enter and design a presettable binary and BCD counter in VHDL.
      Simulate, download and test the functions of the various counters.
      Display counter outputs as both binary values on LEDs and numerical on seven-
       segments displays.




Introduction

While binary counters can be designed using any type of flip-flop, JK and D flip-flops are
commonly used for this function. The synchronous input equations of the JK flip-flops of
a binary counter follow a predictable sequence.
                                     J0= K0 =1
                                     J1= K1= Q0
                                     J2= K2 = Q1 Q0
                                     J3= K3 = Q2 Q1 Q0


D flip-flops can also be used for a binary counter. Their synchronous input equations also
follow a predictable sequence.
                                   D0  Q0
                                   D1  Q1  Q0
                                   D2  Q2  Q1Q0
                                   D3  Q3  Q2 Q1Q0


These equations determine the next state of a counter by generating a toggle condition or



                                                                                            1
a no change condition for each flip-flop throughout the count sequence.
Typically, designing a counter with JK flip-flops yields simple equations, but requires
more work than D flip-flops, since the synchronous input of a D flip-flop is the same as
its required next state, whereas the inputs of a JK flip-flop must be derived from an
excitation table.
The logic diagram of a 3-bit binary counter based on D flip-flops is shown in the figure
below (figure 1). Figure 2 shows counter wave form.



                            XOR                DFF
         AND2
                                                       PRN        OUTPUT
                                                   D          Q   7        Q2
                            4
         5

                                                       CLRN
                                               1




                            XOR                DFF
                                                       PRN        OUTPUT
                                                   D          Q   10       Q1
                            9


                                                       CLRN
                                               2




                                               DFF
                            NOT
                                                       PRN        OUTPUT
                                                   D          Q   11       Q0
                            6


                                                       CLRN
                                               3




                          INPUT
             12   CLOCK    VCC


                          INPUT
             13   RESET    VCC




                                  Figure 1 3-bit binary counter




                                                                                           2
                           Figure 2 Simulation of a 3-bit counter




                                     Figure 2 wave form

The 3-bit counter can be modified as shown in Figure 3 to include a synchronous load
function. Each flip-flop is fed by an AND-OR network (essentially a 2-to-1 multiplexer)
that directs either the count logic or a parallel input to the synchronous input of the flip-
flop.


A simulation of this counter is shown in Figure 4.We can see that the load function is
really synchronous because the first load pulse does not overlap or immediately precede a
positive clock edge and is therefore ignored.




                                                                                                3
Figure 3 3-bit binary counter with synchronous load


                                                      4
               Figure 4 simulation of a 3-bit counter with synchronous load




A 2-digit BCD counter advances in decimal from 00 to 99 (0000 0000 to 1001 1001 in
binary) and then rolls over to 00. Values representing HEX numbers from A to F are not
valid in this code.


For a 2-digit BCD (Binary Coded Decimal) counter, we use an 8-bit output, but divide
the range into two groups of four bits: one group for the one’s digit and one group for the
ten’s digit. This type of counter can be implemented in a similar way to the
behaviourally-designed binary counter, but requires a more complex algorithm for
increasing the count. Rather than simply incrementing a simple count variable with a
range of 0 to 255, we must have two variables, each with a range of 0 to 9. When the
one’s digit is at 9, it must be set to 0 on the next count and the ten’s digit incremented. If
both digits are at 9, both must be set to 0 on the next count. After each clock pulse, the
two BCD variables are assigned to output pins, where they can be displayed directly as
binary numbers or decode to display a numerical output.




                                                                                                 5
Laboratory


Part I


   1. Use the MAX+PLUS II graphic editor to enter the presettable 3-bit counter shown
          in Figure 3.
   2. Save the file as 3bit_dct_s1.gdf.
   3. Set the project to the current file.
   4. Compile the file and create a simulation to verify its operation.
   5. Show the results to your TA.


Part II

   1. Create a default symbol for the 3-bit presettable counter.
   2. In order to manually clock the counter with a pushbutton switch, we require a
          switch debouncer, which is provide in the appendix. Copy the code and save the
          file as debounce.vhd to your working folder, open the file and set the project to
          the current file. Then create a default symbol for the debouncer.
   3. Create a test circuit for the counter, as shown in Figure 5.
   4. Assign the target device and pin assignments according to Table 1. Disable
          unused LEDs by setting them HIGH.
   5. Save the file as 3bit_load_a.gdf and set the project to current file.




                                                                                              6
          Figure 5 3-bit counter test circuit




           Pin Names           Pin Number
             LOAD                   41
               P2                   34
               P1                   33
               P0                   36
              CLK                   83
             PB_IN                  11
            RESET                    1
               Q2                   80
               Q1                   81
               Q0                    4
Table 1 Pin assignments for 3-bit counter test circuit




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6. The CLK input to the debouncer is the system clock from the on-board oscillator
   (25.175 MHz). PB_IN is an input from the on-board pushbutton. PB_OUT is a
   debounced output used as the clock for the counter.
7. Note that the counter in Figure 5 has inverted outputs, so that it will drive the
   LEDs on the Altera UP-2 board causing a HIGH counter output to turn an
   indicator LED on. The counter symbol outputs can be inverted by using the Edit
   Ports/Parameters function of the MAX+PLUS II graphic editor. Right click on the
   counter symbol and select Edit Ports/Parameters.
8. Select Q0 from the Name box and click ALL in the Inversion Box. Select Q1 and
   invert it. Select and invert Q2. Then click OK.
9. Compile the file and download it to the CPLD board.
10. Test the counter by setting the LOAD input LOW and pressing the CLK
   pushbutton several times.
11. Set the LOAD input HIGH, set the P[2..0] inputs to 101, and press the CLK
   pushbutton.
12. Set the LOAD LOW and the clock a few times. Press the RESET pushbutton to
   clear the counter outputs.
13. Show the operation of the circuit to your TA.




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