A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa Department of Physical Electronics Tokyo Institute of Technology 2-12-1, O-okayama, Meguroku, Tokyo, 152-8552, Japan firstname.lastname@example.org Abstract - This paper presents a low offset voltage, low noise ciently low noise comparator to prevent conversion errors . dynamic latched comparator using a self-calibrating technique. In this paper, a dynamic latch type low noise comparator The new calibration technique does not require any amplifiers using self-calibrating technique is proposed. The proposed for the offset voltage cancellation and quiescent current. It offset calibration technique does not require quiescent DC achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. current for offset cancellation owing to use of a charge pump Furthermore the proposed comparator requires only one phase circuit instead of a pre-amplifier. Thus, the proposed offset clock while conventionally two phase clocks were required lead- cancellation achieves not only low offset voltage but also low ing to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 power consumption. Moreover, the proposed circuit topology sigma, three times lower than the conventional one, is obtained. can improve the comparator noise and reduce the clock driv- Prototype comparators are realized in 90 nm 10M1P CMOS ing requirement compared with a conventional comparator. technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 µW/GHz ( 20 fJ/conv. ) from a 1.0 V supply. II. CIRCUIT DESIGN A. Self-Calibrating Technique I. INTRODUCTION The calibration architecture for the offset voltage cancella- A high-speed, low-offset, low-power consumption com- tion of the comparator is shown Fig. 1. The proposed archi- parator is very attractive for many applications, such as mem- tecture consists of a comparator, offset compensation current ory sensing circuits, analog to digital converters and data re- sources (MC1, MC2) and a charge pump. During the calibra- ceivers. While the technology scaling of MOS transistors en- tion mode, all input nodes of the comparator are switched ables high-speed and low-power operation, the offset voltage of the comparator is increased due to the transistor mismatch. from the signal inputs to the common-mode voltage Vcm. In conventional designs, pre-amplifiers are used to reduce Vcm offset voltage . However, these techniques require high CAL voltage gain to reduce the offset voltage and loosing effec- CMPout+ Vin+ In+ tiveness with the reduction of the drain resistance due to the CAL CAL Vin- CMPout- technology scaling. Moreover, large power consumption of CAL In- the amplifier is inevitable for realizing a wide bandwidth am- CAL Icp plifier. On the other hand, a dynamic comparator which has Vcm MC1 MC2 Vc the offset compensation function was proposed . In this Vb method the same input signal of each comparator as the ref- CH CAL erence voltage is given in flash type ADC, and the load ca- Icp pacitances of the output node of each comparator are con- trolled digitally so that the output of the comparator may Vc reach the ideal value. However, the calibration time greatly increases if the resolution of the ADC is increased. Moreover, the speed of the comparator is slowed down due to the in- Voffset ' crease of added capacitances. Additionally, the considerably large size circuits to control the calibration are necessary for 1 each comparator. Therefore this topology is improper for the CMPout design of high resolution flash type ADCs. 0 Moreover, a comparator noise determines the signal to CLK noise ratio of ADCs. This is especially true for a high resolu- tion successive approximation ADC which requires a suffi- Fig. 1. Proposed calibration architecture for offset cancellation. 2nd stage VDD VDD VDD CLK M12' M14 M15 Xi+ Xi- M13 M12 M10' M11' M10 M11 CMPout- CMPout+ CMPout- CMPout+ M8' M6' M7' M9' M8 M6 M7 M9 Di+ Di- Di+ Di- VDD VDD VDD VDD CLK M3 M4 CLK M3 M4 ICP CMPout- MC1 M1 M2 MC2 M1 M2 CAL Vin- Vin+ CMPout+ Vb CAL CLK CLK M5 CH M5 Charge pump ICP + Compensation current source 1st stage (a) Conventional comparator (b) Proposed self-calibrating comparator Fig. 2. Circuit Implementation. CMPout+ 1.0 CMPout [V] 2nd stage CMPout- -0.1 Transistors MC1 and MC2 used to generate the compensation td td:50-100ps current are connected to the internal output node of the com- 1.0 1st stage Di [V] Di+ Proposed comparator uses the parator. The gate of MC1 is connected to Vb to set the common Di- Di nodes voltage instead of CLK for 2nd stage latch timing. mode voltage of the charge pump. -0.1 The gate of MC2 is connected to the capacitor CH which is 1.0 pre-charged to Vb in the initial condition. If the comparator CLK CLK CLK [V] (1st stage latch trigger) (2nd stage latch trigger) has the offset voltage Voffset (Voffset is positive value in this case) the comparator outputs high, and pulls out the charge of CH according to the current Icp, along with the control voltage 0.0 1.8n 2.1n 2.4n 2.7n 3.1n of the current source Vc falls, causing the offset voltage of the Time [s] comparator approaches zero. When Vc exceeds Voffset’ corre- Fig. 3. Signal behavior of the conventional and proposed comparators. sponding to the offset of the comparator being adjusted to zero, comparator outputs high and low alternately as shown in B. Circuit Implementation Fig. 1. During the conversion mode, CH keeps the offset value. The conventional comparator and our proposed circuit are Thus, the offset voltage is canceled in conversion mode. shown in Fig. 2. The signal behavior of these comparators is The comparator offset voltage becomes less than ±1 LSB shown in Fig. 3. ( = Ts × Icp / CH ) due to the charge pump if the comparator The proposed circuit consists of a comparator based on a has no hysteresis characteristics or noise. A wide compensa- double latch type comparator  (M1-15), compensation cur- tion range can be realized by changing Icp. The proposed cali- rent source (MC1-2) and charge pump circuit. bration technique does not require a reference voltage for the During the reset phase (CLK = 0), M3 and M4 pre-charge calibration. Because each comparator can calibrate for the the Di nodes to supply voltage VDD. This result in, M8 (M8’) offset simultaneously, the calibration time can be remarkably and M9 (M9’) discharging the output nodes to ground. After shortened in a system that needs a lot of comparators, such as reset phase, CLK turns to VDD, M3 and M4 turn off and M5 flash type ADCs. The circuit can be made simple and the die turns on. At the Di nodes, the common-mode voltage drops area also can be reduced because the input of the calibration with a rate determined by IM5 / CDi (CDi is the load capacitance data word from outside of the comparators is not required. In of the 1st stage) and an input dependent differential voltage practice, offset voltage cancellation is limited by sensitivity of ∆VDi will build up in a short time. The conventional compara- the comparator. Therefore a low noise comparator is needed tor requires high accuracy timing CLK because the second for achieving low offset voltage in the proposed architecture. latch stage has to detect ∆VDi at very short time td. 100 4.5 90 4.0 80 3.5 70 Conventional P (out=high) [%]_ 3.0 Proposed ∆Vin (σ ) [mV] 60 ∆V in (σ ) = 0.66mV 2.5 50 Conventional 2.0 40 Proposed ∆V in (σ ) = 2.1mV 1.5 30 20 1.0 10 0.5 0 0.0 -4.0 -2.0 0.0 2.0 4.0 0.4 0.5 0.6 0.7 0.8 0.9 ∆V in - V offset [mV] V cm [mV] Fig. 4. Simulated cumulative noise distribution. Fig. 5. Simulated equivalent input noise ∆Vin(σ) obtained from cumulative noise distribution vs. common mode input voltage. The proposed comparator uses the falling edge at the Di 40 nodes for the latch timing of the second stage. M14 and M15 Proposed comparator are used instead of M12’ and these gates are connected to the with calibration Di nodes. M14 and M15 behave not only pre-charge switches 36 but also input transistors of the second latch stage. Therefore, Probability [%] the comparator sensitivity is improved by increasing the gain of the second latch stage. Moreover, the clock driving re- 32 quirements are relaxed because the proposed comparator re- quires only a one phase clock. M12 and M13 are used to reset Proposed comparator 8 without calibration the Xi nodes to avoid mismatch voltage between Xi nodes that Conventional causes comparator offset. comparator Fig. 4 shows the simulation results of the comparator noise 4 obtained with Spectre transient noise simulation. The operat- ing conditions are VDD = 1.0 V, clock frequency fCLK = 4 GHz and the common-mode voltage of the comparator input Vcm = 0 -80 -60 -40 -20 0 20 40 60 80 0.6 V. Same size transistors are used in the conventional and Voffset [mV] the proposed comparator. The offset cancellation was disabled Fig.6. Simulated distribution of the input offset voltage Voffset. in this simulation. Fitting the simulation results to a Gaussian cumulative distribution gives the RMS equivalent input noise TABLE I ∆Vin(σ). ∆Vin(σ) in the proposed comparator equals 0.66 mV SIMULATED INPUT OFFSET VOLTAGE and while conventional one equals 2.1 mV. The simulation Simulation condition Voffset (σ ) result shows the noise of the proposed comparator is about 3 Conventional comparator 21.5 mV times lower than the conventional one. Fig. 5 shows the simu- Proposed comparator without calibration 13.5 mV lated equivalent input noise ∆Vin(σ) obtained from cumulative Proposed comparator with calibration 1.3 mV noise distribution versus common mode input voltage Vcm. ∆Vin(σ) of the proposed circuit increases by only 1.0 mV when Vcm changes from 0.5 V to 0.8 V, in contrast to the 2.8 mV enabled. increase for the conventional comparator. The offset voltage obtained from simulation is shown in Fig. III. MEASUREMENT RESULTS A prototype comparator has been realized in a 90 nm 6 and Table I. The simulation result of the proposed compara- 10M1P CMOS technology with a chip area of 0.0348 mm2 as tor on 100 samples gave an offset voltage distribution of shown in Fig. 7. The chip area includes 64 comparators with Voffset(σ) = 13.5 mV versus 21.5 mV in the conventional com- SR latches to create a static output. parator when calibration technique is not used. The offset The offset voltage of the comparator with and without cali- voltage is improved by increasing the trans-conductance of bration is shown in Fig. 8. The offset voltage is measured on the input transistors in the second stage. The offset voltage 64 samples, VDD = 1.0 V and fCLK = 250 MHz. The offset cali- distribution can be improved to 1.3 mV, when calibration is bration had been executed before the offset voltage 0.29 mm 0.9 f CLK = 600 MHz 0.8 0.12 mm 64 comparators with SR Latch Vin (σ ) [mV] 0.7 0.6 f CLK = 200 MHz Fig. 7. Layout of the proposed comparator. Calibration ON 0.5 Calibration OFF 40 Min/Max : -3.9/+2.9 mV 0.4 30 0.3 0.4 0.5 0.6 0.7 0.8 0.9 20 Voffset (σ ) = 1.69 mV V cm [V] 10 V offset [mV] 0 Fig. 9. Measured equivalent input noise ∆Vin(σ) vs. common mode input voltage Vcm. -10 -20 Voffset (σ ) = 13.7 mV IV. CONCLUSION -30 Min/Max : -38.4/+32.8 mV A low-offset, low-noise dynamic latched comparator using -40 a self-calibrating architecture that does not require a pream- 0 16 32 48 64 0 10 20 30 Comparator Number Probability [%] plifier and a DAC is proposed. Measured results show the (a) Offset voltage (b) Distribution RMS input offset voltage is dramatically improved from 13.7 Fig. 8. Measured offset voltage of the comparator with and without calibra- mV to 1.69 mV by using proposed calibration technique. The tion. comparator noise is only 0.6 mV in case of Vcm = 0.5 and fCLK = 200 MHz and 0.7 mV in case of Vcm = 0.5 and fCLK = 600 measurement. MHz. This value is three times lower than that of the conven- Measurement results show that the offset voltage is dra- tional one. matically improved from 13.7 mV to 1.69mV by using the The proposed comparator can compare 1.0 mV input volt- proposed calibration architecture. age at 1 GHz with a low power consumption of 40 µW/GHz Fig. 9 shows the measured input noise ∆Vin(σ) versus com- ( 20 fJ/conv. ). The proposed calibration technique and com- mon mode input voltage. The input noise is measured on VDD parator topology are very effective for achieving a small area = 1.0 V and Vb = 0 V. The offset cancellation is disabled in and low offset voltage comparator using a deep sub-micron this measurement. Measurement results show that the com- CMOS technology. parator noise is decreased by the decrease of Vcm. ∆Vin(σ) in- ACKNOWLEDGEMENT creases by only 0.16 mV when fCLK is changed from 200 MHz This work was partially supported by MIC and VDEC in to 600 MHz. collaboration with Cadence Design Systems, Inc. The delay time of the comparator (the time is defined by the time between the clock edge and the instant when CMPout REFERENCES crosses 70 % of VDD) obtained from the simulation is 122 ps  B. Razavi, “ Principle of data conversion system design,” IEEE PRESS  G. Van der Plas, S. Decoutere, and S. Donnay, “A 0.19pJ/Conversion-step at 1mV input voltage difference and delay / log(∆Vin) is equal 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process,” ISSCC to -24.3 ps/dec. The simulated power consumption of pro- Dig. of Tech. Papers, pp.566-567, Feb., 2006.  V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas and J. posed comparator is 40 µW, the FoM amounts to 20 fJ/conv. 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