RTL test generation based on FSMs

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					                        Efficient RT-level Test Generation Techniques based on

                                      Refinement of Finite-state Machines *

                                          Huawei Li              Yinghua Min
                                     lihuawei@ict.ac.cn          min@ict.ac.cn
                          Institute of Computing Technology, Chinese Academy of Sciences,
                                        P.O.Box 2704, Beijing 100080, P.R.China

                            Abstract                             the difficulties in RT-level test generation is the lack of
                                                                  appropriate medium to bridge RT-level to low level. To
   This paper presents detailed techniques of RTL test            fill up the gap between a behavioral description and a state
generation based on refinement of finite-state machines           description of an FSM, a new level of description is
(FSMs), as a supplement of [1]. First, an approach to             introduced in [8], which is termed behavioral phase
clustering of behavioral phases is presented so as to             description. The number of behavioral phases can be
represent the function of an FSM more explicitly and              much smaller than that of states. Clustering of behavioral
refinedly, based on the rule given in [1]. Then, the test         phases can be performed to refine the corresponding FSM.
generation algorithm is shown in detail by taking the             A new RTL fault model, termed behavioral phase
advantage of characteristics of clusters.             These       transition fault, is introduced in [1]. The paper shows
techniques are integrated into a program, called ATCLUB.          that an RTL ATPG using the behavioral phase transition
Experimental results show that ATCLUB can gain high               fault model can be very efficient based on a refined
fault coverage, while random test generation results in 6%        description of a given behavioral description, and it can
fault coverage loss with the same length of test sequence.        get short test sequence with considerable fault coverage at
                                                                  gate-level. However, due to the limited space, the paper
Keywords: RT-level, test generation,                 behavioral   doesn‟t explain how to refine a behavioral description and
description, finite-state machine                                 how the ATPG works.
                                                                      As a supplement of [1], this paper focuses on detailed
                                                                  techniques that are not included in [1], including an
1.      Introduction                                              approach to clustering of behavioral phases and an
                                                                  algorithm of RT-level ATPG. Experimental results are
   With increasing complexity, modern designs need be             also given to show that the proposed RTL ATPG gains 6%
described at a higher level of abstraction. Thus, gate            higher fault coverage than random test generation with the
level implementation of a design is not an appropriate            same length of test sequence.
medium for early design verification and early estimation             The paper is organized as follows.            Section 2
of fault coverage of physical defects. Instead, as RT-level       introduces the concepts of behavioral phase and clustering
descriptions stabilize much earlier in the design cycle,          of behavioral phases. Section 3 presents the approach to
RT-level test generation [2-7] can be a good solution to          clustering of behavioral phases in behavioral descriptions
meet these expectations.                                          to obtain a refined and explicit functional representation of
   Since the correspondence of an RT-level behavioral             a given FSM. Section 4 describes the efficient RT-level
description to a gate level description is not unique, one of     test generation algorithm.            Section 5 presents
                                                                  experimental results for ITC‟99 Benchmarks. Finally
                                                                 conclusions are given.
    * This work is supported by NSFC under the grant 69733010.
                                                                   2.2 Behavioral phase transition and clustering of
2.     Concepts                                                        behavioral phases

2.1 Phase variable and behavioral phase                               A transition from one behavioral phase to another is
                                                                   termed behavioral phase transition. Just like state
   In most of RTL behavioral descriptions, all the state           transitions in an FSM, behavioral phase transitions occur
registers of an FSM are associated with only one variable.         under certain conditions, which can be revealed using a
And the FSM is usually a synchronous design with                   transition diagram.     The behavioral phase transition
edge-triggered flip-flops.      To simplify analysis, we           diagram for B01 circuit of Figure 1 is shown in Figure 2.
assume that only one FSM constitutes the controller of a           Each node in the diagram represents a behavioral phase of
given design. Thus, there is a variable defined in the             the circuit. Arrows connecting the nodes are used to
behavioral description that is critical to the control flow of     indicate behavioral phase transitions that occur under
a design. This variable is termed phase variable. A                certain input conditions. Input values corresponding to
value of a phase variable corresponds to a series of states,       transitions are implied in the type of arrows, which are
which is termed behavioral phase. A formal definition of           shown in the legend of the diagram.
phase variable is given in [8], which can help to identify a          A behavioral phase transition diagram is convenient for
phase variable from a behavioral description                       visualizing the function of a design.         Clusters of
automatically.                                                     behavioral phases can be obtained from a behavioral phase
   Let‟s consider the example of B01‟s behavioral                  transition diagram in order to reveal functional modes of
description as shown in Figure 1. B01 is an FSM that               an FSM. Clusters of behavioral phases of B01 are shown
compares serial flows. Obviously, the variable stato is            in dotted ellipse in Figure 2.        The conditions of
critical to the control flow of the design. According to           behavioral phase transitions inside a cluster are same.
the definition in [8], stato will be identified as a phase         The clusters reveal that B01 is simply a four-bit serial
variable. And the eight values that stato may take are             adder [1], or an FSM that compares serial flows as well.
behavioral phases of B01.                                          The 3 clusters correspond to 3 functional modes of the
                                                                   circuit: addition without carry mode, addition with carry
     entity B01 is                                                 mode, and overflow mode. Thus, the transition diagram
     port( line1:in bit; line2:in bit; reset:in bit;               with clusters is a refinement of B01‟s behavioral
        outp:out bit; overflw:out bit; clock:in bit );
     end B01;
     architecture BEHAV of B01 is                                                               x
            constant a:integer:=0; … …                                                reset
      variable stato: integer range 7 downto 0;                                a                                 f
        if reset='1' then stato:=a; … …
        elsif clock'event and clock='1' then                                             b                                 g
                                                                      wf0                               e
        case stato is
           when a => if line1='1' and line2='1'
                          then stato:=f; else stato:=b ; end if;                c                                    wf1
                          outp <= line1 xor line2;
                          overflw <= „0‟;
            when e => … … ;
             when b => … … ;         when f => … … ;
             when c => … … ;         when g => … … ;                     (line1,line2)=(1,1)        (line1,line2)=(0,0)
             when wf0 =>… … ; when wf1 =>… … ;
          end case;                                                      (line1,line2)=~(1,1)       (line1,line2)=~(0,0)
        end if;
      end process;
     end BEHAV;                                                        Figure 2.  The behavioral phase transition
                                                                                 diagram for B01 circuit of Figure 1
                Figure 1. The VHDL code of B01                           (Dotted ellipse: clusters of behavioral phases)
description, which can simplify and accelerate test                    Step 2. Decision about mutual exclusions.
generation process.                                                    For each behavioral phase vx, if there exist two
   In the next section, an approach to clustering of                transitions tm1 (vx vy1) and tm2 (vx vy2), both starting
behavioral phases is introduced to refine the FSM                   from vx, and sm1  sm2 = , then, we say that the two
represented by a behavioral phase transition diagram.               behavioral phases vy1 and vy2 are directly mutually
                                                                    exclusive. If two behavioral phases are directly mutually
                                                                    exclusive, they will not be put into one cluster in the later
3. An approach to clustering of behavioral                          steps.
phases                                                                 For any two clusters pz1 and pz2 in P, if there exist two
                                                                    behavioral phases vy1 and vy2 that are directly mutually
    The rule of clustering [1] is to guarantee that conditions      exclusive, where vy1  pz1 and vy2  pz2, then, we say that
of all behavioral phase transitions inside a cluster are same.      the two clusters pz1 and pz2 are mutually exclusive. Any
In other words, if input signals remain some steady values,         two clusters that are mutually exclusive will not be merged
the current behavioral phase of a circuit will change inside        together in the later steps.
a cluster. To do this, let‟s first give some definitions               Note that if two clusters pz1 and pz2 are mutually
about conditions of behavioral phase transitions.                   exclusive, then, for any two behavioral phases vx1 and vx2 ,
    Definition 1: The satiable set of a transition t.               where vx1  pz1 and vx2  pz2, vx1 and vx2 are either directly
Suppose the set of primary inputs of a given behavioral             mutually exclusive, or indirectly mutually exclusive.
description B is: I = {i1, i2, … , in }. Thus, all the possible     And if two behavioral phases are either directly mutually
values of the vector (i1, i2, … , in ) constitute an input space    exclusive or indirectly mutually exclusive, they will not be
I . Then, the condition of a behavioral phase transition           put into one cluster in the later steps.
tj can be represented as a function ftj (i1, i2, … , in ). The         Step 3. Merger Operation.
satiable set of transition ti is defined as a set sj, while sj =       For any two behavioral phases vx1 and vx2 , where vx1 
{x | ftj (x) = 1, x  I }.                                         pz11, vx2  pz21 and pz11 pz21, if there exist two transitions
    Definition 2: The out-satiable set of a cluster. A              tm1 (vx1 vy1) and tm2 (vx2 vy2), where sm1 = sm2, and the
group of behavioral phases is called a cluster. If for each         following two conditions are also satisfied,
behavioral phase vij (1  j  |bi| , where |bi| is the size of         1) pz11 and pz21 are not mutually exclusive.
cluster bi ) inside a cluster bi, there exists a transition tij        2) The out-satiable set sm1 (= sm2) can be the mutual
start from vij and end at a behavioral phase vjk that is not in               out-satiable set of pz11 and pz21. In other words,
cluster bi, and all the transitions tij ( j = 1, 2, … ,|bi|) have             for each behavioral phase vij either in pz11 or in pz21,
the same satiable set si. Then, si is defined as the                          there exists a transition tij start from vij and end at
out-satiable set of the cluster. Otherwise, the out-satiable                  a behavioral phase vjk that is not in cluster pz11 and
set of the cluster is .                                                      pz21, and sij = sm1 = sm2.
    Suppose all the behavioral phases in a given behavioral            Then, the two clusters, pz11 and pz21, are merged into
description constitute a behavioral phase set V, where V =          one cluster pz1. The out-satiable set of pz1 is sm1 (= sm2).
{ v1, v2, … , vr }. And suppose all the behavioral phase               Merger and decision about mutual exclusions are
transitions constitute a set T, where T = { t1, t2, … , tk }.       alternatively done till no Merger can be performed any
The corresponding satiable sets of all the transitions in T         more. The partition P finally obtained has the minimum
constitute a set { s1, s2, … , sk }, while si may equal to sj (1    number of clusters. It can be proved that conditions of all
 i  j  k ). Clustering of behavioral phases can be               behavioral phase transitions inside a cluster of P are same
obtained as a partition P of the set V, according to the            if number of transitions that start from any behavioral
following steps.                                                    phase is no more than two. Hopefully, this will also be
    Step 1. Initialize P as r clusters p1, p2, … , pr, each         tenable in most cases when number of transitions that start
cluster includes only one behavioral phase. For each                from a behavioral phase is more than two.
cluster pi, its out-satiable set can be an arbitrary one. In
other words, any two clusters may have the same
out-satiable set. Any two clusters that have the same               4. Algorithm of RT-level test generation
out-satiable set will have the opportunity to be merged into
one cluster in the later steps.                                        A behavioral phase transition diagram with clustering
of behavioral phases is a refined representation of an FSM.
It represents the function of an FSM more explicitly than a                    ①
behavioral description, and the number of behavioral                       ②
phases is generally much less than the number of states in                               ④                     …
the FSM. It is shown in [8] that a behavioral phase                                                   ⑤-②
transition diagram can be extracted from a behavioral
description efficiently. Thus, test generation can be                   Figure 3. The process of     CTG Algorithm
performed based on a behavioral phase transition diagram
instead of a behavioral description.                                     the test generation process is over. Else, generate
    We consider single behavioral phase transition fault [1]             randomly a new test sequence with a certain vector
during test generation. To activate a behavioral phase                   count (comparable to vector count of TS). The new
transition fault a       b in a given circuit, an initial input          test sequence is linked behind TS on purpose to
sequence is needed to make the current behavioral phase                  propagate the error to primary outputs.
of the circuit to be a. Then, a test vector should be                 7) Save the current test sequence. If there exists a
generated to satisfy the condition of the behavioral phase               behavioral phase transition fault that has not been
transition ab.                                                          activated, goto 1) to find another test sequence in
    Deterministic test pattern generation based on the                   order to activate it. Else, the test generation process
behavioral phase transition fault model is difficult since an            is over.
initial sequence to activate each fault should be found first.        The first 5 steps move in circles during test generation,
However, given a behavioral phase transition diagram, a            which is shown in Figure 3. Circles in Figure 3 represent
test sequence to cover each fault in some order can be             clusters of behavioral phases. Nodes in a circle represent
efficiently found based on clustering of behavioral phases.        behavioral phases in a cluster. Arrows connecting nodes
    Remember that all the conditions of behavioral phase           represent behavioral phase transition faults activated by
transitions inside a cluster are the same. The algorithm           each step of CTG Algorithm, while the label on an edge
for test pattern generation based on clustering of                 corresponds to Step-No. in CTG Algorithm. The edge
behavioral phases, named CTG Algorithm, is shown                   labeled „⑤-②‟ indicates the point when the steps in CTG
below.                                                             Algorithm begin to loop, which is caused because the
    1) Generate a test vector as an initial vector of a test       current behavioral phase enters into a new cluster in Step 5
       sequence to reset the circuit under test.                   and the test generation process returns to Step 2.
    2) Suppose the current behavioral phase of the circuit is         To simplify test generation process, the observability of
       a, and a is in cluster X. If there is a behavioral          behavioral phase transition faults is not considered in CTG
       phase transition fault in X that has not been activated,    Algorithm. Instead, a sequence of input vectors in a
       try to generate a test vector to satisfy the condition of   certain length is linked behind each generated test
       the transitions in cluster X. Else, goto 4).                sequence in expectation that errors will be propagated to
    3) If the condition of the transitions in cluster X is         some primary output during efficient clock cycles (in Step
       satisfied, the current behavioral phase will remain in      6 of CTG Algorithm)
       cluster X. Maintain the input values steady, until the         In CTG Algorithm, to activate the behavioral phase
       generated test sequence can not activate any new            transition faults inside a cluster, only one test vector is
       behavioral phase transition fault in cluster X.             truly generated, while the others are the same. Thus, the
    4) Suppose the current behavioral phase in cluster X is c,     test generation process is efficient.
       try to generate a test vector to activate a behavioral
       phase transition fault c       d, while d is in another
       cluster Y, and there exists a behavioral phase              5. Experimental results
       transition fault in Y that has not been activated.
    5) If such a test vector as described in 4) is generated,          An RT-level ATPG system based on refinement of
       then goto 2). Else, goto 6).                                FSMs, called ATCLUB, is developed to generate test
    6) A test sequence TS is obtained. If TS does not              patterns for behavioral phase transition fault model. The
       activate a new behavioral phase transition fault that is    first 11 ITC‟99 benchmark circuits at VHDL RT-level are
       not activated by the prior generated test sequences,        taken as examples to show the efficiency of ATCLUB.
Experimental results are obtained on a 600 MHz Pentium
III with 64 MB of RAM. The CPU time spent on                   6. Conclusions
refinement of a given FSM, including extracting a
behavioral phase transition diagram and clustering of             As a supplement of [1], this paper introduces an
behavioral phases, is less than 0.001 second, thus             approach to clustering of behavioral phases and an
neglectable. The CPU time spent on test generation             algorithm of RT-level test generation based on refinement
based on clustering of behavioral phases is generally less     of FSMs. These techniques are integrated into an
than 0.001 second, and the longest CPU time is no more         RT-level ATPG, called ATCLUB. The most significant
than 0.05 second.                                              improvement of ATCLUB is that compared to gate-level
    Compared to a commercial gate-level ATPG [5] and           test generation scheme, it reduces test generation time by 6
two RT-level ATPG: ARTIST [5] and X-Pulling [7],               orders of magnitude [1]. This paper also shows that
ATCLUB shows a sharp decrease of 76%, 91%, 62% in              ATCLUB can gain high fault coverage, while random test
terms of vector count, at the penalty of a slightly decrease   generation results in 6% fault coverage loss with the same
of 4.9%, 2.9%, 3.9% in terms of gate-level stuck-at fault      length of test sequence.
coverage respectively [1]. The significant improvement
is that CPU time spent by ATCLUB is much shorter than
that by the other ATPGs [1]. The average CPU time is           References
above 12,000 seconds for the gate-level ATPG, above            [1] Huawei Li, Yinghua Min, and Zhongcheng Li, “An RT-level
7,000 seconds for ARTIST, and about 0.7 second for                 ATPG Based on Clustering of Circuit States,” Proc. of IEEE
X-Pulling. While the average CPU time spent by                     ATS-2001, Japan, Nov. 2001.
ATCLUB is less than 0.01 second.                               [2] S. Bhatia and N.K. Jha, “Genesis: A behavioral synthesis
                                                                   system for hierarchical testability,” Proc. of European
   Table 1. Fault coverage comparison with the same                Design and Test Conf., Paris, France, February 1994, pp.
                      vector counts                                272-276.
                                                               [3] I. Ghosh, A. Raghunathan, N. K. Jha, “A DFT Technique for
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                   FC(%)         FC(%)                             Trans. on Computer-Aided Design of Integrated Circuits and
      B01           97.29         98.06         30                 Systems, 1998, Vol. 17, no. 8, pp. 706-723.
      B02           99.33         99.33         24             [4] Yiorgos Makris, Jamison Collins, and Alex Orailoglu, “Fast
      B05           33.25         33.21         70                 Hierarchical Test Path Construction for DFT-Free
      B06           90.73         97.02         24                 Controller-Datapath Circuits,” Proc. of Asian Test Symp.,
      B07           58.11         57.70         90                 Taiwan, December 2000, pp. 185-190.
      B08           74.51         85.73        150             [5] F. Corno, M. Sonza Reorda, G. Squillero, “RT-level ITC‟99
                                                                   benchmarks and first ATPG results,” IEEE Design & Test of
      B09           50.67         70.11        139
                                                                   Computers, July-Sept. 2000, pp. 44-53.
      B10           72.20         85.20         75
                                                               [6] F. Corno, M. Sonza Reorda, G. Squillero, “High-Level
      B11           77.75         78.52         90
                                                                   Observability for Effective High-Level ATPG,” 18th IEEE
      Average       72.65         78.32         77
                                                                   VLSI Test Symposium, Montreal, Canada, 2000, pp.
   Table 1 demonstrates comparison of fault coverage (FC)
                                                               [7] Zhigang Yin, Yinghua Min, Xiaowei Li, “An Approach to
with the same vector counts (#vectors) between ATCLUB
                                                                   RTL Fault Extraction and Test Generation,” Proc. of IEEE
and random test generation. Of the tested circuits,
                                                                   ATS-2001, Japan, Nov. 2001.
ATCLUB outperforms random test generation in general
                                                               [8] Huawei Li, Yinghua Min, and Zhongcheng Li, “Refinement
except B05 and B07. It should be noticed that B05/B07
                                                                   of Finit-State Machines,” Proc. of 7th International Conf. on
only has 1-bit wide of primary input.            Thus, the
                                                                   Computer-Aided Design and Computer Graphics, Kunming,
accessibility to the internal circuit from primary input of
                                                                   China, Aug. 2001, pp. 624-629.
B05 (or B07) is very weak. On average, ATCLUB gains
6% higher fault coverage than random test generation with
the same length of test sequence.