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					Programmable Logic Devices


                by
        Abdulqadir Alaqeeli
             1/27/98
Programmable Logic
 — Programming Methods
 — Programmable Logic Devices
    – SPLDs
    – CPLDs
    – FPGAs

Designing for FPGAs
    – Metastability
    – Synchronous Designs
    – Designing State Machine
                                2
  Programming Methods


           Programming Methods


Fuseable   EPROM     EEPROM      SRAM




                                        3
                     FUSE
 Fuses are the basic
  storage element in TTL
  programmable circuits.
 Passing a large current
  through fuse layer
  blows it. This allows
  the IC to store data by
  having the fuses
  selectively blown.


                            4
                   EPROM
 In CMOS the metal
  fuse is replaced by
  FAMOS transistor.
 By hot electron
  injection, a charge is
  placed onto the floating
  gate and switch action
  is provided.
 UV erasable.


                             5
    EEPROM and SRAM
 EEPROM
   — Electrically erasable floating gate.
   — No UV.


 SRAM
   — Loads configuration memory cells that
     control the logic and interconnect. (i.e.
     pass-transistors)
   — To erase, turn the power off.
                                                 6
Programming Technologies

 1) Bipolar fusible link
       - Closed device, burned open by high current
 2) SRAM based
       - Uses pass transistors controlled by SRAM
       - CMOS based
 3) E/EEPROM based
       - Floating gate
       - CMOS based


                                              7
Programmable Logic
      Devices
     Simple PLDs:
         – PALs
         – PLAs
         – PROMs
         – GALs
     Complex PLDs
     FPGAs


                     8
Programmable Array Logic
        PALs

  Programmable AND array.
  Fixed OR array.
  Bipolar, Fuse.
  Large number of Inputs.
  Each Output relatively independent.

                                         9
Programmable Logic Arrays
         PLAs

 Programmable AND array.
 Programmable OR array.
 Bipolar, Fuse.
 Large number of Inputs.
 Output functions share some product terms.

                                               10
    Programmable ROM
          PROM

 Fixed AND array.
 programmable OR array.
 Fuse.
 Limited number of Inputs.
 Strong independence among the Outputs.

                                           11
 PALs : most popular PLD architecture.


 PLAs : most flexible of combinatorial PLDs.


 PROMs:can be used to store any logic
  function.



                                                12
   Generic Array Logic
         GALs

 Configurable PAL-type.
 CMOS.
 Electrically Erasable CMOS technology
 Replaces many PAL devices.



                                          13
Complex Programmable Logic
         Devices
         ( CPLDs )



                         14
                   XC7300 Dual Block
                      Architecture
  Universal Interconnect Matrix
      - SMARTswitch                                  PAL-like Function Block



                          High              High
                  I/O
                         Density           Density               Input
                        Function          Function       I/O
                                                                 Registers
                          Block             Block

                                    UIM
3.3 /5 Volt I/O

                           Fast             Fast               High Drive
                  FO     Function         Function       FO
                          Block            Block
                                                               - 24 mA



              FAST                           FAST
              5 ns Pin to Pin                tSU = 4.0 ns
              fCLK =167 MHz                  tC0 = 5.5 ns
                                                                             15
XC9500 - Flexible Architecture
                      3
                            JTAG                  In-System
      JTAG Port           Controller        Programming Controller




                                                          Function
       I/O                                                 Block 1

       I/O
                                                          Function
       I/O                                                 Block 2
                               I/O     FastCONNECT
       I/O                Blocks       Switch Matrix

  Global                                                  Function
                                                           Block 3
  Clocks          3
  Global
 Set/Reset            1
                                                          Function
  Global                                                  Block n
 Tri-States
                      2 or 4




                                                                     16
       XC9500 Function Block
                                  Global     3      Global     2 or 4
                                  Clocks           Tri-State
                                                                        I/O
                                    Macrocell 1



                      Product-
              AND
                        Term
              Array
                      Allocator
     36

    From
FastCONNECT




                                    Macrocell 18                        I/O
     To
FastCONNECT



                                                                              17
XC9500 Architectural Features
 Uniform, PAL-like architecture
 Flexible function block
   —36 inputs with 18 outputs
   —Expandable to 90 product terms per macrocell
   —Product term and global 3-state enables
   —Product term and global clocks
 3.3V/5V I/O operation


                                                   18
   XC9500 Optimizes Pin-Locking

                         Add another pin
                         or FB output      Add more logic
Inputs


                                                            Fixed
                                                            Output
                            36                               Pin
                          Inputs                   D/T Q




         FastCONNECT                   Function Block
         Switch Matrix                     Logic
                         Add another FB input

                                                                     19
       XC9500 Product Family
                               0.6µ Phase I Family
             9536    9572     95108
             9536F   9572F    95108F   95144    95180      95216   95288


Macrocells    36      72       108      144          180    216     288

Usable
              800    1600      2400     3200     4000       4800    6400
Gates

tPD (ns)       5      7.5      7.5      7.5          10      10      10


Registers     36      72       108      144          180    216     288

Max. User
              34      72       108      133          168    168     192
  I/Os

Packages     44PC1
             44VQ
                     84PC1    84PC1
                     100TQ    100TQ
                     100PQ1   100PQ1   100PQ
                              160PQ1   160PQ     160PQ     160PQ
                                                 208HQ     208HQ   208HQ
                                                                   304HQ




                                                                           20
Field Programmable Gate
         Arrays
        ( FPGAs )



                          21
                                                          FPGA Architecture
                                                                                                                                   Vcc
                                                                                                            Slew        Passive
                                                                                                            Rate        Pull-Up,
                                                                                                           Control     Pull-Down
             CLB                                 CLB


                                                                                                   D   Q
                       Switch                                                                                          Output            Pad
                       Matrix                                                                                          Buffer




                                                                                                                        Input
                                                                                                                        Buffer
                                                                                                   Q   D       Delay
             CLB                                 CLB



     Programmable
                                                                                            I/O Blocks (IOBs)
      Interconnect
                         C1 C2 C3 C4

                         H1 DIN S/R EC
                                        S/R
                                       Control


G4                         DIN
G3    G                    F'
                                                         SD

G2   Func.                 G'                        D        Q

     Gen.                  H'

G1
                                                     EC
                                                       RD
                                       1

                 H         G'
                                                                  Y
               Func.       H'
                                            S/R

F4             Gen.                        Control



F3     F

                                                                      Configurable
                           DIN
     Func.                                               SD
F2   Gen.
                           F'
                           G'                        D        Q

F1                         H'



                                                     EC
                                                       RD



                                                                      Logic Blocks (CLBs)
                                       1
                           H'
                           F'
                                                                  X
K




                                                                                                                                     22
 XC4000 Configurable Logic Blocks
                                             C1 C2 C3 C4
 2 Four-input function
  generators (Look Up                        H1 DIN S/R EC
  Tables)                                                   S/R
                                                           Control



   — 16x1 RAM or G4                           DIN
                                                                             SD
                              G               F'

        Logic function G3                     G'                         D        Q   YQ
                        G2   Func.             H'
                             Gen.
 2 Registers           G1                                               EC


                                                                           RD
     - Each can be                     H       G'
                                                           1

                                                                                      Y
                                               H'
  configured as Flip                 Func                       S/R

                                     .Gen.
                                                               Control


  Flop or Latch         F4
                        F3     F              DIN
                                                                             SD
    - Independent      F2
                             Func.
                             Gen.
                                               F'
                                               G'                        D        Q   XQ
                                               H'

  clock polarity        F1
                                                                         EC
    - Synchronous                             H'
                                                           1
                                                                           RD

                                                                                      X
  and asynchronous           K
                                               F'



  Set/Reset


                                                                         23
               Look Up Tables
 Combinatorial Logic is stored in 16x1 SRAM Look Up
  Tables (LUTs) in a CLB                  Look Up Table
 Example:                              4-bit address
         Combinatorial Logic
                                        A B C D         Z
   A                                                           4
                                        0   0   0   0   0    (2 )
   B
                               Z        0   0   0   1   0   2
   C
   D
                                        0   0   1   0   0   = 64K !
                                        0   0   1   1   1
                                        0   1   0   0   1
 Capacity is limited by number of      0   1   0   1   1
  inputs, not complexity                    . . .
 Choose to use each function           1   1   0   0   0
  generator as 4 input logic (LUT) or   1   1   0   1   0
  as high speed sync.dual port          1   1   1   0   0
  RAM            WE                     1   1   1   1   1
                G4
                G3    G
                G2   Func.
                     Gen.
                G1                                             24
     ROM is Equivalent to Logic
  When using ROM, it is simply defining logic
   functions in a look-up table format
    — Memory might be an easier way to define logic
    — Xilinx provides ROM library cells
  FPGA lookup tables are essentially blocks of RAM
    — Data is written during configuration
    — Data is read after configuration
       – Effectively operate as a ROM
           As Gates                    As ROM
I1                             A0      DATA(0)=0
      F1                            F1
           O = I1*I2   X   O           DATA(1)=0 X    DOUT
I2    F2                       A1   F2 DATA(2)=0
                                       DATA(3)=1

                                                      25
RAM Provides 16X the Storage of
          Flip-Flops
 32 bits versus 2 bits of storage
   — Two 16x1 RAMS or One 32X1 Single Port
      Ram fit in one CLB
   — One 16x1 Dual Port RAM fits in one CLB
              CLB                 CLB
      D1                   D1         DQ   Q1
      A0
      A1              O1
            32 bits              2 bits
      A2                   D2        DQ    Q2
      A3
      A4

            WE                  CLK
 32x8 shift register with RAM = 11 CLBs
   — Using flip-flops, takes 128 CLBs for data alone
   — Address decoders not included
                                                    26
Using Function Generator
        As RAM




                           27
           RAM Guidelines
 Less than 32 words is best
   —32x1 or 16x2 per RAM requires only one CLB
     – Delays are short, (one level of logic)
   —Data and output MUXes are required to expand
    depth
 Less than 256 words recommended per RAM
   —Use external memory for 256 words or more
 Width easily expanded
  —Connect the address lines to multiple blocks
 Recommendation: Use less than 1/2 of max memory
  resources
   —Maximum memory uses all logic resources of
     CLBs
                                                  28
 XC4000E I/O Block Diagram
                                                              Vcc
                                       Slew        Passive
                                       Rate        Pull-Up,
                                      Control     Pull-Down


     T/OE

       O                      D   Q
                                                  Output            Pad
                                                  Buffer
OK (Output
   Clock)
       I1
                                                   Input
       I2                                          Buffer
                             Q    D       Delay
       CE
  IK (Input
    Clock)

            Elements in BLUE are not in the XC3000 family.
                                                                          29
       Xilinx FPGA Routing
 Fast Direct Interconnect - CLB to CLB
 General Purpose Interconnect - Uses switch
  matrix
  Long Lines                     CLB            CLB
    — Segmented
      across chip
                         Switch         Switch
    — Global clocks,
                         Matrix         Matrix
      lowest skew
    — 2 Tri-states per
      CLB for busses              CLB            CLB




                                                       30
   Fast Direct Interconnect

 Direct connections
  from CLB to adjacent
  CLB or IOB             CLB   CLB




 Fastest interconnect
   —Less than 1 ns
    delay                CLB   CLB




                                     31
Flexible General-Purpose Interconnect
 Flexible but slow if
  crosses many channels
 XC3000
   —5 lines per channel            CLB            CLB

 XC4000
   —8 similar Single-    Switch          Switch
    Length lines          Matrix         Matrix
   —4 Double-Length lines
    skip every other switch
    matrix                         CLB            CLB
   —4 Quadrable-Length
    Lines skip three switch
    matrices.
                                                        32
Use Long Lines for High Fanout Nets
 Single metal lines that traverse length & width of chip
 Lowest skew
 Ideal for high fan-out signals
                                   CLB               CLB
 Ideal for clocking
 Internal three-state buffers
  for buses and wide
  functions


                                   CLB               CLB




                                                            33
         CPLD or FPGA?
  CPLD                     FPGA
 Non-volatile            SRAM reconfiguration
 Wide fan-in             Excellent for computer
                           architecture, DSP,
 Fast counters, state     registered designs
  machines
                          PROM required for non-
 Combinational Logic      volatile operation




                                                  34
Designing For
  FPGAs




                35
       Avoiding Metastability
 Metastability caused by violation of timing specifications such
  as setup
 In-between state takes unknown time to resolve
    —Two destinations could be responding to different values
 Error rate decreases by a factor of 40 for every additional 1ns
  of delay before destinations respond to signal
 Be aware but not paranoid!

                         D     Q
                                       Metastable Output
         Data and Clock
         Change Simultaneously
                                                                    36
  Use Synchronous Design
 Easy to analyze internal timing of synchronous
  designs
 Hold time is not an issue
   —Clock skew is guaranteed to be much shorter
    than the minimum clock-to-Q of any CLB
 Use global clock distribution networks
   —If not, check for clock skew problems

                           2.5ns
                   D   Q           D   Q
           3.0ns           3.1ns


                                                   37
                Avoid Gated Clock or
                Asynchronous Reset
  Move gating to non-clock pin to prevent glitch from
   affecting logic
3-Bit Counter                 3-Bit Counter

  Q0                    D Q          Q0
                Carry                         Carry-1
  Q1                                 Q1                 D Q
  Q2                                 Q2




  Or separate input signal changes by at least a CLB
   delay to minimize the likelihood of a glitch


                                                              38
        Pipeline for Speed
 Register-rich FPGAs encourage pipelining
 Pipelining improves speed
   —Consider wherever latency is not an issue
   —Use for terminal counts, carry lookahead, etc.
 Clock period will be approximately
   —2 x (number of combinatorial levels) x (speed
     grade)
   —XC3100A-3: 3 levels x 2 x 3ns = 18 ns clock
     period
                                                     39
          Use Dedicated Carry for
              Large Counters
 Use XC4000/XC5000 carry logic to improve counter speed
  and density
   —Especially for counters of >5 bits
                     tADDER          tCO

                       A
                       d             R
                       d             e
                       e             g
                       r

                              tNET




                                                           40
           Use One-Hot Encoding
             for State Machines
 Shift register is always fast and dense
   —―One-hot‖ uses one flip-flop for each count
   —Useful for state machine encoding

       D   Q   D   Q   D   Q   D   Q   D   Q




 Use MooreType state machines.

                                                  41
Use LFSRs for Fixed Count
 Consider Linear Feedback Shift Register for speed when
  terminal count is all that is needed
    —Or when any regular sequence is acceptable (e.g.,
     FIFO)
 Maximal length sequence of 2n-1
 Use XNOR feedback to make lockup state all 1s

                D1
                      10-bit Shift Register
                 Q1                Q7         Q10




                                                           42
  Use Global Clock Buffers
 Use clock buffers for highest fanout clocks
   —Drive low-skew, high-speed long line resources
   —Use BUFG primitive to be family-independent
 Limit number of clocks to ease placement issues
   —XC3000: 2 (GCLK, ACLK)
   —XC4000/XC5000: 4 (BUFGP / BUFG)
 Additional clocks might be routable on long lines
   —Otherwise routed on general interconnect
       –Slower and higher skew


                                                      43
Using a Clock Generated Off-Chip

 Connect IPAD directly to clock buffer
  primitive
   —Required for BUFGP
 Provides higher speed and uses fewer routing
  resources
                               D
            IPAD
                      BUFG




                                                 44
Generating Clock On-Chip
 XC4000
   —Internal clock available
    after configuration
   —Use OSC4 primitive
                               F8M

                               F500k
                                       BUFGS
                        OSC4   F16k

                               F490

                               F15

                                         45
        Use Clock Enables Instead
             of Gating Clock
 Use clock enable when using              FDxE
  most of or all logic inputs
   —Not recommended to gate                D   Q
       clock signal directly
                                      CE

 Use muxed data when using
  only 1-2 logic inputs
                                               D   Q
   —Easier to route
 Some macros use logic for clock        CE
  enable while others use the CE pin
   —Make sure CE, if unused, is always connected to VCC

                                                          46

				
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