PROGRAMMABLE LOGIC DEVICES (PLD)
PLDs are programmable standard parts which serve to replace several SSI and
MSI logic chips. The functionality of a PLD is determined by selective
connections in a logic matrix. The process of defining those connections is
called customization (programming).
Types of PLDs:
PROM - programmable read only memory
EPROM - erasable PROM
IFL - integrated array logic
PAL - programmable array logic
PMUX - programmable multiplexer
Conceptually, all of them are similar (except PMUX) but different in the
degree of flexibility in implementing logic.
CHARACTERISTICS OF PLDS
1. digital logic devices
2. programming is achieved by electrical means
3. functions are defined in terms of sum-of-products
4. limited input variables
5. limited output variables
6. density of function is equivalent to several SSI or MSI logic chips
7. performance is poor as compared with other ASIC technologies
8. not suitable to use as a direct replacement of standard components in
existing designs. Should be chosen in the early stage of a design for the
2. quick turnaround
3. low development cost
4. no special expertise required
5. does not involve any processing step in customization
6. sell as standard components
The majority of PLDs are based on array logic. The simplest form of array
logic structure is the diode matrix.
Two-level logic (AND-OR)
A memory device is converted to perform combinational logic function.
ADDRESS input input variables
DATA output output variables
The device is divided into two logic matrices:
Generate all product terms.
e.g. 4 input variables
There will be 16 4-input AND gates in the AND matrix
The full set of product terms is ORed.
Number of OR gates depends on number of output variables.
Number of inputs to each OR gate is determined by the number of AND
gates (product terms) in the AND matrix.
e.g. 4 input variables
16-input OR gate
For each output, any Boolean function can be generated by connecting the
required product terms to the corresponding OR gate. All input variables must
be defined in the expression eventhough some of them are redundant.
e.g. F = AB
For A 3-1 PROM
O = AB(C+C)
O = ABC+ABC
Two product terms in canonical form are connected to the OR gate.
THE MATRIX STRUCTURE IN PROM
1. only a portion of product terms is utilized
2. long programming time
3. wasteful of silicon
Erasible PROM available allows modification even after customization.
First introduced by Monolithic Memory Incorporated.
AND matrix – programmable to generate any product term as required
OR matrix - fixed
Number of inputs to OR gates varies from one type of PAL to another.
Although PAL is a trademark. This term is often used to refer to PLDs with
fixed OR matrix. Other vendors use terms like GAL (Lattice Logic) or simply
GENERIC PAL CONFIGURATION
To achieve the capability and to suit different applications, different PALs are
devised based on the generic configuration. The variations are achieved by
adding additional logic to the fixed OR gates, and in clocking scheme and
CONFIGURATION WITH REGISTERS
Additional D-types at each output lines.
All D-type latch in data on the same clock edge.
Outputs are fedback as input lines.
Very useful in implementing synchronous state machine.
CONFIGURATION WITH EXOR GATE
Sum of products is segmented into two, which are then XORed to D-type. This
allows carries from previous operations to be XORed with sum generated by
This facilitates arithmetic functions, ADD, SUBSTRACT etc.
Extra flexibility is gained by gating feedback paths and inputs.
Modern PLDs are not made from diode matrices; their circuit development has
closely followed that of semiconductor memory technology. Apart from using
fuses or transistor which can be broken down by avalanche-induced migration,
erasible memory technology has been adopted more and more.
EPROM technology to realize AND array
The AND logic is implemented by OR logic since
The floating gate transistor:
Normally the floating gate transistors can be switched. After the injection of
charges, the transistor can not be switched and remains off. Thus, the
corresponding input is effectively isolated from the wired-OR structure.
PAL DESIGN PROCEDURE
SETUP LOGIC EQUATIONS
SELECT THE RIGHT PAL
CREATE BIT PATTERN
LOAD PATTERN INTO PROGRAMMER
PROGRAM ARRAY MARTIX
VERIFY ARRAY MATRIX
CHECK PAL FUNCITON
In earlier days, engineers had to create manually a text file of tabular
equivalent defining the connections in the programmable matrix.
Specification languages – rudimentary HDL and software application
PALASM 2 - from Monolithic Memories
Boolean form of description corresponds to each output
support state machine description
CUPL from Assisted Technology
ABEL from Data I/O
Gate Array is an integrated circuit which has gone through the majority of the
processing steps but the final metallization stage.
Prefabricated structure contains many unconnected active and passive
components which are organized in an array of identical cells.
Customization is the process to define interconnections between these
Therefore, foundry service is required to achieve the customization. However,
the layout can be done without processing knowledge.
Gate Array is a contracting market, only a few semi-conductor vendors still
offer Gate Array products with limited options and designed in less advanced
In the past, all types of logic techniques were employed in Gate Array, CML,
ECL, CMOS, BiCMOS… Today, only CMOS is likely to be employed.
- limit on number of gates
- limit on number of bond pads
- performance characteristics are pre-determined
- customization only involves one or two masks for interconnections
- metal tracks are routed on a grid system
- interfacing to other devices is not flexible
- higher order functions are created from primitive gates
- uncommitted wafers are stock-piled to achieve economy of scale
- turnaround time is in weeks
One current Gate Array product:
Fujitsu CG61 series manufactured in 0.35um process offered up to 1.5million
gates operated under a single power supply from 3.3V to 2V.
How cells are organized.
There are three recognized types of architectures.
Block type architecture was used in many early generation of gate arrays when
the CAD tools available were primitive and double-layer metal process was
expensive. Block type architecture allows more freedom in routing
interconnections. With clever arrangement, only one layer of metal can
achieve very high density interconnection which is usually done manually.
With larger and larger array sizes, block type architecture has given way to
channel type architecture which facilitates design automation hence shorter
The main characteristic is rows/columns of logic cells separated by dedicated
routing areas. Routings are achieved by two layers of metal. One metal layer is
dedicated for x-direction of routing and the other layer for y-direction of
routing. Connections between the two metal layers are made by holes, called
vias, in the insulation layer between the metal layers.
Channel type suffers from bad silicon utilization.
generous allocation of routing areas as much as 50% of the total die area
inefficiency in implementing mega functions, such as multipliers, RAM,
which are broken at regular interval by the routing areas.
The core area contains a regular pattern of uninterrupted logic cells.
Interconnections are achieved by routing over unused cells. As a result,
channeless architecture requires at least one more customization layer, the
In older process technologies which provide only a limited number of metal
layers, the core area is usually ‘channelized’ first during the customization
process, allocating routing areas on unused cells. Then the cells can be
connected as in the channel type array.
In today’s processes which provide multi-layers of routing metal, inter-cell
connections can be realized using higher metal layers. As a result, all logic
cells can be used to implement logic with interconnect channels running
directly over the cells. Routing channels are now located on top of cells rather
than on dedicated areas between cells, so lead to higher utilization.
The most significant advantage of channeless architecture is the ability to
dedicate a section of closely packed cells to form mega functions which can
have performance close to a cell-based design.
Structure influenced by
The majority of gate arrays have simple cell which contains components to
create one or two 2-input primitive gates.
This choice has the advantages of
efficient in silicon usage
Some arrays called macrocell has very large cell which has enough
components to create higher order functions such as flip-flops, adders
tend to have more unused components
tend to have less interconnections between cells
FERRANTI C-SERIES ULA (UNCOMMITTED LOGIC ARRAY)
Matrix cells (logic cells) surrounded by peripheral cells on all sides.
In the C-series, there are several versions available to cater for different
requirements such as performance, gate count.
225 cells 440 cells
ULA2C000 ULA2N000 ULA5C000 ULA5N000
gate delay 9ns 25ns 9ns 25ns
gate power 0.25mW 70W 0.25mW 70W
MATRIX CELL LAYOUT
4 gate transistors
1 current source transistor
2 load resistors
1 current source resistor
3 pre-fixed cross-unders
Within the cell, there is access to Vs, supply voltage and ground, GND.
Gate transistors are grouped in pairs with common collector. Each transistor
has multiple collector contacts to facilitate routing.
Mainly for implementing I/O buffer and bond pad for connection with package.
Input buffer: TTL, CMOS interfacing
Output buffer: TTL CMOS interfacing
The cell can also be wired to form:
The cell logic capability is two 2-input NOR gates. The current source
transistor provides two independent current sources.
CML NOR gate:
Tracks are required to run on a grid system with grid points falling on contacts.
MICRO CIRCUIT ENGINEERING CMOS GATE ARRAY
Polysilicon gate technology.
Single layer metal
2 pMOS and 2 nMOS transistors
same transistor type has common drain or source
different transistor type has common gate
cell has 2-input NAND/NOR gate capability
supply rails running through the cell
cell internal connections are between supply rails
cell terminals are on two sides of the cell (top and bottom)
Implement I/O buffer.
interfacing with TTL logic
pull-up resistor available
can be wired to form schmitt trigger
Channel has pre-fixed polysilicon used as cross-unders
Metal tracks are routed over these cross-unders and between cross-under
The channel as shown can accommodate 10 metal tracks
Some cross-unders are extension of gate inputs of transistors in the cell
SPEC SHEET FOR DIFFERENT GATES IN LIBRARY
PROPAGATION DELAY EVALUATION
Delay through a gate
= no load + (n x Dld)
n - number of equivalent load
Dld - load delay factor associated with the gate concerned
On the spec sheet, equivalent load and Dld are defined for each gate type.
Since all transistors have identical channel dimension, the pull-up and pull-
down delays are different. Thus there are two no load figures for each gate type.
Track capacitance will be specified in terms of equivalent load.
To implement design on this array, library macros should be used to realize
higher order functions.
The timing characteristics quoted are nominal values at 5V and at 25C. There
timings will vary due to changes in supply voltage and temperature and also
from batch to batch of silicon.
Allowing processing tolerance:
maximum delay = 1.7 x nominal delay
There is no dedicated regulation system or special supply to the array. VDD is
directly taken from the chip supply pin.