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Implementation of Direct Processor Access in Transient Faulty Nodes


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									                                                           (IJCSIS) International Journal of Computer Science and Information Security,
                                                           Vol. 9, No. 4, April 2011

          Implementation of Direct Processor Access in
                       Transient Nodes

P. S. BALAMURUGAN,                                                           K.THANUSHKODI,
Research Scholar ,                                                           Director ,

Anna University of Technology,                                               Akshaya College of Engineering and Technology,

Coimbatore .                                                                 Coimbatore.

Abstract- Wireless sensor networks faces a number of                       The failure of sensor nodes should not affect the overall task
challenges; a wireless sensor network which includes a number              of the sensor network.
of sensor nodes must provide reliability and fault tolerance
against a number of odds such as scalability, hardware,
environmental conditions, power and energy factors. In this                A. Challenges of Wireless Sensor Networks
paper, we address these two issues of Reliability and Fault
Tolerance using mirror nodes. We demonstrate that increased                In monitoring sensor networks, data coming from various
reliability can be achieved by using mirror nodes and the costs            streams of the sensor nodes have to be examined
could be maintained by implementing the Direct Processor                   dynamically and combined into normal patterns in order to
Access(DPA). Experimental results on the benchmarks data set
show that our proposed system based on Direct Processor                    detect potential anomalies. Due to the requirement for the
Access outperforms the other well-known methods such as the                support of mission critical applications in many cases, the
Distributed Deviation Detection, Distributed anomaly                       sensors must possess mechanisms for securing
detection, Intrusion detection for routing attacks, Statistical en
route filtering and Abnormal Relationship Tests(ART). The
                                                                           communications and for validating the collected data.
improvement in performance using DPA is very high,                         Several attack scenarios that exploit the weaknesses of
particularly, for the graphical and network processes (6.8                 WSNs has been identified and the scale of deployments of
percent improvement). Statistical Tests also demonstrate                   WSNs requires careful decisions and tradeoffs among
higher fault tolerance and improvement in performance for
our method. Finally, we show that our system is robust and is              various security measures. These issues are taken into
able to handle faulty sensor nodes without compromising                    consideration and mechanisms to achieve a higher level of
performance.                                                               security and reliability has been proposed in these networks.
Keywords -Wireless Sensor Networks,;Faulty Sensor Nodes;
                                                                             II. WIRELESS SENSOR NETWORK WITH MIRROR
Fault Tolerance; Direct Processor Access ;Mirror Nodes
                    I. INTRODUCTION
A wireless sensor network (WSN) is a collection of nodes                   In this investigation, we assign a mirror node for each
organized in a network where each node consists of one or                  master node. At a time only a single node will be activated,
more microcontrollers, CPU’s or DSP chips, a memory and                    either master node or mirror node. The mirror node will be
a RF transceiver, a power source such as battery. It also                  in active state only in the absence of the master node.
accommodates various sensors and actuators. The nodes                      Whenever master node is identified as faulty node, the
communicate without wire (wireless) and often organize
                                                                           primary node will activate the mirror node and isolate the
itself after being deployed in an ad hoc fashion . The
intrinsic properties of individual sensor nodes pose                       master node from the sensor network. This process helps to
additional challenges to the communication protocols in                    improve the availability of the sensor networks during
terms of energy consumption.                                               threats and disaster and its performance is shown in Fig 1.
              The reliability or fault tolerance is yet another
issue. Some sensor nodes may fail or be blocked due to lack
of power, physical damage or environmental interference.

                                                                                                      ISSN 1947-5500
                                                                  (IJCSIS) International Journal of Computer Science and Information Security,
                                                                  Vol. 9, No. 4, April 2011

TABLE 1: PERFORMANCE OF SENSOR NETWORK WITH MIRROR                               If the cost of the network is more expensive than deploying
                       NODES                                                     traditional sensors, then the sensor network is not cost
                                                                                 justified. we have formulated two approaches for allocating
  Data Transmission rate in       Data Transmission rate in
                                                                                 monitor node for a cluster. Clustering can be structured
  sensor network with             sensor network without
  mirror nodes (MB/ s)            mirror nodes(MB/s)
                                                                                 asymmetrically or symmetrically. In asymmetric clustering,
                                                                                 one machine is in non dedicated mode while the other is
                 0.2              0.1                                            acquiring real time data. The non dedicated host does
                                                                                 nothing but simply monitors the remaining nodes in the
                 0.4              0.22                                           cluster. If any node fails, then the non dedicated host
                                                                                 becomes the active node. In the second approach, two or
                 0.45             0.33
                                                                                 more hosts are monitoring each other. If any node in the co-
                 0.52             0.34                                           operating system fails, then the monitoring nodes share the
                                                                                 workload of faulty nodes among them. These approaches
                 0.56             0.41                                           are useful where maximum reliability and availability are
                                                                                 required and its performance is shown in fig 3.
                 0.59             0.42
                                                                                       TABLE 2: PERFORMANCE OF SENSOR NETWORK WITH
                 0.61             0.43
                                                                                                    ASYNCHRONOUS MIRROR NODES
                 0.67             0.46
                                                                                   Data Transmission rate in sensor        Data Transmission     rate in
                 0.69             0.51                                             network with     Asynchronous           sensor network without Mirror
                                                                                   mirror (MB/s)                           nodes (MB/ s)
                 0.74             0.52
                                                                                                    0.19                   0.1
                 0.78             0.54
                                                                                                    0.35                   0.22

                                                                                                    0.412                  0.33

      0.9                                                                                           0.452                  0.34

                                                                                                    0.516                  0.41

      0.5                                                 eie 1
                                                         Sr s
      0.4                                                 eie 2
                                                         Sr s                                       0.58                   0.42

                                                                                                    0.59                   0.43

            1s         3s   5s   7s      9s   11s                                                   0.64                   0.46

                                                                                                    0.656                  0.51
      Figure 1:Performance of sensor network with mirror nodes
                                                                                                    0.714                  0.52
In the previous investigation, the availability of the sensor
                                                                                                    0.728                  0.54
networks was increased to the optimum level. But the
sensor networks consist of a large number of sensor nodes                                           0.781                  0.56
and implanting a mirror node for each individual sensor
node will increase the overall cost of the networks.

                                                                                              0.5                                              Series1
                                                                                              0.4                                              Series2
                                                                                                    1 s     3s   5s   7s    9s    11 s

   Figure 2: Structure of Sensor node with asynchronous mirror node
                                                                                         Figure 3: Performance graph for asymmetric mirror nodes

                                                                                                                 ISSN 1947-5500
                                                                      (IJCSIS) International Journal of Computer Science and Information Security,
                                                                      Vol. 9, No. 4, April 2011

TABLE 3: COMPARISON OF TIME DELAY FOR A SENSOR                                       processor can access the data and codes easily, by searching
 NETWORK WITH ASYNCHRONOUS MIRROR NODE AND                                           in the specified memory location. By this procedure the
                        WITHOUT MIRROR NODE                                          value n will not represent the total cache memory space but
                                                                                     it will represent only the value of an array. When a program
 Time delay for a sensor              Time delay for a sensor                        needs more memory space than the allotted memory by
 network without mirror in            network with asynchronous                      using artificial intelligence we can combine the memory and
 sensor network (ns)                  mirror in sensor network (ns)                  utilize it to execute the program. The process of combining
                 0.2                                  0.1                            memory can be done by calculating the frequently used
                                                                                     program or FIFO method. This method is highly applicable
                0.31                               0.23                              when we need to run a program which needs memory space
                0.42                               0.28                              less than n/11 in a high RAM capacity machine. In this
                                                                                     methodology the work of the processor is simplified by
                0.46                               0.31
                                                                                     allowing it to search in the allotted array.
                0.51                              0.344

                0.62                               0.38
                                                                                                                   Array Methodology
                0.74                               0.51
                                                                                                                   Co – Processor (DSP)
                0.89                               0.64

                0.916                                 0.7

                                                                                                                        Processor unit
                                                                                               CD Drive
                                                                                                                    (Multi core Processor)



          0.5                                                e s1
                                                            S rie
          0.4                                                e s2
                                                            S rie                                                  Array Methodology


          0.1                                                                                                      (FPGA)
                 1 ns     3ns   5ns      7ns    9ns

Figre 4: Time delay for a sensor network having mirror node and without                 Figure 5: Block Diagram of Array methodology Based Co - Processor
                               mirror node                                                                            Design

      From these comparisons we could conclude that                                  Another important concern that influences the processor
introducing mirror nodes will obviously improve the                                  performance is the heat sink designed for the IC and the
performance of sensor networks. Hence sensor networks                                design has to be chosen between its size and performance.
with mirror nodes can be implemented in real time systems                            The impact of CMOS technologies on substrate and metal
where time constraints are strictly followed and cost factor                         line temperatures have resulted in improved reliability and
is not an issue.                                                                     better performance of the devices and interconnections. 74
                                                                                     % of processor failures are due to thermal factors and high
                        III. DPA in Sensor Network                                   power sources such as power dissipation, temperature
                                                                                     relation, a method for full chip temperature calculation and
To increase the accessing speed and to attain an efficient                           implications on the design of high performance low power
memory access, a new methodology is employed in the                                  VLSI circuits. By spacing the memory in an array manner,
proposed system. The methodology is termed as Array                                  the cache port’s accessibility could be improved. This can
Methodology. By this methodology the processor will                                  be known from the percentage of hit ratio tabulated for the
interact with the RAM device in an array fashion by which                            different programs.
the RAM will be divided into arrays and each array will be
allotted for a default program to be utilized. Thus the

                                                                                                                  ISSN 1947-5500
                                                        (IJCSIS) International Journal of Computer Science and Information Security,
                                                        Vol. 9, No. 4, April 2011

In the existing system, the faulty node is identified and              work with these extreme numbers of nodes. Since the sensor
isolated from the network by using the statistically available         networks consist of a large number of sensor nodes, the cost
tools. The erroneous data due to faulty nodes may become               of a single node is very important to justify the overall cost
an issue if any real time system does depend on the output             of the networks. If the cost of the network is more
of sensor. The delay or erroneous data will become a hectic            expensive than deploying traditional sensors, then the
issue where small delays or erroneous data will result the             sensor network is not cost justified. As a result, the cost of
entire system to get fail. Moreover in real time applications,         each sensor node has to be kept low which results in low
several hundreds to thousands of nodes are deployed                    quality sensors to be deployed and hence results in less
throughout the sensor field. The introduction of a mirror              performance.
node to each cluster of nodes will increase the total number
of nodes to maximum. So instead of going for a separate                IV. CONCLUSION
node for each cluster, we intend to use Direct Processor
Access (DPA) as mirror node so as to utilize the sensor                From the above results, we arrive at a conclusion that the
node to perform the sensor related task and console                    introduction of mirror node either to a cluster of nodes or to
application task simultaneously. Also more number of                   each sensor node will result in increasing the performance
processors could be embedded in the DPA in executing the               of the sensor network and also the availability is increased
console and real time applications thus improving
                                                                       to a maximum level. The method of introducing mirror node
parallelism. There incurred some overhead while
implementing multi core processors within a system                     for each sensor node is not suitable for commercial
because of high IO and context switch between the                      application due to high cost factor. In systems where cost
processors for resources. The DPA should also be designed              factor is an issue the later can be opted to improve the
in such a way that should control the remaining processors             performance of the system. To overcome the difficulty that
in the sensor networks. Moreover security issues must be               incurred due to high cost, we proposed a system, where a
considered while implementing multiple processors in DPA,              single node (DPA) is allocated for monitoring the remaining
as it belongs to a network leading to more possibilities for
                                                                       nodes in the cluster. If any of the monitored nodes produced
security threats. The performance of sensor networks has
been increased by implementing DPA as mirror nodes and                 anomalous data, then the faulty node would be isolated from
by utilizing FPGA and DSP Processor in DPA.                            the network and the monitoring node will take charge
                                                                       performing the tasks that needs to be done by the faulty
The hit ratio in a non-dedicated multi processor is                    node. Thus implementing substitute node for each cluster
comparatively higher than that of a single processor and the           will improve the reliability of the sensor network and makes
accessing time is efficient for a program which has a
                                                                       the sensor to work more efficiently in real time systems
minimum capacity of Random Access Memory. In our
proposed system the mirror node is replaced by a FPGA                  where strict constraints are followed to make the system
processor in the network so that the sensor node will                  work correctly.
perform more than one task simultaneously. One is to gather
data and that task depends on the application of sensor                This proposed system is designed for a static sensor
network. The other task is to monitor the remaining nodes in           network. It makes use of substitution nodes to ensure
the network. Hence the cost to mirror node ratio will                  continuous flow of data even in case of base node failure.
decrease drastically and also the performance of the sensor            Also work can be done by using a scalable network to
network will increase to the optimum level because of
                                                                       increase the performance. Cloud computing could also be
parallel processing done by FPGA. In addition to the
monitoring task, FPGA can also perform some application                made use of, which offers many benefits, such as flexibility
specific tasks during its leisure time. By making FPGA                 and instant access to the latest data and applications. But
processor to execute some application specific tasks, it               there are also risks, such as the dependency on high
always stays in the busy state and never remains idle. Hence           availability, high performance network connections, and not
by implanting FPGA processor in sensor node, console                   to forget about the least security and privacy.
application as well as sensor specific tasks could be done in
parallel. We propose a new approach in which data gathered
from sensor nodes are shared among different computers in                                       REFERENCES
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                                                                                                   ISSN 1947-5500
                                                                      (IJCSIS) International Journal of Computer Science and Information Security,
                                                                      Vol. 9, No. 4, April 2011

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                                                                                                                   ISSN 1947-5500

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